pred.isa revision 8518
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// Predicated Instruction Execution 46// 47 48let {{ 49 predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)' 50 condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)' 51}}; 52 53def template DataImmDeclare {{ 54class %(class_name)s : public %(base_class)s 55{ 56 public: 57 // Constructor 58 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 59 IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 60 %(BasicExecDeclare)s 61}; 62}}; 63 64def template DataImmConstructor {{ 65 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 66 IntRegIndex _dest, 67 IntRegIndex _op1, 68 uint32_t _imm, 69 bool _rotC) 70 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 71 _dest, _op1, _imm, _rotC) 72 { 73 %(constructor)s; 74 if (!(condCode == COND_AL || condCode == COND_UC)) { 75 for (int x = 0; x < _numDestRegs; x++) { 76 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 77 } 78 } 79 } 80}}; 81 82def template DataRegDeclare {{ 83class %(class_name)s : public %(base_class)s 84{ 85 public: 86 // Constructor 87 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 88 IntRegIndex _op1, IntRegIndex _op2, 89 int32_t _shiftAmt, ArmShiftType _shiftType); 90 %(BasicExecDeclare)s 91}; 92}}; 93 94def template DataRegConstructor {{ 95 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 96 IntRegIndex _dest, 97 IntRegIndex _op1, 98 IntRegIndex _op2, 99 int32_t _shiftAmt, 100 ArmShiftType _shiftType) 101 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 102 _dest, _op1, _op2, _shiftAmt, _shiftType) 103 { 104 %(constructor)s; 105 if (!(condCode == COND_AL || condCode == COND_UC)) { 106 for (int x = 0; x < _numDestRegs; x++) { 107 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 108 } 109 } 110 111 if (%(is_branch)s){ 112 flags[IsControl] = true; 113 flags[IsIndirectControl] = true; 114 if (condCode == COND_AL || condCode == COND_UC) 115 flags[IsCondControl] = true; 116 else 117 flags[IsUncondControl] = true; 118 } 119 120 if (%(is_ras_pop)s) { 121 flags[IsReturn] = true; 122 } 123 } 124}}; 125 126def template DataRegRegDeclare {{ 127class %(class_name)s : public %(base_class)s 128{ 129 public: 130 // Constructor 131 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 132 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 133 ArmShiftType _shiftType); 134 %(BasicExecDeclare)s 135}; 136}}; 137 138def template DataRegRegConstructor {{ 139 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 140 IntRegIndex _dest, 141 IntRegIndex _op1, 142 IntRegIndex _op2, 143 IntRegIndex _shift, 144 ArmShiftType _shiftType) 145 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 146 _dest, _op1, _op2, _shift, _shiftType) 147 { 148 %(constructor)s; 149 if (!(condCode == COND_AL || condCode == COND_UC)) { 150 for (int x = 0; x < _numDestRegs; x++) { 151 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 152 } 153 } 154 } 155}}; 156 157def template PredOpExecute {{ 158 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 159 { 160 Fault fault = NoFault; 161 uint64_t resTemp = 0; 162 resTemp = resTemp; 163 %(op_decl)s; 164 %(op_rd)s; 165 166 if (%(predicate_test)s) 167 { 168 %(code)s; 169 if (fault == NoFault) 170 { 171 %(op_wb)s; 172 } 173 } else { 174 xc->setPredicate(false); 175 } 176 177 return fault; 178 } 179}}; 180 181def template QuiescePredOpExecute {{ 182 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 183 { 184 Fault fault = NoFault; 185 uint64_t resTemp = 0; 186 resTemp = resTemp; 187 %(op_decl)s; 188 %(op_rd)s; 189 190 if (%(predicate_test)s) 191 { 192 %(code)s; 193 if (fault == NoFault) 194 { 195 %(op_wb)s; 196 } 197 } else { 198 xc->setPredicate(false); 199#if FULL_SYSTEM 200 PseudoInst::quiesceSkip(xc->tcBase()); 201#endif 202 } 203 204 return fault; 205 } 206}}; 207 208def template QuiescePredOpExecuteWithFixup {{ 209 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 210 { 211 Fault fault = NoFault; 212 uint64_t resTemp = 0; 213 resTemp = resTemp; 214 %(op_decl)s; 215 %(op_rd)s; 216 217 if (%(predicate_test)s) 218 { 219 %(code)s; 220 if (fault == NoFault) 221 { 222 %(op_wb)s; 223 } 224 } else { 225 xc->setPredicate(false); 226 %(pred_fixup)s; 227#if FULL_SYSTEM 228 PseudoInst::quiesceSkip(xc->tcBase()); 229#endif 230 } 231 232 return fault; 233 } 234}}; 235 236def template DataDecode {{ 237 if (machInst.opcode4 == 0) { 238 if (machInst.sField == 0) 239 return new %(class_name)sImm(machInst); 240 else 241 return new %(class_name)sImmCc(machInst); 242 } else { 243 if (machInst.sField == 0) 244 return new %(class_name)s(machInst); 245 else 246 return new %(class_name)sCc(machInst); 247 } 248}}; 249 250def template DataImmDecode {{ 251 if (machInst.sField == 0) 252 return new %(class_name)s(machInst); 253 else 254 return new %(class_name)sCc(machInst); 255}}; 256