xref: /gem5/src/arch/arm/isa/templates/pred.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
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// property including but not limited to intellectual property relating
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// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
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// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
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// neither the name of the copyright holders nor the names of its
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// this software without specific prior written permission.
//
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Predicated Instruction Execution
//

let {{
    predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)'
    condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)'
}};

def template DataImmDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
        %(BasicExecDeclare)s
};
}};

def template DataImmConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          uint32_t _imm,
                                          bool _rotC)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm, _rotC)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template DataRegDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, IntRegIndex _op2,
                int32_t _shiftAmt, ArmShiftType _shiftType);
        %(BasicExecDeclare)s
};
}};

def template DataRegConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          int32_t _shiftAmt,
                                          ArmShiftType _shiftType)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _shiftAmt, _shiftType)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }

        if (%(is_branch)s){
            flags[IsControl] = true;
            flags[IsIndirectControl] = true;
            if (condCode == COND_AL || condCode == COND_UC)
                flags[IsUncondControl] = true;
            else
                flags[IsCondControl] = true;

            if (%(is_ras_pop)s) {
                flags[IsReturn] = true;
            }
        }

    }
}};

def template DataRegRegDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
                ArmShiftType _shiftType);
        %(BasicExecDeclare)s
};
}};

def template DataRegRegConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          IntRegIndex _shift,
                                          ArmShiftType _shiftType)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _shift, _shiftType)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
        }
    }
}};

def template PredOpExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;
        uint64_t resTemp = 0;
        resTemp = resTemp;
        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            %(code)s;
            if (fault == NoFault)
            {
                %(op_wb)s;
            }
        } else {
            xc->setPredicate(false);
        }

        return fault;
    }
}};

def template QuiescePredOpExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;
        uint64_t resTemp = 0;
        resTemp = resTemp;
        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            %(code)s;
            if (fault == NoFault)
            {
                %(op_wb)s;
            }
        } else {
            xc->setPredicate(false);
            PseudoInst::quiesceSkip(xc->tcBase());
        }

        return fault;
    }
}};

def template QuiescePredOpExecuteWithFixup {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;
        uint64_t resTemp = 0;
        resTemp = resTemp;
        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            %(code)s;
            if (fault == NoFault)
            {
                %(op_wb)s;
            }
        } else {
            xc->setPredicate(false);
            %(pred_fixup)s;
            PseudoInst::quiesceSkip(xc->tcBase());
        }

        return fault;
    }
}};

def template DataDecode {{
    if (machInst.opcode4 == 0) {
        if (machInst.sField == 0)
            return new %(class_name)sImm(machInst);
        else
            return new %(class_name)sImmCc(machInst);
    } else {
        if (machInst.sField == 0)
            return new %(class_name)s(machInst);
        else
            return new %(class_name)sCc(machInst);
    }
}};

def template DataImmDecode {{
    if (machInst.sField == 0)
        return new %(class_name)s(machInst);
    else
        return new %(class_name)sCc(machInst);
}};