pred.isa revision 7597
16019SN/A// -*- mode:c++ -*- 26019SN/A 37110SN/A// Copyright (c) 2010 ARM Limited 47110SN/A// All rights reserved 57110SN/A// 67110SN/A// The license below extends only to copyright in the software and shall 77110SN/A// not be construed as granting a license to any other intellectual 87110SN/A// property including but not limited to intellectual property relating 97110SN/A// to a hardware implementation of the functionality of the software 107110SN/A// licensed hereunder. You may use the software subject to the license 117110SN/A// terms below provided that you ensure that this notice is replicated 127110SN/A// unmodified and in its entirety in all distributions of the software, 137110SN/A// modified or unmodified, in source code or in binary form. 147110SN/A// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426019SN/A 436019SN/A//////////////////////////////////////////////////////////////////// 446019SN/A// 456019SN/A// Predicated Instruction Execution 466019SN/A// 476019SN/A 486243SN/Alet {{ 497422Sgblack@eecs.umich.edu predicateTest = 'testPredicate(OptCondCodes, condCode)' 507422Sgblack@eecs.umich.edu condPredicateTest = 'testPredicate(CondCodes, condCode)' 516243SN/A}}; 526243SN/A 537138Sgblack@eecs.umich.edudef template DataImmDeclare {{ 547138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 557138Sgblack@eecs.umich.edu{ 567138Sgblack@eecs.umich.edu public: 577138Sgblack@eecs.umich.edu // Constructor 587138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 597138Sgblack@eecs.umich.edu IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 607138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 617138Sgblack@eecs.umich.edu}; 627138Sgblack@eecs.umich.edu}}; 637138Sgblack@eecs.umich.edu 647138Sgblack@eecs.umich.edudef template DataImmConstructor {{ 657138Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 667138Sgblack@eecs.umich.edu IntRegIndex _dest, 677138Sgblack@eecs.umich.edu IntRegIndex _op1, 687138Sgblack@eecs.umich.edu uint32_t _imm, 697138Sgblack@eecs.umich.edu bool _rotC) 707138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 717138Sgblack@eecs.umich.edu _dest, _op1, _imm, _rotC) 727138Sgblack@eecs.umich.edu { 737138Sgblack@eecs.umich.edu %(constructor)s; 747138Sgblack@eecs.umich.edu } 757138Sgblack@eecs.umich.edu}}; 767138Sgblack@eecs.umich.edu 777138Sgblack@eecs.umich.edudef template DataRegDeclare {{ 787138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 797138Sgblack@eecs.umich.edu{ 807138Sgblack@eecs.umich.edu public: 817138Sgblack@eecs.umich.edu // Constructor 827138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 837138Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, 847138Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType); 857138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 867138Sgblack@eecs.umich.edu}; 877138Sgblack@eecs.umich.edu}}; 887138Sgblack@eecs.umich.edu 897138Sgblack@eecs.umich.edudef template DataRegConstructor {{ 907138Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 917138Sgblack@eecs.umich.edu IntRegIndex _dest, 927138Sgblack@eecs.umich.edu IntRegIndex _op1, 937138Sgblack@eecs.umich.edu IntRegIndex _op2, 947138Sgblack@eecs.umich.edu int32_t _shiftAmt, 957138Sgblack@eecs.umich.edu ArmShiftType _shiftType) 967138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 977138Sgblack@eecs.umich.edu _dest, _op1, _op2, _shiftAmt, _shiftType) 987138Sgblack@eecs.umich.edu { 997138Sgblack@eecs.umich.edu %(constructor)s; 1007138Sgblack@eecs.umich.edu } 1017138Sgblack@eecs.umich.edu}}; 1027138Sgblack@eecs.umich.edu 1037138Sgblack@eecs.umich.edudef template DataRegRegDeclare {{ 1047138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1057138Sgblack@eecs.umich.edu{ 1067138Sgblack@eecs.umich.edu public: 1077138Sgblack@eecs.umich.edu // Constructor 1087138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 1097138Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 1107138Sgblack@eecs.umich.edu ArmShiftType _shiftType); 1117138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1127138Sgblack@eecs.umich.edu}; 1137138Sgblack@eecs.umich.edu}}; 1147138Sgblack@eecs.umich.edu 1157138Sgblack@eecs.umich.edudef template DataRegRegConstructor {{ 1167138Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1177138Sgblack@eecs.umich.edu IntRegIndex _dest, 1187138Sgblack@eecs.umich.edu IntRegIndex _op1, 1197138Sgblack@eecs.umich.edu IntRegIndex _op2, 1207138Sgblack@eecs.umich.edu IntRegIndex _shift, 1217138Sgblack@eecs.umich.edu ArmShiftType _shiftType) 1227138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1237138Sgblack@eecs.umich.edu _dest, _op1, _op2, _shift, _shiftType) 1247138Sgblack@eecs.umich.edu { 1257138Sgblack@eecs.umich.edu %(constructor)s; 1267138Sgblack@eecs.umich.edu } 1277138Sgblack@eecs.umich.edu}}; 1287138Sgblack@eecs.umich.edu 1296019SN/Adef template PredOpExecute {{ 1306019SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1316019SN/A { 1326019SN/A Fault fault = NoFault; 1336271SN/A uint64_t resTemp = 0; 1346271SN/A resTemp = resTemp; 1356019SN/A %(op_decl)s; 1366019SN/A %(op_rd)s; 1376019SN/A 1386243SN/A if (%(predicate_test)s) 1396019SN/A { 1406243SN/A %(code)s; 1416019SN/A if (fault == NoFault) 1426019SN/A { 1436019SN/A %(op_wb)s; 1446019SN/A } 1457597Sminkyu.jeong@arm.com } else { 1467597Sminkyu.jeong@arm.com xc->setPredicate(false); 1476019SN/A } 1486019SN/A 1497408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1507408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1517408Sgblack@eecs.umich.edu } 1527408Sgblack@eecs.umich.edu 1536019SN/A return fault; 1546019SN/A } 1556019SN/A}}; 1566019SN/A 1576265SN/Adef template DataDecode {{ 1586265SN/A if (machInst.opcode4 == 0) { 1596265SN/A if (machInst.sField == 0) 1606265SN/A return new %(class_name)sImm(machInst); 1616265SN/A else 1626265SN/A return new %(class_name)sImmCc(machInst); 1636265SN/A } else { 1646265SN/A if (machInst.sField == 0) 1656265SN/A return new %(class_name)s(machInst); 1666265SN/A else 1676265SN/A return new %(class_name)sCc(machInst); 1686265SN/A } 1696265SN/A}}; 1706265SN/A 1716270SN/Adef template DataImmDecode {{ 1726270SN/A if (machInst.sField == 0) 1736270SN/A return new %(class_name)s(machInst); 1746270SN/A else 1756270SN/A return new %(class_name)sCc(machInst); 1766270SN/A}}; 177