pred.isa revision 7138
16019SN/A// -*- mode:c++ -*- 26019SN/A 37110SN/A// Copyright (c) 2010 ARM Limited 47110SN/A// All rights reserved 57110SN/A// 67110SN/A// The license below extends only to copyright in the software and shall 77110SN/A// not be construed as granting a license to any other intellectual 87110SN/A// property including but not limited to intellectual property relating 97110SN/A// to a hardware implementation of the functionality of the software 107110SN/A// licensed hereunder. You may use the software subject to the license 117110SN/A// terms below provided that you ensure that this notice is replicated 127110SN/A// unmodified and in its entirety in all distributions of the software, 137110SN/A// modified or unmodified, in source code or in binary form. 147110SN/A// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426019SN/A 436019SN/A//////////////////////////////////////////////////////////////////// 446019SN/A// 456019SN/A// Predicated Instruction Execution 466019SN/A// 476019SN/A 486243SN/Alet {{ 496724SN/A predicateTest = 'testPredicate(CondCodes, condCode)' 506243SN/A}}; 516243SN/A 527138Sgblack@eecs.umich.edudef template DataImmDeclare {{ 537138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 547138Sgblack@eecs.umich.edu{ 557138Sgblack@eecs.umich.edu public: 567138Sgblack@eecs.umich.edu // Constructor 577138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 587138Sgblack@eecs.umich.edu IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 597138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 607138Sgblack@eecs.umich.edu}; 617138Sgblack@eecs.umich.edu}}; 627138Sgblack@eecs.umich.edu 637138Sgblack@eecs.umich.edudef template DataImmConstructor {{ 647138Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 657138Sgblack@eecs.umich.edu IntRegIndex _dest, 667138Sgblack@eecs.umich.edu IntRegIndex _op1, 677138Sgblack@eecs.umich.edu uint32_t _imm, 687138Sgblack@eecs.umich.edu bool _rotC) 697138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 707138Sgblack@eecs.umich.edu _dest, _op1, _imm, _rotC) 717138Sgblack@eecs.umich.edu { 727138Sgblack@eecs.umich.edu %(constructor)s; 737138Sgblack@eecs.umich.edu } 747138Sgblack@eecs.umich.edu}}; 757138Sgblack@eecs.umich.edu 767138Sgblack@eecs.umich.edudef template DataRegDeclare {{ 777138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 787138Sgblack@eecs.umich.edu{ 797138Sgblack@eecs.umich.edu public: 807138Sgblack@eecs.umich.edu // Constructor 817138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 827138Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, 837138Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType); 847138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 857138Sgblack@eecs.umich.edu}; 867138Sgblack@eecs.umich.edu}}; 877138Sgblack@eecs.umich.edu 887138Sgblack@eecs.umich.edudef template DataRegConstructor {{ 897138Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 907138Sgblack@eecs.umich.edu IntRegIndex _dest, 917138Sgblack@eecs.umich.edu IntRegIndex _op1, 927138Sgblack@eecs.umich.edu IntRegIndex _op2, 937138Sgblack@eecs.umich.edu int32_t _shiftAmt, 947138Sgblack@eecs.umich.edu ArmShiftType _shiftType) 957138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 967138Sgblack@eecs.umich.edu _dest, _op1, _op2, _shiftAmt, _shiftType) 977138Sgblack@eecs.umich.edu { 987138Sgblack@eecs.umich.edu %(constructor)s; 997138Sgblack@eecs.umich.edu } 1007138Sgblack@eecs.umich.edu}}; 1017138Sgblack@eecs.umich.edu 1027138Sgblack@eecs.umich.edudef template DataRegRegDeclare {{ 1037138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1047138Sgblack@eecs.umich.edu{ 1057138Sgblack@eecs.umich.edu public: 1067138Sgblack@eecs.umich.edu // Constructor 1077138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 1087138Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 1097138Sgblack@eecs.umich.edu ArmShiftType _shiftType); 1107138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1117138Sgblack@eecs.umich.edu}; 1127138Sgblack@eecs.umich.edu}}; 1137138Sgblack@eecs.umich.edu 1147138Sgblack@eecs.umich.edudef template DataRegRegConstructor {{ 1157138Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1167138Sgblack@eecs.umich.edu IntRegIndex _dest, 1177138Sgblack@eecs.umich.edu IntRegIndex _op1, 1187138Sgblack@eecs.umich.edu IntRegIndex _op2, 1197138Sgblack@eecs.umich.edu IntRegIndex _shift, 1207138Sgblack@eecs.umich.edu ArmShiftType _shiftType) 1217138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1227138Sgblack@eecs.umich.edu _dest, _op1, _op2, _shift, _shiftType) 1237138Sgblack@eecs.umich.edu { 1247138Sgblack@eecs.umich.edu %(constructor)s; 1257138Sgblack@eecs.umich.edu } 1267138Sgblack@eecs.umich.edu}}; 1277138Sgblack@eecs.umich.edu 1286019SN/Adef template PredOpExecute {{ 1296019SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1306019SN/A { 1316019SN/A Fault fault = NoFault; 1326271SN/A uint64_t resTemp = 0; 1336271SN/A resTemp = resTemp; 1346019SN/A %(op_decl)s; 1356019SN/A %(op_rd)s; 1366019SN/A 1376243SN/A if (%(predicate_test)s) 1386019SN/A { 1396243SN/A %(code)s; 1406019SN/A if (fault == NoFault) 1416019SN/A { 1426019SN/A %(op_wb)s; 1436019SN/A } 1446019SN/A } 1456019SN/A 1466019SN/A return fault; 1476019SN/A } 1486019SN/A}}; 1496019SN/A 1506265SN/Adef template DataDecode {{ 1516265SN/A if (machInst.opcode4 == 0) { 1526265SN/A if (machInst.sField == 0) 1536265SN/A return new %(class_name)sImm(machInst); 1546265SN/A else 1556265SN/A return new %(class_name)sImmCc(machInst); 1566265SN/A } else { 1576265SN/A if (machInst.sField == 0) 1586265SN/A return new %(class_name)s(machInst); 1596265SN/A else 1606265SN/A return new %(class_name)sCc(machInst); 1616265SN/A } 1626265SN/A}}; 1636265SN/A 1646270SN/Adef template DataImmDecode {{ 1656270SN/A if (machInst.sField == 0) 1666270SN/A return new %(class_name)s(machInst); 1676270SN/A else 1686270SN/A return new %(class_name)sCc(machInst); 1696270SN/A}}; 170