pred.isa revision 10184
16019SN/A// -*- mode:c++ -*- 26019SN/A 37110SN/A// Copyright (c) 2010 ARM Limited 47110SN/A// All rights reserved 57110SN/A// 67110SN/A// The license below extends only to copyright in the software and shall 77110SN/A// not be construed as granting a license to any other intellectual 87110SN/A// property including but not limited to intellectual property relating 97110SN/A// to a hardware implementation of the functionality of the software 107110SN/A// licensed hereunder. You may use the software subject to the license 117110SN/A// terms below provided that you ensure that this notice is replicated 127110SN/A// unmodified and in its entirety in all distributions of the software, 137110SN/A// modified or unmodified, in source code or in binary form. 147110SN/A// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426019SN/A 436019SN/A//////////////////////////////////////////////////////////////////// 446019SN/A// 456019SN/A// Predicated Instruction Execution 466019SN/A// 476019SN/A 486243SN/Alet {{ 498303SAli.Saidi@ARM.com predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)' 508303SAli.Saidi@ARM.com condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)' 516243SN/A}}; 526243SN/A 537138Sgblack@eecs.umich.edudef template DataImmDeclare {{ 547138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 557138Sgblack@eecs.umich.edu{ 567138Sgblack@eecs.umich.edu public: 577138Sgblack@eecs.umich.edu // Constructor 587138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 597138Sgblack@eecs.umich.edu IntRegIndex _op1, uint32_t _imm, bool _rotC=true); 607138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 617138Sgblack@eecs.umich.edu}; 627138Sgblack@eecs.umich.edu}}; 637138Sgblack@eecs.umich.edu 647138Sgblack@eecs.umich.edudef template DataImmConstructor {{ 6510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 667138Sgblack@eecs.umich.edu IntRegIndex _dest, 677138Sgblack@eecs.umich.edu IntRegIndex _op1, 687138Sgblack@eecs.umich.edu uint32_t _imm, 697138Sgblack@eecs.umich.edu bool _rotC) 707138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 717138Sgblack@eecs.umich.edu _dest, _op1, _imm, _rotC) 727138Sgblack@eecs.umich.edu { 737138Sgblack@eecs.umich.edu %(constructor)s; 747848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 757848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 767848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 777848SAli.Saidi@ARM.com } 787848SAli.Saidi@ARM.com } 799250SAli.Saidi@ARM.com 809573Ssaidi@eecs.umich.edu if (%(is_branch)s && !isFloating()){ 819250SAli.Saidi@ARM.com flags[IsControl] = true; 829250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 839250SAli.Saidi@ARM.com if (condCode == COND_AL || condCode == COND_UC) 849250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 859250SAli.Saidi@ARM.com else 869250SAli.Saidi@ARM.com flags[IsCondControl] = true; 879250SAli.Saidi@ARM.com } 887138Sgblack@eecs.umich.edu } 897138Sgblack@eecs.umich.edu}}; 907138Sgblack@eecs.umich.edu 917138Sgblack@eecs.umich.edudef template DataRegDeclare {{ 927138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 937138Sgblack@eecs.umich.edu{ 947138Sgblack@eecs.umich.edu public: 957138Sgblack@eecs.umich.edu // Constructor 967138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 977138Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, 987138Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType); 997138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1007138Sgblack@eecs.umich.edu}; 1017138Sgblack@eecs.umich.edu}}; 1027138Sgblack@eecs.umich.edu 1037138Sgblack@eecs.umich.edudef template DataRegConstructor {{ 10410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1057138Sgblack@eecs.umich.edu IntRegIndex _dest, 1067138Sgblack@eecs.umich.edu IntRegIndex _op1, 1077138Sgblack@eecs.umich.edu IntRegIndex _op2, 1087138Sgblack@eecs.umich.edu int32_t _shiftAmt, 1097138Sgblack@eecs.umich.edu ArmShiftType _shiftType) 1107138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1117138Sgblack@eecs.umich.edu _dest, _op1, _op2, _shiftAmt, _shiftType) 1127138Sgblack@eecs.umich.edu { 1137138Sgblack@eecs.umich.edu %(constructor)s; 1147848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1157848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1167848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1177848SAli.Saidi@ARM.com } 1187848SAli.Saidi@ARM.com } 1198203SAli.Saidi@ARM.com 1209573Ssaidi@eecs.umich.edu if (%(is_branch)s && !isFloating()){ 1218203SAli.Saidi@ARM.com flags[IsControl] = true; 1228203SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 1238203SAli.Saidi@ARM.com if (condCode == COND_AL || condCode == COND_UC) 1248910Snpremill@irisa.fr flags[IsUncondControl] = true; 1258910Snpremill@irisa.fr else 1268203SAli.Saidi@ARM.com flags[IsCondControl] = true; 1279077SAli.Saidi@ARM.com 1289077SAli.Saidi@ARM.com if (%(is_ras_pop)s) { 1299077SAli.Saidi@ARM.com flags[IsReturn] = true; 1309077SAli.Saidi@ARM.com } 1318203SAli.Saidi@ARM.com } 1328203SAli.Saidi@ARM.com 1337138Sgblack@eecs.umich.edu } 1347138Sgblack@eecs.umich.edu}}; 1357138Sgblack@eecs.umich.edu 1367138Sgblack@eecs.umich.edudef template DataRegRegDeclare {{ 1377138Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1387138Sgblack@eecs.umich.edu{ 1397138Sgblack@eecs.umich.edu public: 1407138Sgblack@eecs.umich.edu // Constructor 1417138Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 1427138Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, 1437138Sgblack@eecs.umich.edu ArmShiftType _shiftType); 1447138Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1457138Sgblack@eecs.umich.edu}; 1467138Sgblack@eecs.umich.edu}}; 1477138Sgblack@eecs.umich.edu 1487138Sgblack@eecs.umich.edudef template DataRegRegConstructor {{ 14910184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1507138Sgblack@eecs.umich.edu IntRegIndex _dest, 1517138Sgblack@eecs.umich.edu IntRegIndex _op1, 1527138Sgblack@eecs.umich.edu IntRegIndex _op2, 1537138Sgblack@eecs.umich.edu IntRegIndex _shift, 1547138Sgblack@eecs.umich.edu ArmShiftType _shiftType) 1557138Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1567138Sgblack@eecs.umich.edu _dest, _op1, _op2, _shift, _shiftType) 1577138Sgblack@eecs.umich.edu { 1587138Sgblack@eecs.umich.edu %(constructor)s; 1597848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1607848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1617848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1627848SAli.Saidi@ARM.com } 1637848SAli.Saidi@ARM.com } 1647138Sgblack@eecs.umich.edu } 1657138Sgblack@eecs.umich.edu}}; 1667138Sgblack@eecs.umich.edu 1676019SN/Adef template PredOpExecute {{ 1686019SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1696019SN/A { 1706019SN/A Fault fault = NoFault; 1716271SN/A uint64_t resTemp = 0; 1726271SN/A resTemp = resTemp; 1736019SN/A %(op_decl)s; 1746019SN/A %(op_rd)s; 1756019SN/A 1766243SN/A if (%(predicate_test)s) 1776019SN/A { 1786243SN/A %(code)s; 1796019SN/A if (fault == NoFault) 1806019SN/A { 1816019SN/A %(op_wb)s; 1826019SN/A } 1837597Sminkyu.jeong@arm.com } else { 1847597Sminkyu.jeong@arm.com xc->setPredicate(false); 1856019SN/A } 1866019SN/A 1876019SN/A return fault; 1886019SN/A } 1896019SN/A}}; 1906019SN/A 1918142SAli.Saidi@ARM.comdef template QuiescePredOpExecute {{ 1928142SAli.Saidi@ARM.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1938142SAli.Saidi@ARM.com { 1948142SAli.Saidi@ARM.com Fault fault = NoFault; 1958142SAli.Saidi@ARM.com uint64_t resTemp = 0; 1968142SAli.Saidi@ARM.com resTemp = resTemp; 1978142SAli.Saidi@ARM.com %(op_decl)s; 1988142SAli.Saidi@ARM.com %(op_rd)s; 1998142SAli.Saidi@ARM.com 2008142SAli.Saidi@ARM.com if (%(predicate_test)s) 2018142SAli.Saidi@ARM.com { 2028142SAli.Saidi@ARM.com %(code)s; 2038142SAli.Saidi@ARM.com if (fault == NoFault) 2048142SAli.Saidi@ARM.com { 2058142SAli.Saidi@ARM.com %(op_wb)s; 2068142SAli.Saidi@ARM.com } 2078142SAli.Saidi@ARM.com } else { 2088142SAli.Saidi@ARM.com xc->setPredicate(false); 2098142SAli.Saidi@ARM.com PseudoInst::quiesceSkip(xc->tcBase()); 2108142SAli.Saidi@ARM.com } 2118142SAli.Saidi@ARM.com 2128142SAli.Saidi@ARM.com return fault; 2138142SAli.Saidi@ARM.com } 2148142SAli.Saidi@ARM.com}}; 2158142SAli.Saidi@ARM.com 2168518Sgeoffrey.blake@arm.comdef template QuiescePredOpExecuteWithFixup {{ 2178518Sgeoffrey.blake@arm.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2188518Sgeoffrey.blake@arm.com { 2198518Sgeoffrey.blake@arm.com Fault fault = NoFault; 2208518Sgeoffrey.blake@arm.com uint64_t resTemp = 0; 2218518Sgeoffrey.blake@arm.com resTemp = resTemp; 2228518Sgeoffrey.blake@arm.com %(op_decl)s; 2238518Sgeoffrey.blake@arm.com %(op_rd)s; 2248518Sgeoffrey.blake@arm.com 2258518Sgeoffrey.blake@arm.com if (%(predicate_test)s) 2268518Sgeoffrey.blake@arm.com { 2278518Sgeoffrey.blake@arm.com %(code)s; 2288518Sgeoffrey.blake@arm.com if (fault == NoFault) 2298518Sgeoffrey.blake@arm.com { 2308518Sgeoffrey.blake@arm.com %(op_wb)s; 2318518Sgeoffrey.blake@arm.com } 2328518Sgeoffrey.blake@arm.com } else { 2338518Sgeoffrey.blake@arm.com xc->setPredicate(false); 2348518Sgeoffrey.blake@arm.com %(pred_fixup)s; 2358518Sgeoffrey.blake@arm.com PseudoInst::quiesceSkip(xc->tcBase()); 2368518Sgeoffrey.blake@arm.com } 2378518Sgeoffrey.blake@arm.com 2388518Sgeoffrey.blake@arm.com return fault; 2398518Sgeoffrey.blake@arm.com } 2408518Sgeoffrey.blake@arm.com}}; 2418518Sgeoffrey.blake@arm.com 2426265SN/Adef template DataDecode {{ 2436265SN/A if (machInst.opcode4 == 0) { 2446265SN/A if (machInst.sField == 0) 2456265SN/A return new %(class_name)sImm(machInst); 2466265SN/A else 2476265SN/A return new %(class_name)sImmCc(machInst); 2486265SN/A } else { 2496265SN/A if (machInst.sField == 0) 2506265SN/A return new %(class_name)s(machInst); 2516265SN/A else 2526265SN/A return new %(class_name)sCc(machInst); 2536265SN/A } 2546265SN/A}}; 2556265SN/A 2566270SN/Adef template DataImmDecode {{ 2576270SN/A if (machInst.sField == 0) 2586270SN/A return new %(class_name)s(machInst); 2596270SN/A else 2606270SN/A return new %(class_name)sCc(machInst); 2616270SN/A}}; 262