neon64.isa revision 11488
110037SARM gem5 Developers// -*- mode: c++ -*- 210037SARM gem5 Developers 310037SARM gem5 Developers// Copyright (c) 2012-2013 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Mbou Eyole 3910037SARM gem5 Developers// Giacomo Gabrielli 4010037SARM gem5 Developers 4110037SARM gem5 Developerslet {{ 4210037SARM gem5 Developers simd64EnabledCheckCode = vfp64EnabledCheckCode 4310037SARM gem5 Developers}}; 4410037SARM gem5 Developers 4510037SARM gem5 Developersdef template NeonX2RegOpDeclare {{ 4610037SARM gem5 Developerstemplate <class _Element> 4710037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 4810037SARM gem5 Developers{ 4910037SARM gem5 Developers protected: 5010037SARM gem5 Developers typedef _Element Element; 5110037SARM gem5 Developers public: 5210037SARM gem5 Developers // Constructor 5310037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 5410037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) 5510037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 5610037SARM gem5 Developers _dest, _op1, _op2) 5710037SARM gem5 Developers { 5810037SARM gem5 Developers %(constructor)s; 5910037SARM gem5 Developers } 6010037SARM gem5 Developers 6110037SARM gem5 Developers %(BasicExecDeclare)s 6210037SARM gem5 Developers}; 6310037SARM gem5 Developers}}; 6410037SARM gem5 Developers 6510037SARM gem5 Developersdef template NeonX2RegImmOpDeclare {{ 6610037SARM gem5 Developerstemplate <class _Element> 6710037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers protected: 7010037SARM gem5 Developers typedef _Element Element; 7110037SARM gem5 Developers public: 7210037SARM gem5 Developers // Constructor 7310037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 7410037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 7510037SARM gem5 Developers uint64_t _imm) 7610037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7710037SARM gem5 Developers _dest, _op1, _op2, _imm) 7810037SARM gem5 Developers { 7910037SARM gem5 Developers %(constructor)s; 8010037SARM gem5 Developers } 8110037SARM gem5 Developers 8210037SARM gem5 Developers %(BasicExecDeclare)s 8310037SARM gem5 Developers}; 8410037SARM gem5 Developers}}; 8510037SARM gem5 Developers 8610037SARM gem5 Developersdef template NeonX1RegOpDeclare {{ 8710037SARM gem5 Developerstemplate <class _Element> 8810037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 8910037SARM gem5 Developers{ 9010037SARM gem5 Developers protected: 9110037SARM gem5 Developers typedef _Element Element; 9210037SARM gem5 Developers public: 9310037SARM gem5 Developers // Constructor 9410037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 9510037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1) 9610037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9710037SARM gem5 Developers _dest, _op1) 9810037SARM gem5 Developers { 9910037SARM gem5 Developers %(constructor)s; 10010037SARM gem5 Developers } 10110037SARM gem5 Developers 10210037SARM gem5 Developers %(BasicExecDeclare)s 10310037SARM gem5 Developers}; 10410037SARM gem5 Developers}}; 10510037SARM gem5 Developers 10610037SARM gem5 Developersdef template NeonX1RegImmOpDeclare {{ 10710037SARM gem5 Developerstemplate <class _Element> 10810037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 10910037SARM gem5 Developers{ 11010037SARM gem5 Developers protected: 11110037SARM gem5 Developers typedef _Element Element; 11210037SARM gem5 Developers public: 11310037SARM gem5 Developers // Constructor 11410037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 11510037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) 11610037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11710037SARM gem5 Developers _dest, _op1, _imm) 11810037SARM gem5 Developers { 11910037SARM gem5 Developers %(constructor)s; 12010037SARM gem5 Developers } 12110037SARM gem5 Developers 12210037SARM gem5 Developers %(BasicExecDeclare)s 12310037SARM gem5 Developers}; 12410037SARM gem5 Developers}}; 12510037SARM gem5 Developers 12610037SARM gem5 Developersdef template NeonX1Reg2ImmOpDeclare {{ 12710037SARM gem5 Developerstemplate <class _Element> 12810037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 12910037SARM gem5 Developers{ 13010037SARM gem5 Developers protected: 13110037SARM gem5 Developers typedef _Element Element; 13210037SARM gem5 Developers public: 13310037SARM gem5 Developers // Constructor 13410037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 13510037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, 13610037SARM gem5 Developers uint64_t _imm2) 13710037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 13810037SARM gem5 Developers _dest, _op1, _imm1, _imm2) 13910037SARM gem5 Developers { 14010037SARM gem5 Developers %(constructor)s; 14110037SARM gem5 Developers } 14210037SARM gem5 Developers 14310037SARM gem5 Developers %(BasicExecDeclare)s 14410037SARM gem5 Developers}; 14510037SARM gem5 Developers}}; 14610037SARM gem5 Developers 14710037SARM gem5 Developersdef template NeonX1RegImmOnlyOpDeclare {{ 14810037SARM gem5 Developerstemplate <class _Element> 14910037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 15010037SARM gem5 Developers{ 15110037SARM gem5 Developers protected: 15210037SARM gem5 Developers typedef _Element Element; 15310037SARM gem5 Developers public: 15410037SARM gem5 Developers // Constructor 15510037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 15610037SARM gem5 Developers IntRegIndex _dest, uint64_t _imm) 15710037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 15810037SARM gem5 Developers _dest, _imm) 15910037SARM gem5 Developers { 16010037SARM gem5 Developers %(constructor)s; 16110037SARM gem5 Developers } 16210037SARM gem5 Developers 16310037SARM gem5 Developers %(BasicExecDeclare)s 16410037SARM gem5 Developers}; 16510037SARM gem5 Developers}}; 16610037SARM gem5 Developers 16710037SARM gem5 Developersdef template NeonXExecDeclare {{ 16810037SARM gem5 Developers template 16910037SARM gem5 Developers Fault %(class_name)s<%(targs)s>::execute( 17010196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 17110037SARM gem5 Developers}}; 17210037SARM gem5 Developers 17310037SARM gem5 Developersdef template NeonXEqualRegOpExecute {{ 17410037SARM gem5 Developers template <class Element> 17510196SCurtis.Dunham@arm.com Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, 17610037SARM gem5 Developers Trace::InstRecord *traceData) const 17710037SARM gem5 Developers { 17810037SARM gem5 Developers Fault fault = NoFault; 17910037SARM gem5 Developers %(op_decl)s; 18010037SARM gem5 Developers %(op_rd)s; 18110037SARM gem5 Developers 18210037SARM gem5 Developers const unsigned rCount = %(r_count)d; 18310037SARM gem5 Developers const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); 18410037SARM gem5 Developers const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element); 18510037SARM gem5 Developers 18610037SARM gem5 Developers union RegVect { 18710037SARM gem5 Developers FloatRegBits regs[rCount]; 18810037SARM gem5 Developers Element elements[eCount]; 18910037SARM gem5 Developers }; 19010037SARM gem5 Developers 19110037SARM gem5 Developers union FullRegVect { 19210037SARM gem5 Developers FloatRegBits regs[4]; 19310037SARM gem5 Developers Element elements[eCountFull]; 19410037SARM gem5 Developers }; 19510037SARM gem5 Developers 19610037SARM gem5 Developers %(code)s; 19710037SARM gem5 Developers if (fault == NoFault) 19810037SARM gem5 Developers { 19910037SARM gem5 Developers %(op_wb)s; 20010037SARM gem5 Developers } 20110037SARM gem5 Developers 20210037SARM gem5 Developers return fault; 20310037SARM gem5 Developers } 20410037SARM gem5 Developers}}; 20510037SARM gem5 Developers 20610037SARM gem5 Developersdef template NeonXUnequalRegOpExecute {{ 20710037SARM gem5 Developers template <class Element> 20810196SCurtis.Dunham@arm.com Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, 20910037SARM gem5 Developers Trace::InstRecord *traceData) const 21010037SARM gem5 Developers { 21110037SARM gem5 Developers typedef typename bigger_type_t<Element>::type BigElement; 21210037SARM gem5 Developers Fault fault = NoFault; 21310037SARM gem5 Developers %(op_decl)s; 21410037SARM gem5 Developers %(op_rd)s; 21510037SARM gem5 Developers 21610037SARM gem5 Developers const unsigned rCount = %(r_count)d; 21710037SARM gem5 Developers const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); 21810037SARM gem5 Developers const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element); 21910037SARM gem5 Developers 22010037SARM gem5 Developers union RegVect { 22110037SARM gem5 Developers FloatRegBits regs[rCount]; 22210037SARM gem5 Developers Element elements[eCount]; 22310037SARM gem5 Developers BigElement bigElements[eCount / 2]; 22410037SARM gem5 Developers }; 22510037SARM gem5 Developers 22610037SARM gem5 Developers union BigRegVect { 22710037SARM gem5 Developers FloatRegBits regs[2 * rCount]; 22810037SARM gem5 Developers BigElement elements[eCount]; 22910037SARM gem5 Developers }; 23010037SARM gem5 Developers 23110037SARM gem5 Developers union FullRegVect { 23210037SARM gem5 Developers FloatRegBits regs[4]; 23310037SARM gem5 Developers Element elements[eCountFull]; 23410037SARM gem5 Developers }; 23510037SARM gem5 Developers 23610037SARM gem5 Developers %(code)s; 23710037SARM gem5 Developers if (fault == NoFault) 23810037SARM gem5 Developers { 23910037SARM gem5 Developers %(op_wb)s; 24010037SARM gem5 Developers } 24110037SARM gem5 Developers 24210037SARM gem5 Developers return fault; 24310037SARM gem5 Developers } 24410037SARM gem5 Developers}}; 24510037SARM gem5 Developers 24610037SARM gem5 Developersdef template MicroNeonMemDeclare64 {{ 24710037SARM gem5 Developers class %(class_name)s : public %(base_class)s 24810037SARM gem5 Developers { 24910037SARM gem5 Developers protected: 25010037SARM gem5 Developers // True if the base register is SP (used for SP alignment checking) 25110037SARM gem5 Developers bool baseIsSP; 25210037SARM gem5 Developers // Access size in bytes 25310037SARM gem5 Developers uint8_t accSize; 25410037SARM gem5 Developers // Vector element size (0 -> 8-bit, 1 -> 16-bit, 2 -> 32-bit, 25510037SARM gem5 Developers // 3 -> 64-bit) 25610037SARM gem5 Developers uint8_t eSize; 25710037SARM gem5 Developers 25810037SARM gem5 Developers public: 25910037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _ura, 26010037SARM gem5 Developers uint32_t _imm, unsigned extraMemFlags, bool _baseIsSP, 26110037SARM gem5 Developers uint8_t _accSize, uint8_t _eSize) 26210037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, 26310037SARM gem5 Developers _ura, _imm), 26410037SARM gem5 Developers baseIsSP(_baseIsSP), accSize(_accSize), eSize(_eSize) 26510037SARM gem5 Developers { 26610037SARM gem5 Developers memAccessFlags |= extraMemFlags; 26710037SARM gem5 Developers %(constructor)s; 26810037SARM gem5 Developers } 26910037SARM gem5 Developers 27010037SARM gem5 Developers %(BasicExecDeclare)s 27110037SARM gem5 Developers %(InitiateAccDeclare)s 27210037SARM gem5 Developers %(CompleteAccDeclare)s 27310037SARM gem5 Developers }; 27410037SARM gem5 Developers}}; 27510037SARM gem5 Developers 27610037SARM gem5 Developersdef template NeonLoadExecute64 {{ 27710037SARM gem5 Developers Fault %(class_name)s::execute( 27810196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 27910037SARM gem5 Developers { 28010037SARM gem5 Developers Addr EA; 28110037SARM gem5 Developers Fault fault = NoFault; 28210037SARM gem5 Developers 28310037SARM gem5 Developers %(op_decl)s; 28410037SARM gem5 Developers %(mem_decl)s; 28510037SARM gem5 Developers %(op_rd)s; 28610037SARM gem5 Developers %(ea_code)s; 28710037SARM gem5 Developers 28810037SARM gem5 Developers MemUnion memUnion; 28910037SARM gem5 Developers uint8_t *dataPtr = memUnion.bytes; 29010037SARM gem5 Developers 29110037SARM gem5 Developers if (fault == NoFault) { 29210037SARM gem5 Developers fault = xc->readMem(EA, dataPtr, accSize, memAccessFlags); 29310037SARM gem5 Developers %(memacc_code)s; 29410037SARM gem5 Developers } 29510037SARM gem5 Developers 29610037SARM gem5 Developers if (fault == NoFault) { 29710037SARM gem5 Developers %(op_wb)s; 29810037SARM gem5 Developers } 29910037SARM gem5 Developers 30010037SARM gem5 Developers return fault; 30110037SARM gem5 Developers } 30210037SARM gem5 Developers}}; 30310037SARM gem5 Developers 30410037SARM gem5 Developersdef template NeonLoadInitiateAcc64 {{ 30510037SARM gem5 Developers Fault %(class_name)s::initiateAcc( 30610196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 30710037SARM gem5 Developers { 30810037SARM gem5 Developers Addr EA; 30910037SARM gem5 Developers Fault fault = NoFault; 31010037SARM gem5 Developers 31110037SARM gem5 Developers %(op_decl)s; 31210037SARM gem5 Developers %(mem_decl)s; 31310037SARM gem5 Developers %(op_rd)s; 31410037SARM gem5 Developers %(ea_code)s; 31510037SARM gem5 Developers 31610037SARM gem5 Developers if (fault == NoFault) { 31711303Ssteve.reinhardt@amd.com fault = xc->initiateMemRead(EA, accSize, memAccessFlags); 31810037SARM gem5 Developers } 31910037SARM gem5 Developers 32010037SARM gem5 Developers return fault; 32110037SARM gem5 Developers } 32210037SARM gem5 Developers}}; 32310037SARM gem5 Developers 32410037SARM gem5 Developersdef template NeonLoadCompleteAcc64 {{ 32510037SARM gem5 Developers Fault %(class_name)s::completeAcc( 32610196SCurtis.Dunham@arm.com PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 32710037SARM gem5 Developers Trace::InstRecord *traceData) const 32810037SARM gem5 Developers { 32910037SARM gem5 Developers Fault fault = NoFault; 33010037SARM gem5 Developers 33110037SARM gem5 Developers %(mem_decl)s; 33210037SARM gem5 Developers %(op_decl)s; 33310037SARM gem5 Developers %(op_rd)s; 33410037SARM gem5 Developers 33511488Sandreas.hansson@arm.com MemUnion memUnion { { } }; 33611488Sandreas.hansson@arm.com memcpy(&memUnion, pkt->getPtr<uint8_t>(), pkt->getSize()); 33710037SARM gem5 Developers 33810037SARM gem5 Developers if (fault == NoFault) { 33910037SARM gem5 Developers %(memacc_code)s; 34010037SARM gem5 Developers } 34110037SARM gem5 Developers 34210037SARM gem5 Developers if (fault == NoFault) { 34310037SARM gem5 Developers %(op_wb)s; 34410037SARM gem5 Developers } 34510037SARM gem5 Developers 34610037SARM gem5 Developers return fault; 34710037SARM gem5 Developers } 34810037SARM gem5 Developers}}; 34910037SARM gem5 Developers 35010037SARM gem5 Developersdef template NeonStoreExecute64 {{ 35110037SARM gem5 Developers Fault %(class_name)s::execute( 35210196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 35310037SARM gem5 Developers { 35410037SARM gem5 Developers Addr EA; 35510037SARM gem5 Developers Fault fault = NoFault; 35610037SARM gem5 Developers 35710037SARM gem5 Developers %(op_decl)s; 35810037SARM gem5 Developers %(mem_decl)s; 35910037SARM gem5 Developers %(op_rd)s; 36010037SARM gem5 Developers %(ea_code)s; 36110037SARM gem5 Developers 36210037SARM gem5 Developers MemUnion memUnion; 36310037SARM gem5 Developers uint8_t *dataPtr = memUnion.bytes; 36410037SARM gem5 Developers 36510037SARM gem5 Developers if (fault == NoFault) { 36610037SARM gem5 Developers %(memacc_code)s; 36710037SARM gem5 Developers } 36810037SARM gem5 Developers 36910037SARM gem5 Developers if (fault == NoFault) { 37010037SARM gem5 Developers fault = xc->writeMem(dataPtr, accSize, EA, memAccessFlags, 37110037SARM gem5 Developers NULL); 37210037SARM gem5 Developers } 37310037SARM gem5 Developers 37410037SARM gem5 Developers if (fault == NoFault) { 37510037SARM gem5 Developers %(op_wb)s; 37610037SARM gem5 Developers } 37710037SARM gem5 Developers 37810037SARM gem5 Developers return fault; 37910037SARM gem5 Developers } 38010037SARM gem5 Developers}}; 38110037SARM gem5 Developers 38210037SARM gem5 Developersdef template NeonStoreInitiateAcc64 {{ 38310037SARM gem5 Developers Fault %(class_name)s::initiateAcc( 38410196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 38510037SARM gem5 Developers { 38610037SARM gem5 Developers Addr EA; 38710037SARM gem5 Developers Fault fault = NoFault; 38810037SARM gem5 Developers 38910037SARM gem5 Developers %(op_decl)s; 39010037SARM gem5 Developers %(mem_decl)s; 39110037SARM gem5 Developers %(op_rd)s; 39210037SARM gem5 Developers %(ea_code)s; 39310037SARM gem5 Developers 39410037SARM gem5 Developers MemUnion memUnion; 39510037SARM gem5 Developers if (fault == NoFault) { 39610037SARM gem5 Developers %(memacc_code)s; 39710037SARM gem5 Developers } 39810037SARM gem5 Developers 39910037SARM gem5 Developers if (fault == NoFault) { 40010037SARM gem5 Developers fault = xc->writeMem(memUnion.bytes, accSize, EA, memAccessFlags, 40110037SARM gem5 Developers NULL); 40210037SARM gem5 Developers } 40310037SARM gem5 Developers 40410037SARM gem5 Developers return fault; 40510037SARM gem5 Developers } 40610037SARM gem5 Developers}}; 40710037SARM gem5 Developers 40810037SARM gem5 Developersdef template NeonStoreCompleteAcc64 {{ 40910037SARM gem5 Developers Fault %(class_name)s::completeAcc( 41010196SCurtis.Dunham@arm.com PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 41110037SARM gem5 Developers Trace::InstRecord *traceData) const 41210037SARM gem5 Developers { 41310037SARM gem5 Developers return NoFault; 41410037SARM gem5 Developers } 41510037SARM gem5 Developers}}; 41610037SARM gem5 Developers 41710037SARM gem5 Developersdef template VMemMultDeclare64 {{ 41810037SARM gem5 Developers class %(class_name)s : public %(base_class)s 41910037SARM gem5 Developers { 42010037SARM gem5 Developers public: 42110037SARM gem5 Developers // Constructor 42210037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd, 42310037SARM gem5 Developers RegIndex rm, uint8_t eSize, uint8_t dataSize, 42410037SARM gem5 Developers uint8_t numStructElems, uint8_t numRegs, bool wb); 42510037SARM gem5 Developers %(BasicExecPanic)s 42610037SARM gem5 Developers }; 42710037SARM gem5 Developers}}; 42810037SARM gem5 Developers 42910037SARM gem5 Developersdef template VMemSingleDeclare64 {{ 43010037SARM gem5 Developers class %(class_name)s : public %(base_class)s 43110037SARM gem5 Developers { 43210037SARM gem5 Developers public: 43310037SARM gem5 Developers // Constructor 43410037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd, 43510037SARM gem5 Developers RegIndex rm, uint8_t eSize, uint8_t dataSize, 43610037SARM gem5 Developers uint8_t numStructElems, uint8_t index, bool wb, 43710037SARM gem5 Developers bool replicate = false); 43810037SARM gem5 Developers %(BasicExecPanic)s 43910037SARM gem5 Developers }; 44010037SARM gem5 Developers}}; 44110037SARM gem5 Developers 44210037SARM gem5 Developersdef template VMemMultConstructor64 {{ 44310037SARM gem5 Developers %(class_name)s::%(class_name)s( 44410037SARM gem5 Developers ExtMachInst machInst, RegIndex rn, RegIndex vd, RegIndex rm, 44510037SARM gem5 Developers uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, 44610037SARM gem5 Developers uint8_t _numRegs, bool _wb) : 44710037SARM gem5 Developers %(base_class)s( 44810037SARM gem5 Developers "%(mnemonic)s", machInst, %(op_class)s, rn, vd, rm, 44910037SARM gem5 Developers _eSize, _dataSize, _numStructElems, _numRegs, _wb) 45010037SARM gem5 Developers { 45110037SARM gem5 Developers %(constructor)s; 45210037SARM gem5 Developers } 45310037SARM gem5 Developers}}; 45410037SARM gem5 Developers 45510037SARM gem5 Developersdef template VMemSingleConstructor64 {{ 45610037SARM gem5 Developers %(class_name)s::%(class_name)s( 45710037SARM gem5 Developers ExtMachInst machInst, RegIndex rn, RegIndex vd, RegIndex rm, 45810037SARM gem5 Developers uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, 45910037SARM gem5 Developers uint8_t _index, bool _wb, bool _replicate) : 46010037SARM gem5 Developers %(base_class)s( 46110037SARM gem5 Developers "%(mnemonic)s", machInst, %(op_class)s, rn, vd, rm, 46210037SARM gem5 Developers _eSize, _dataSize, _numStructElems, _index, _wb, 46310037SARM gem5 Developers _replicate) 46410037SARM gem5 Developers { 46510037SARM gem5 Developers %(constructor)s; 46610037SARM gem5 Developers } 46710037SARM gem5 Developers}}; 46810037SARM gem5 Developers 46910037SARM gem5 Developersdef template MicroNeonMixDeclare64 {{ 47010037SARM gem5 Developers class %(class_name)s : public %(base_class)s 47110037SARM gem5 Developers { 47210037SARM gem5 Developers public: 47310037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 47410037SARM gem5 Developers uint8_t _eSize, uint8_t _dataSize, 47510037SARM gem5 Developers uint8_t _numStructElems, uint8_t _numRegs, 47610037SARM gem5 Developers uint8_t _step) : 47710037SARM gem5 Developers %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 47810037SARM gem5 Developers _dest, _op1, _eSize, _dataSize, _numStructElems, 47910037SARM gem5 Developers _numRegs, _step) 48010037SARM gem5 Developers { 48110037SARM gem5 Developers %(constructor)s; 48210037SARM gem5 Developers } 48310037SARM gem5 Developers 48410037SARM gem5 Developers %(BasicExecDeclare)s 48510037SARM gem5 Developers }; 48610037SARM gem5 Developers}}; 48710037SARM gem5 Developers 48810037SARM gem5 Developersdef template MicroNeonMixLaneDeclare64 {{ 48910037SARM gem5 Developers class %(class_name)s : public %(base_class)s 49010037SARM gem5 Developers { 49110037SARM gem5 Developers public: 49210037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 49310037SARM gem5 Developers uint8_t _eSize, uint8_t _dataSize, 49410037SARM gem5 Developers uint8_t _numStructElems, uint8_t _lane, uint8_t _step, 49510037SARM gem5 Developers bool _replicate = false) : 49610037SARM gem5 Developers %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 49710037SARM gem5 Developers _dest, _op1, _eSize, _dataSize, _numStructElems, 49810037SARM gem5 Developers _lane, _step, _replicate) 49910037SARM gem5 Developers { 50010037SARM gem5 Developers %(constructor)s; 50110037SARM gem5 Developers } 50210037SARM gem5 Developers 50310037SARM gem5 Developers %(BasicExecDeclare)s 50410037SARM gem5 Developers }; 50510037SARM gem5 Developers}}; 50610037SARM gem5 Developers 50710037SARM gem5 Developersdef template MicroNeonMixExecute64 {{ 50810196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 50910037SARM gem5 Developers Trace::InstRecord *traceData) const 51010037SARM gem5 Developers { 51110037SARM gem5 Developers Fault fault = NoFault; 51210037SARM gem5 Developers uint64_t resTemp = 0; 51310037SARM gem5 Developers resTemp = resTemp; 51410037SARM gem5 Developers %(op_decl)s; 51510037SARM gem5 Developers %(op_rd)s; 51610037SARM gem5 Developers 51710037SARM gem5 Developers %(code)s; 51810037SARM gem5 Developers if (fault == NoFault) 51910037SARM gem5 Developers { 52010037SARM gem5 Developers %(op_wb)s; 52110037SARM gem5 Developers } 52210037SARM gem5 Developers 52310037SARM gem5 Developers return fault; 52410037SARM gem5 Developers } 52510037SARM gem5 Developers}}; 526