neon.isa revision 7641:788c719d0fc8
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def template NeonRegRegRegOpDeclare {{ 41template <class _Element> 42class %(class_name)s : public %(base_class)s 43{ 44 protected: 45 typedef _Element Element; 46 public: 47 // Constructor 48 %(class_name)s(ExtMachInst machInst, 49 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) 50 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 51 _dest, _op1, _op2) 52 { 53 %(constructor)s; 54 } 55 56 %(BasicExecDeclare)s 57}; 58}}; 59 60def template NeonRegRegRegImmOpDeclare {{ 61template <class _Element> 62class %(class_name)s : public %(base_class)s 63{ 64 protected: 65 typedef _Element Element; 66 public: 67 // Constructor 68 %(class_name)s(ExtMachInst machInst, 69 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 70 uint64_t _imm) 71 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 72 _dest, _op1, _op2, _imm) 73 { 74 %(constructor)s; 75 } 76 77 %(BasicExecDeclare)s 78}; 79}}; 80 81def template NeonRegRegImmOpDeclare {{ 82template <class _Element> 83class %(class_name)s : public %(base_class)s 84{ 85 protected: 86 typedef _Element Element; 87 public: 88 // Constructor 89 %(class_name)s(ExtMachInst machInst, 90 IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) 91 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 92 _dest, _op1, _imm) 93 { 94 %(constructor)s; 95 } 96 97 %(BasicExecDeclare)s 98}; 99}}; 100 101def template NeonRegImmOpDeclare {{ 102template <class _Element> 103class %(class_name)s : public %(base_class)s 104{ 105 protected: 106 typedef _Element Element; 107 public: 108 // Constructor 109 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) 110 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) 111 { 112 %(constructor)s; 113 } 114 115 %(BasicExecDeclare)s 116}; 117}}; 118 119def template NeonRegRegOpDeclare {{ 120template <class _Element> 121class %(class_name)s : public %(base_class)s 122{ 123 protected: 124 typedef _Element Element; 125 public: 126 // Constructor 127 %(class_name)s(ExtMachInst machInst, 128 IntRegIndex _dest, IntRegIndex _op1) 129 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 130 _dest, _op1) 131 { 132 %(constructor)s; 133 } 134 135 %(BasicExecDeclare)s 136}; 137}}; 138 139def template NeonExecDeclare {{ 140 template 141 Fault %(class_name)s<%(targs)s>::execute( 142 %(CPU_exec_context)s *, Trace::InstRecord *) const; 143}}; 144 145output header {{ 146 template <class T> 147 // Implement a less-than-zero function: ltz() 148 // this function exists because some versions of GCC complain when a 149 // comparison is done between a unsigned variable and 0 and for GCC 4.2 150 // there is no way to disable this warning 151 inline bool ltz(T t); 152 153 template <> 154 inline bool ltz(uint8_t) { return false; } 155 template <> 156 inline bool ltz(uint16_t) { return false; } 157 template <> 158 inline bool ltz(uint32_t) { return false; } 159 template <> 160 inline bool ltz(uint64_t) { return false; } 161 template <> 162 inline bool ltz(int8_t v) { return v < 0; } 163 template <> 164 inline bool ltz(int16_t v) { return v < 0; } 165 template <> 166 inline bool ltz(int32_t v) { return v < 0; } 167 template <> 168 inline bool ltz(int64_t v) { return v < 0; } 169}}; 170 171def template NeonEqualRegExecute {{ 172 template <class Element> 173 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 174 Trace::InstRecord *traceData) const 175 { 176 Fault fault = NoFault; 177 %(op_decl)s; 178 %(op_rd)s; 179 180 const unsigned rCount = %(r_count)d; 181 const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); 182 183 union RegVect { 184 FloatRegBits regs[rCount]; 185 Element elements[eCount]; 186 }; 187 188 if (%(predicate_test)s) 189 { 190 %(code)s; 191 if (fault == NoFault) 192 { 193 %(op_wb)s; 194 } 195 } 196 197 if (fault == NoFault && machInst.itstateMask != 0) { 198 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 199 } 200 201 return fault; 202 } 203}}; 204 205output header {{ 206 uint16_t nextBiggerType(uint8_t); 207 uint32_t nextBiggerType(uint16_t); 208 uint64_t nextBiggerType(uint32_t); 209 int16_t nextBiggerType(int8_t); 210 int32_t nextBiggerType(int16_t); 211 int64_t nextBiggerType(int32_t); 212}}; 213 214def template NeonUnequalRegExecute {{ 215 template <class Element> 216 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 217 Trace::InstRecord *traceData) const 218 { 219 typedef typeof(nextBiggerType((Element)0)) BigElement; 220 Fault fault = NoFault; 221 %(op_decl)s; 222 %(op_rd)s; 223 224 const unsigned rCount = %(r_count)d; 225 const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element); 226 227 union RegVect { 228 FloatRegBits regs[rCount]; 229 Element elements[eCount]; 230 BigElement bigElements[eCount / 2]; 231 }; 232 233 union BigRegVect { 234 FloatRegBits regs[2 * rCount]; 235 BigElement elements[eCount]; 236 }; 237 238 if (%(predicate_test)s) 239 { 240 %(code)s; 241 if (fault == NoFault) 242 { 243 %(op_wb)s; 244 } 245 } 246 247 if (fault == NoFault && machInst.itstateMask != 0) { 248 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 249 } 250 251 return fault; 252 } 253}}; 254