misc64.isa revision 10037 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template RegRegImmImmOp64Declare {{
41class %(class_name)s : public %(base_class)s
42{
43  protected:
44    public:
45        // Constructor
46        %(class_name)s(ExtMachInst machInst,
47                       IntRegIndex _dest, IntRegIndex _op1,
48                       uint64_t _imm1, uint64_t _imm2);
49        %(BasicExecDeclare)s
50};
51}};
52
53def template RegRegImmImmOp64Constructor {{
54    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
55                                          IntRegIndex _dest,
56                                          IntRegIndex _op1,
57                                          uint64_t _imm1,
58                                          uint64_t _imm2)
59        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
60                         _dest, _op1, _imm1, _imm2)
61    {
62        %(constructor)s;
63    }
64}};
65
66def template RegRegRegImmOp64Declare {{
67class %(class_name)s : public %(base_class)s
68{
69  protected:
70    public:
71        // Constructor
72        %(class_name)s(ExtMachInst machInst,
73                       IntRegIndex _dest, IntRegIndex _op1,
74                       IntRegIndex _op2, uint64_t _imm);
75        %(BasicExecDeclare)s
76};
77}};
78
79def template RegRegRegImmOp64Constructor {{
80    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
81                                          IntRegIndex _dest,
82                                          IntRegIndex _op1,
83                                          IntRegIndex _op2,
84                                          uint64_t _imm)
85        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
86                         _dest, _op1, _op2, _imm)
87    {
88        %(constructor)s;
89    }
90}};
91
92