misc64.isa revision 12280
110037SARM gem5 Developers// -*- mode:c++ -*- 210037SARM gem5 Developers 312280Sgiacomo.travaglini@arm.com// Copyright (c) 2011,2017 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Gabe Black 3910037SARM gem5 Developers 4010037SARM gem5 Developersdef template RegRegImmImmOp64Declare {{ 4110037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 4210037SARM gem5 Developers{ 4310037SARM gem5 Developers protected: 4410037SARM gem5 Developers public: 4510037SARM gem5 Developers // Constructor 4610037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 4710037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, 4810037SARM gem5 Developers uint64_t _imm1, uint64_t _imm2); 4912236Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const; 5010037SARM gem5 Developers}; 5110037SARM gem5 Developers}}; 5210037SARM gem5 Developers 5310037SARM gem5 Developersdef template RegRegImmImmOp64Constructor {{ 5410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 5510037SARM gem5 Developers IntRegIndex _dest, 5610037SARM gem5 Developers IntRegIndex _op1, 5710037SARM gem5 Developers uint64_t _imm1, 5810037SARM gem5 Developers uint64_t _imm2) 5910037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6010037SARM gem5 Developers _dest, _op1, _imm1, _imm2) 6110037SARM gem5 Developers { 6210037SARM gem5 Developers %(constructor)s; 6310037SARM gem5 Developers } 6410037SARM gem5 Developers}}; 6510037SARM gem5 Developers 6610037SARM gem5 Developersdef template RegRegRegImmOp64Declare {{ 6710037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers protected: 7010037SARM gem5 Developers public: 7110037SARM gem5 Developers // Constructor 7210037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 7310037SARM gem5 Developers IntRegIndex _dest, IntRegIndex _op1, 7410037SARM gem5 Developers IntRegIndex _op2, uint64_t _imm); 7512236Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const; 7610037SARM gem5 Developers}; 7710037SARM gem5 Developers}}; 7810037SARM gem5 Developers 7910037SARM gem5 Developersdef template RegRegRegImmOp64Constructor {{ 8010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8110037SARM gem5 Developers IntRegIndex _dest, 8210037SARM gem5 Developers IntRegIndex _op1, 8310037SARM gem5 Developers IntRegIndex _op2, 8410037SARM gem5 Developers uint64_t _imm) 8510037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8610037SARM gem5 Developers _dest, _op1, _op2, _imm) 8710037SARM gem5 Developers { 8810037SARM gem5 Developers %(constructor)s; 8910037SARM gem5 Developers } 9010037SARM gem5 Developers}}; 9110037SARM gem5 Developers 9212280Sgiacomo.travaglini@arm.comdef template MiscRegRegOp64Declare {{ 9312280Sgiacomo.travaglini@arm.comclass %(class_name)s : public %(base_class)s 9412280Sgiacomo.travaglini@arm.com{ 9512280Sgiacomo.travaglini@arm.com public: 9612280Sgiacomo.travaglini@arm.com // Constructor 9712280Sgiacomo.travaglini@arm.com %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, 9812280Sgiacomo.travaglini@arm.com IntRegIndex _op1, uint64_t _imm); 9912280Sgiacomo.travaglini@arm.com 10012280Sgiacomo.travaglini@arm.com Fault execute(ExecContext *, Trace::InstRecord *) const; 10112280Sgiacomo.travaglini@arm.com}; 10212280Sgiacomo.travaglini@arm.com}}; 10312280Sgiacomo.travaglini@arm.com 10412280Sgiacomo.travaglini@arm.comdef template MiscRegRegOp64Constructor {{ 10512280Sgiacomo.travaglini@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10612280Sgiacomo.travaglini@arm.com MiscRegIndex _dest, 10712280Sgiacomo.travaglini@arm.com IntRegIndex _op1, 10812280Sgiacomo.travaglini@arm.com uint64_t _imm) 10912280Sgiacomo.travaglini@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11012280Sgiacomo.travaglini@arm.com _dest, _op1, _imm) 11112280Sgiacomo.travaglini@arm.com { 11212280Sgiacomo.travaglini@arm.com %(constructor)s; 11312280Sgiacomo.travaglini@arm.com } 11412280Sgiacomo.travaglini@arm.com}}; 11512280Sgiacomo.travaglini@arm.com 11612280Sgiacomo.travaglini@arm.comdef template RegMiscRegOp64Declare {{ 11712280Sgiacomo.travaglini@arm.comclass %(class_name)s : public %(base_class)s 11812280Sgiacomo.travaglini@arm.com{ 11912280Sgiacomo.travaglini@arm.com public: 12012280Sgiacomo.travaglini@arm.com // Constructor 12112280Sgiacomo.travaglini@arm.com %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 12212280Sgiacomo.travaglini@arm.com MiscRegIndex _op1, uint64_t _imm); 12312280Sgiacomo.travaglini@arm.com 12412280Sgiacomo.travaglini@arm.com Fault execute(ExecContext *, Trace::InstRecord *) const; 12512280Sgiacomo.travaglini@arm.com}; 12612280Sgiacomo.travaglini@arm.com}}; 12712280Sgiacomo.travaglini@arm.com 12812280Sgiacomo.travaglini@arm.comdef template RegMiscRegOp64Constructor {{ 12912280Sgiacomo.travaglini@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 13012280Sgiacomo.travaglini@arm.com IntRegIndex _dest, 13112280Sgiacomo.travaglini@arm.com MiscRegIndex _op1, 13212280Sgiacomo.travaglini@arm.com uint64_t _imm) 13312280Sgiacomo.travaglini@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 13412280Sgiacomo.travaglini@arm.com _dest, _op1, _imm) 13512280Sgiacomo.travaglini@arm.com { 13612280Sgiacomo.travaglini@arm.com %(constructor)s; 13712280Sgiacomo.travaglini@arm.com } 13812280Sgiacomo.travaglini@arm.com}}; 139