misc.isa revision 7331
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def template MrsDeclare {{ 41class %(class_name)s : public %(base_class)s 42{ 43 protected: 44 public: 45 // Constructor 46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); 47 %(BasicExecDeclare)s 48}; 49}}; 50 51def template MrsConstructor {{ 52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 53 IntRegIndex _dest) 54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) 55 { 56 %(constructor)s; 57 } 58}}; 59 60def template MsrRegDeclare {{ 61class %(class_name)s : public %(base_class)s 62{ 63 protected: 64 public: 65 // Constructor 66 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); 67 %(BasicExecDeclare)s 68}; 69}}; 70 71def template MsrRegConstructor {{ 72 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 73 IntRegIndex _op1, 74 uint8_t mask) 75 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) 76 { 77 %(constructor)s; 78 } 79}}; 80 81def template MsrImmDeclare {{ 82class %(class_name)s : public %(base_class)s 83{ 84 protected: 85 public: 86 // Constructor 87 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); 88 %(BasicExecDeclare)s 89}; 90}}; 91 92def template MsrImmConstructor {{ 93 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 94 uint32_t imm, 95 uint8_t mask) 96 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) 97 { 98 %(constructor)s; 99 } 100}}; 101 102def template ImmOpDeclare {{ 103class %(class_name)s : public %(base_class)s 104{ 105 protected: 106 public: 107 // Constructor 108 %(class_name)s(ExtMachInst machInst, uint64_t _imm); 109 %(BasicExecDeclare)s 110}; 111}}; 112 113def template ImmOpConstructor {{ 114 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 115 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 116 { 117 %(constructor)s; 118 } 119}}; 120 121def template RegRegOpDeclare {{ 122class %(class_name)s : public %(base_class)s 123{ 124 protected: 125 public: 126 // Constructor 127 %(class_name)s(ExtMachInst machInst, 128 IntRegIndex _dest, IntRegIndex _op1); 129 %(BasicExecDeclare)s 130}; 131}}; 132 133def template RegRegOpConstructor {{ 134 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 135 IntRegIndex _dest, IntRegIndex _op1) 136 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) 137 { 138 %(constructor)s; 139 } 140}}; 141 142def template RegRegRegImmOpDeclare {{ 143class %(class_name)s : public %(base_class)s 144{ 145 protected: 146 public: 147 // Constructor 148 %(class_name)s(ExtMachInst machInst, 149 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 150 uint64_t _imm); 151 %(BasicExecDeclare)s 152}; 153}}; 154 155def template RegRegRegImmOpConstructor {{ 156 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 157 IntRegIndex _dest, 158 IntRegIndex _op1, 159 IntRegIndex _op2, 160 uint64_t _imm) 161 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 162 _dest, _op1, _op2, _imm) 163 { 164 %(constructor)s; 165 } 166}}; 167 168def template RegRegRegRegOpDeclare {{ 169class %(class_name)s : public %(base_class)s 170{ 171 protected: 172 public: 173 // Constructor 174 %(class_name)s(ExtMachInst machInst, 175 IntRegIndex _dest, IntRegIndex _op1, 176 IntRegIndex _op2, IntRegIndex _op3); 177 %(BasicExecDeclare)s 178}; 179}}; 180 181def template RegRegRegRegOpConstructor {{ 182 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 183 IntRegIndex _dest, 184 IntRegIndex _op1, 185 IntRegIndex _op2, 186 IntRegIndex _op3) 187 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 188 _dest, _op1, _op2, _op3) 189 { 190 %(constructor)s; 191 } 192}}; 193 194def template RegRegRegOpDeclare {{ 195class %(class_name)s : public %(base_class)s 196{ 197 protected: 198 public: 199 // Constructor 200 %(class_name)s(ExtMachInst machInst, 201 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); 202 %(BasicExecDeclare)s 203}; 204}}; 205 206def template RegRegRegOpConstructor {{ 207 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 208 IntRegIndex _dest, 209 IntRegIndex _op1, 210 IntRegIndex _op2) 211 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 212 _dest, _op1, _op2) 213 { 214 %(constructor)s; 215 } 216}}; 217 218def template RegRegImmOpDeclare {{ 219class %(class_name)s : public %(base_class)s 220{ 221 protected: 222 public: 223 // Constructor 224 %(class_name)s(ExtMachInst machInst, 225 IntRegIndex _dest, IntRegIndex _op1, 226 uint64_t _imm); 227 %(BasicExecDeclare)s 228}; 229}}; 230 231def template RegRegImmOpConstructor {{ 232 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 233 IntRegIndex _dest, 234 IntRegIndex _op1, 235 uint64_t _imm) 236 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 237 _dest, _op1, _imm) 238 { 239 %(constructor)s; 240 } 241}}; 242 243def template RegRegImmImmOpDeclare {{ 244class %(class_name)s : public %(base_class)s 245{ 246 protected: 247 public: 248 // Constructor 249 %(class_name)s(ExtMachInst machInst, 250 IntRegIndex _dest, IntRegIndex _op1, 251 uint64_t _imm1, uint64_t _imm2); 252 %(BasicExecDeclare)s 253}; 254}}; 255 256def template RegRegImmImmOpConstructor {{ 257 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 258 IntRegIndex _dest, 259 IntRegIndex _op1, 260 uint64_t _imm1, 261 uint64_t _imm2) 262 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 263 _dest, _op1, _imm1, _imm2) 264 { 265 %(constructor)s; 266 } 267}}; 268 269def template RegImmRegOpDeclare {{ 270class %(class_name)s : public %(base_class)s 271{ 272 protected: 273 public: 274 // Constructor 275 %(class_name)s(ExtMachInst machInst, 276 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); 277 %(BasicExecDeclare)s 278}; 279}}; 280 281def template RegImmRegOpConstructor {{ 282 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 283 IntRegIndex _dest, 284 uint64_t _imm, 285 IntRegIndex _op1) 286 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 287 _dest, _imm, _op1) 288 { 289 %(constructor)s; 290 } 291}}; 292 293def template RegImmRegShiftOpDeclare {{ 294class %(class_name)s : public %(base_class)s 295{ 296 protected: 297 public: 298 // Constructor 299 %(class_name)s(ExtMachInst machInst, 300 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, 301 int32_t _shiftAmt, ArmShiftType _shiftType); 302 %(BasicExecDeclare)s 303}; 304}}; 305 306def template RegImmRegShiftOpConstructor {{ 307 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 308 IntRegIndex _dest, 309 uint64_t _imm, 310 IntRegIndex _op1, 311 int32_t _shiftAmt, 312 ArmShiftType _shiftType) 313 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 314 _dest, _imm, _op1, _shiftAmt, _shiftType) 315 { 316 %(constructor)s; 317 } 318}}; 319