misc.isa revision 10184
12817Sksewell@umich.edu// -*- mode:c++ -*- 22817Sksewell@umich.edu 32817Sksewell@umich.edu// Copyright (c) 2010-2013 ARM Limited 42817Sksewell@umich.edu// All rights reserved 52817Sksewell@umich.edu// 62817Sksewell@umich.edu// The license below extends only to copyright in the software and shall 72817Sksewell@umich.edu// not be construed as granting a license to any other intellectual 82817Sksewell@umich.edu// property including but not limited to intellectual property relating 92817Sksewell@umich.edu// to a hardware implementation of the functionality of the software 102817Sksewell@umich.edu// licensed hereunder. You may use the software subject to the license 112817Sksewell@umich.edu// terms below provided that you ensure that this notice is replicated 122817Sksewell@umich.edu// unmodified and in its entirety in all distributions of the software, 132817Sksewell@umich.edu// modified or unmodified, in source code or in binary form. 142817Sksewell@umich.edu// 152817Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 162817Sksewell@umich.edu// modification, are permitted provided that the following conditions are 172817Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 182817Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 192817Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 202817Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 212817Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 222817Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 232817Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 242817Sksewell@umich.edu// this software without specific prior written permission. 252817Sksewell@umich.edu// 262817Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272817Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282817Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292817Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302817Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312817Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 323776Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 332817Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342834Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352817Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362817Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372817Sksewell@umich.edu// 382817Sksewell@umich.edu// Authors: Gabe Black 395499Ssaidi@eecs.umich.edu 402817Sksewell@umich.edudef template MrsDeclare {{ 415499Ssaidi@eecs.umich.educlass %(class_name)s : public %(base_class)s 422817Sksewell@umich.edu{ 432817Sksewell@umich.edu protected: 442817Sksewell@umich.edu public: 452817Sksewell@umich.edu // Constructor 462817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); 472817Sksewell@umich.edu %(BasicExecDeclare)s 483126Sktlim@umich.edu}; 492817Sksewell@umich.edu}}; 502817Sksewell@umich.edu 512817Sksewell@umich.edudef template MrsConstructor {{ 522817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 532817Sksewell@umich.edu IntRegIndex _dest) 542817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) 552817Sksewell@umich.edu { 562817Sksewell@umich.edu %(constructor)s; 572817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 582817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 592817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 602817Sksewell@umich.edu } 612817Sksewell@umich.edu } 622817Sksewell@umich.edu } 632817Sksewell@umich.edu}}; 642817Sksewell@umich.edu 652817Sksewell@umich.edudef template MrsBankedRegDeclare {{ 665714Shsul@eecs.umich.educlass %(class_name)s : public %(base_class)s 675715Shsul@eecs.umich.edu{ 682817Sksewell@umich.edu protected: 692817Sksewell@umich.edu uint8_t byteMask; 702817Sksewell@umich.edu bool r; 712817Sksewell@umich.edu 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu // Constructor 742817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 752817Sksewell@umich.edu uint8_t _sysM, bool _r); 762817Sksewell@umich.edu %(BasicExecDeclare)s 772817Sksewell@umich.edu}; 782817Sksewell@umich.edu}}; 792817Sksewell@umich.edu 802817Sksewell@umich.edudef template MrsBankedRegConstructor {{ 812817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 822817Sksewell@umich.edu IntRegIndex _dest, 832817Sksewell@umich.edu uint8_t _sysM, 842817Sksewell@umich.edu bool _r) 852817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest), 862817Sksewell@umich.edu byteMask(_sysM), r(_r) 872817Sksewell@umich.edu { 882817Sksewell@umich.edu %(constructor)s; 892817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 902817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 912817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 922817Sksewell@umich.edu } 932817Sksewell@umich.edu } 942817Sksewell@umich.edu } 952817Sksewell@umich.edu}}; 962817Sksewell@umich.edu 972817Sksewell@umich.edudef template MsrBankedRegDeclare {{ 982875Sksewell@umich.educlass %(class_name)s : public %(base_class)s 995715Shsul@eecs.umich.edu{ 1002817Sksewell@umich.edu protected: 1012817Sksewell@umich.edu bool r; 1022817Sksewell@umich.edu 1032817Sksewell@umich.edu public: 1042817Sksewell@umich.edu // Constructor 1052817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 1062817Sksewell@umich.edu uint8_t _sysM, bool _r); 1072817Sksewell@umich.edu %(BasicExecDeclare)s 1082817Sksewell@umich.edu}; 1095715Shsul@eecs.umich.edu}}; 1102817Sksewell@umich.edu 1112817Sksewell@umich.edudef template MsrBankedRegConstructor {{ 1122817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1132817Sksewell@umich.edu IntRegIndex _op1, 1142817Sksewell@umich.edu uint8_t _sysM, 1152817Sksewell@umich.edu bool _r) 1165715Shsul@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM), 1172817Sksewell@umich.edu r(_r) 1182817Sksewell@umich.edu { 1192817Sksewell@umich.edu %(constructor)s; 1202817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 1215250Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 1222817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1232875Sksewell@umich.edu } 1245715Shsul@eecs.umich.edu } 1252817Sksewell@umich.edu } 1262817Sksewell@umich.edu}}; 1272817Sksewell@umich.edu 1282817Sksewell@umich.edudef template MsrRegDeclare {{ 1292817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 1302817Sksewell@umich.edu{ 1312817Sksewell@umich.edu protected: 1322817Sksewell@umich.edu public: 1332817Sksewell@umich.edu // Constructor 1342817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); 1352817Sksewell@umich.edu %(BasicExecDeclare)s 1365704Snate@binkert.org}; 1372817Sksewell@umich.edu}}; 1382817Sksewell@umich.edu 1392817Sksewell@umich.edudef template MsrRegConstructor {{ 1402817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1412817Sksewell@umich.edu IntRegIndex _op1, 1422817Sksewell@umich.edu uint8_t mask) 1435715Shsul@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) 1442817Sksewell@umich.edu { 1452817Sksewell@umich.edu %(constructor)s; 1462817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 1472817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 1482875Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1492817Sksewell@umich.edu } 1503221Sktlim@umich.edu } 1515715Shsul@eecs.umich.edu } 1522817Sksewell@umich.edu}}; 1532817Sksewell@umich.edu 1542817Sksewell@umich.edudef template MsrImmDeclare {{ 1552817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 1562817Sksewell@umich.edu{ 1575715Shsul@eecs.umich.edu protected: 1582817Sksewell@umich.edu public: 1592817Sksewell@umich.edu // Constructor 1602817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); 1612817Sksewell@umich.edu %(BasicExecDeclare)s 1625250Sksewell@umich.edu}; 1632817Sksewell@umich.edu}}; 1642875Sksewell@umich.edu 1655715Shsul@eecs.umich.edudef template MsrImmConstructor {{ 1662817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1672817Sksewell@umich.edu uint32_t imm, 1682817Sksewell@umich.edu uint8_t mask) 1692817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) 1702817Sksewell@umich.edu { 1715715Shsul@eecs.umich.edu %(constructor)s; 1722817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 1732817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 1742817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1752817Sksewell@umich.edu } 1762817Sksewell@umich.edu } 1772817Sksewell@umich.edu } 1782817Sksewell@umich.edu}}; 1793548Sgblack@eecs.umich.edu 1802817Sksewell@umich.edudef template MrrcOpDeclare {{ 1812817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 1822817Sksewell@umich.edu{ 1832817Sksewell@umich.edu protected: 1842817Sksewell@umich.edu public: 1852817Sksewell@umich.edu // Constructor 1862817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 1872817Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm); 1882817Sksewell@umich.edu %(BasicExecDeclare)s 1892817Sksewell@umich.edu}; 1902817Sksewell@umich.edu}}; 1912817Sksewell@umich.edu 1922817Sksewell@umich.edudef template MrrcOpConstructor {{ 1932817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1942817Sksewell@umich.edu IntRegIndex op1, 1952817Sksewell@umich.edu IntRegIndex dest, 1962817Sksewell@umich.edu IntRegIndex dest2, 1972817Sksewell@umich.edu uint32_t imm) 1982817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest, 1992817Sksewell@umich.edu dest2, imm) 2002817Sksewell@umich.edu { 2012817Sksewell@umich.edu %(constructor)s; 2022817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 2032817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 2042817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2052817Sksewell@umich.edu } 2062817Sksewell@umich.edu } 2072817Sksewell@umich.edu } 2082817Sksewell@umich.edu}}; 2092817Sksewell@umich.edu 2102817Sksewell@umich.edudef template McrrOpDeclare {{ 2112817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 2122817Sksewell@umich.edu{ 2132817Sksewell@umich.edu protected: 2142817Sksewell@umich.edu public: 2152817Sksewell@umich.edu // Constructor 2162817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, 2172817Sksewell@umich.edu IntRegIndex _dest, uint32_t imm); 2182817Sksewell@umich.edu %(BasicExecDeclare)s 2192817Sksewell@umich.edu}; 2202817Sksewell@umich.edu}}; 2212817Sksewell@umich.edu 2222817Sksewell@umich.edudef template McrrOpConstructor {{ 2232817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 2243126Sktlim@umich.edu IntRegIndex op1, 2253126Sktlim@umich.edu IntRegIndex op2, 2263126Sktlim@umich.edu IntRegIndex dest, 2272817Sksewell@umich.edu uint32_t imm) 2282817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2, 2292817Sksewell@umich.edu dest, imm) 2302817Sksewell@umich.edu { 2313126Sktlim@umich.edu %(constructor)s; 2323126Sktlim@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 2333126Sktlim@umich.edu for (int x = 0; x < _numDestRegs; x++) { 2342817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2352817Sksewell@umich.edu } 2362817Sksewell@umich.edu } 2372817Sksewell@umich.edu } 2382817Sksewell@umich.edu}}; 2392817Sksewell@umich.edu 2402817Sksewell@umich.edudef template ImmOpDeclare {{ 2412817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 2422817Sksewell@umich.edu{ 2432817Sksewell@umich.edu protected: 2442817Sksewell@umich.edu public: 2452817Sksewell@umich.edu // Constructor 2462817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, uint64_t _imm); 2472817Sksewell@umich.edu %(BasicExecDeclare)s 2482817Sksewell@umich.edu}; 2495715Shsul@eecs.umich.edu}}; 2502817Sksewell@umich.edu 2512817Sksewell@umich.edudef template ImmOpConstructor {{ 2522817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 2532817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 2542817Sksewell@umich.edu { 2552817Sksewell@umich.edu %(constructor)s; 2562817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 2572817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 2582817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2592817Sksewell@umich.edu } 2602817Sksewell@umich.edu } 2612817Sksewell@umich.edu } 2622817Sksewell@umich.edu}}; 2632817Sksewell@umich.edu 2642817Sksewell@umich.edudef template RegImmOpDeclare {{ 2652817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 2662817Sksewell@umich.edu{ 2672817Sksewell@umich.edu protected: 2682817Sksewell@umich.edu public: 2692817Sksewell@umich.edu // Constructor 2702817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); 2712817Sksewell@umich.edu %(BasicExecDeclare)s 2722986Sgblack@eecs.umich.edu}; 2732817Sksewell@umich.edu}}; 2745258Sksewell@umich.edu 2755258Sksewell@umich.edudef template RegImmOpConstructor {{ 2762817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 2772817Sksewell@umich.edu IntRegIndex _dest, uint64_t _imm) 2785258Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) 2795258Sksewell@umich.edu { 2805258Sksewell@umich.edu %(constructor)s; 2812817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 2822817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 2832817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2842817Sksewell@umich.edu } 2852817Sksewell@umich.edu } 2862817Sksewell@umich.edu } 2872817Sksewell@umich.edu}}; 2882817Sksewell@umich.edu 2892817Sksewell@umich.edudef template RegRegOpDeclare {{ 2902817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 2912817Sksewell@umich.edu{ 2922817Sksewell@umich.edu protected: 2932817Sksewell@umich.edu public: 2942817Sksewell@umich.edu // Constructor 2953776Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 2965715Shsul@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1); 2972817Sksewell@umich.edu %(BasicExecDeclare)s 2982817Sksewell@umich.edu}; 2992817Sksewell@umich.edu}}; 3002986Sgblack@eecs.umich.edu 3012817Sksewell@umich.edudef template RegRegOpConstructor {{ 3022817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3035258Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _op1) 3042817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) 3052817Sksewell@umich.edu { 3065715Shsul@eecs.umich.edu %(constructor)s; 3072817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 3085715Shsul@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 3092817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3102817Sksewell@umich.edu } 3112817Sksewell@umich.edu } 3122817Sksewell@umich.edu } 3132817Sksewell@umich.edu}}; 3142817Sksewell@umich.edu 3152817Sksewell@umich.edudef template RegRegRegImmOpDeclare {{ 3162986Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 3172817Sksewell@umich.edu{ 3182817Sksewell@umich.edu protected: 3195258Sksewell@umich.edu public: 3205715Shsul@eecs.umich.edu // Constructor 3212817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 3222817Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 3232817Sksewell@umich.edu uint64_t _imm); 3242986Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3252817Sksewell@umich.edu}; 3262817Sksewell@umich.edu}}; 3272817Sksewell@umich.edu 3285258Sksewell@umich.edudef template RegRegRegImmOpConstructor {{ 3295715Shsul@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3302817Sksewell@umich.edu IntRegIndex _dest, 3312817Sksewell@umich.edu IntRegIndex _op1, 3322817Sksewell@umich.edu IntRegIndex _op2, 3332986Sgblack@eecs.umich.edu uint64_t _imm) 3342817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3352817Sksewell@umich.edu _dest, _op1, _op2, _imm) 3365258Sksewell@umich.edu { 3375715Shsul@eecs.umich.edu %(constructor)s; 3382817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 3392817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 3402817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3412817Sksewell@umich.edu } 3422817Sksewell@umich.edu } 3432817Sksewell@umich.edu } 3443776Sgblack@eecs.umich.edu}}; 3455715Shsul@eecs.umich.edu 3462817Sksewell@umich.edudef template RegRegRegRegOpDeclare {{ 3472817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 3482817Sksewell@umich.edu{ 3495715Shsul@eecs.umich.edu protected: 3502817Sksewell@umich.edu public: 3512817Sksewell@umich.edu // Constructor 3522817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 3532817Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _op1, 3542817Sksewell@umich.edu IntRegIndex _op2, IntRegIndex _op3); 3552817Sksewell@umich.edu %(BasicExecDeclare)s 3562817Sksewell@umich.edu}; 3575258Sksewell@umich.edu}}; 3582817Sksewell@umich.edu 3592817Sksewell@umich.edudef template RegRegRegRegOpConstructor {{ 3605715Shsul@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3612817Sksewell@umich.edu IntRegIndex _dest, 3622817Sksewell@umich.edu IntRegIndex _op1, 3635715Shsul@eecs.umich.edu IntRegIndex _op2, 3642817Sksewell@umich.edu IntRegIndex _op3) 3652817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3662817Sksewell@umich.edu _dest, _op1, _op2, _op3) 3672817Sksewell@umich.edu { 3682817Sksewell@umich.edu %(constructor)s; 3695715Shsul@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 3702817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 3712817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3722817Sksewell@umich.edu } 3732817Sksewell@umich.edu } 3742817Sksewell@umich.edu } 3752817Sksewell@umich.edu}}; 3762817Sksewell@umich.edu 3775258Sksewell@umich.edudef template RegRegRegOpDeclare {{ 3785715Shsul@eecs.umich.educlass %(class_name)s : public %(base_class)s 3792817Sksewell@umich.edu{ 3802817Sksewell@umich.edu protected: 3815715Shsul@eecs.umich.edu public: 3822817Sksewell@umich.edu // Constructor 3832817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 3842817Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); 3852817Sksewell@umich.edu %(BasicExecDeclare)s 3862817Sksewell@umich.edu}; 3872817Sksewell@umich.edu}}; 3882817Sksewell@umich.edu 3892817Sksewell@umich.edudef template RegRegRegOpConstructor {{ 3902817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3915258Sksewell@umich.edu IntRegIndex _dest, 3925715Shsul@eecs.umich.edu IntRegIndex _op1, 3932817Sksewell@umich.edu IntRegIndex _op2) 3942817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3952817Sksewell@umich.edu _dest, _op1, _op2) 3965715Shsul@eecs.umich.edu { 3972817Sksewell@umich.edu %(constructor)s; 3982817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 3992817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 4002817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4012817Sksewell@umich.edu } 4022817Sksewell@umich.edu } 4032817Sksewell@umich.edu } 4045258Sksewell@umich.edu}}; 4055715Shsul@eecs.umich.edu 4062817Sksewell@umich.edudef template RegRegImmOpDeclare {{ 4072817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 4082817Sksewell@umich.edu{ 4095715Shsul@eecs.umich.edu protected: 4102817Sksewell@umich.edu public: 4112817Sksewell@umich.edu // Constructor 4122817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 4132817Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _op1, 4142817Sksewell@umich.edu uint64_t _imm); 4152817Sksewell@umich.edu %(BasicExecDeclare)s 4162817Sksewell@umich.edu}; 4175715Shsul@eecs.umich.edu}}; 4182817Sksewell@umich.edu 4192817Sksewell@umich.edudef template RegRegImmOpConstructor {{ 4202817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 4215715Shsul@eecs.umich.edu IntRegIndex _dest, 4222817Sksewell@umich.edu IntRegIndex _op1, 4232817Sksewell@umich.edu uint64_t _imm) 4242817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4252817Sksewell@umich.edu _dest, _op1, _imm) 4262817Sksewell@umich.edu { 4272817Sksewell@umich.edu %(constructor)s; 4282817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 4295715Shsul@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 4302817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4312817Sksewell@umich.edu } 4322817Sksewell@umich.edu } 4335715Shsul@eecs.umich.edu } 4342817Sksewell@umich.edu}}; 4352817Sksewell@umich.edu 4362817Sksewell@umich.edudef template RegImmImmOpDeclare {{ 4372817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 4383468Sgblack@eecs.umich.edu{ 4395258Sksewell@umich.edu protected: 4405258Sksewell@umich.edu public: 4415715Shsul@eecs.umich.edu // Constructor 4425258Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 4435258Sksewell@umich.edu IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2); 4445258Sksewell@umich.edu %(BasicExecDeclare)s 4455715Shsul@eecs.umich.edu}; 4465258Sksewell@umich.edu}}; 4475258Sksewell@umich.edu 4485258Sksewell@umich.edudef template RegImmImmOpConstructor {{ 4495258Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 4505258Sksewell@umich.edu IntRegIndex _dest, 4515258Sksewell@umich.edu uint64_t _imm1, 4525258Sksewell@umich.edu uint64_t _imm2) 4535715Shsul@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4545258Sksewell@umich.edu _dest, _imm1, _imm2) 4555258Sksewell@umich.edu { 4565258Sksewell@umich.edu %(constructor)s; 4575715Shsul@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 4585258Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 4595258Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4605258Sksewell@umich.edu } 4615258Sksewell@umich.edu } 4625258Sksewell@umich.edu } 4634172Ssaidi@eecs.umich.edu}}; 4642817Sksewell@umich.edu 4655715Shsul@eecs.umich.edudef template RegRegImmImmOpDeclare {{ 4662817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 4672817Sksewell@umich.edu{ 4682817Sksewell@umich.edu protected: 4695715Shsul@eecs.umich.edu public: 4702817Sksewell@umich.edu // Constructor 4712817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 4722817Sksewell@umich.edu IntRegIndex _dest, IntRegIndex _op1, 4732817Sksewell@umich.edu uint64_t _imm1, uint64_t _imm2); 4743468Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4754172Ssaidi@eecs.umich.edu}; 4762817Sksewell@umich.edu}}; 4772817Sksewell@umich.edu 4785715Shsul@eecs.umich.edudef template RegRegImmImmOpConstructor {{ 4792817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 4802817Sksewell@umich.edu IntRegIndex _dest, 4812817Sksewell@umich.edu IntRegIndex _op1, 4825715Shsul@eecs.umich.edu uint64_t _imm1, 4832817Sksewell@umich.edu uint64_t _imm2) 4842817Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4852817Sksewell@umich.edu _dest, _op1, _imm1, _imm2) 4862817Sksewell@umich.edu { 4872817Sksewell@umich.edu %(constructor)s; 4882817Sksewell@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 4892817Sksewell@umich.edu for (int x = 0; x < _numDestRegs; x++) { 4902817Sksewell@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4912817Sksewell@umich.edu } 4925715Shsul@eecs.umich.edu } 4932817Sksewell@umich.edu } 4942817Sksewell@umich.edu}}; 4952817Sksewell@umich.edu 4962817Sksewell@umich.edudef template RegImmRegOpDeclare {{ 4972817Sksewell@umich.educlass %(class_name)s : public %(base_class)s 4982817Sksewell@umich.edu{ 4995715Shsul@eecs.umich.edu protected: 5002817Sksewell@umich.edu public: 5012817Sksewell@umich.edu // Constructor 5022817Sksewell@umich.edu %(class_name)s(ExtMachInst machInst, 5032817Sksewell@umich.edu IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); 5042817Sksewell@umich.edu %(BasicExecDeclare)s 5052817Sksewell@umich.edu}; 5065715Shsul@eecs.umich.edu}}; 5072817Sksewell@umich.edu 5082817Sksewell@umich.edudef template RegImmRegOpConstructor {{ 5092817Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 5102817Sksewell@umich.edu IntRegIndex _dest, 511 uint64_t _imm, 512 IntRegIndex _op1) 513 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 514 _dest, _imm, _op1) 515 { 516 %(constructor)s; 517 if (!(condCode == COND_AL || condCode == COND_UC)) { 518 for (int x = 0; x < _numDestRegs; x++) { 519 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 520 } 521 } 522 } 523}}; 524 525def template RegImmRegShiftOpDeclare {{ 526class %(class_name)s : public %(base_class)s 527{ 528 protected: 529 public: 530 // Constructor 531 %(class_name)s(ExtMachInst machInst, 532 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, 533 int32_t _shiftAmt, ArmShiftType _shiftType); 534 %(BasicExecDeclare)s 535}; 536}}; 537 538def template RegImmRegShiftOpConstructor {{ 539 %(class_name)s::%(class_name)s(ExtMachInst machInst, 540 IntRegIndex _dest, 541 uint64_t _imm, 542 IntRegIndex _op1, 543 int32_t _shiftAmt, 544 ArmShiftType _shiftType) 545 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 546 _dest, _imm, _op1, _shiftAmt, _shiftType) 547 { 548 %(constructor)s; 549 if (!(condCode == COND_AL || condCode == COND_UC)) { 550 for (int x = 0; x < _numDestRegs; x++) { 551 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 552 } 553 } 554 } 555}}; 556 557