mem.isa revision 7291:2d21be52e57f
14276Sgblack@eecs.umich.edu// -*- mode:c++ -*- 24276Sgblack@eecs.umich.edu 34276Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 44276Sgblack@eecs.umich.edu// All rights reserved 54276Sgblack@eecs.umich.edu// 64276Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 74276Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 84276Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 94276Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 104276Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 114276Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 124276Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 134276Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 144276Sgblack@eecs.umich.edu// 154276Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 164276Sgblack@eecs.umich.edu// All rights reserved. 174276Sgblack@eecs.umich.edu// 184276Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 194276Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 204276Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 214276Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 224276Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 234276Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 244276Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 254276Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 264276Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 274276Sgblack@eecs.umich.edu// this software without specific prior written permission. 284276Sgblack@eecs.umich.edu// 294276Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304276Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314276Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324276Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334276Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344276Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354276Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364276Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374276Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384276Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394276Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404276Sgblack@eecs.umich.edu// 414276Sgblack@eecs.umich.edu// Authors: Stephen Hines 424276Sgblack@eecs.umich.edu 434276Sgblack@eecs.umich.edu 444276Sgblack@eecs.umich.edudef template SwapExecute {{ 454276Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474276Sgblack@eecs.umich.edu { 484276Sgblack@eecs.umich.edu Addr EA; 494276Sgblack@eecs.umich.edu Fault fault = NoFault; 504276Sgblack@eecs.umich.edu 514276Sgblack@eecs.umich.edu %(op_decl)s; 524276Sgblack@eecs.umich.edu uint64_t memData = 0; 534276Sgblack@eecs.umich.edu %(op_rd)s; 544276Sgblack@eecs.umich.edu %(ea_code)s; 554276Sgblack@eecs.umich.edu 564276Sgblack@eecs.umich.edu if (%(predicate_test)s) 574276Sgblack@eecs.umich.edu { 584276Sgblack@eecs.umich.edu %(preacc_code)s; 594276Sgblack@eecs.umich.edu 604276Sgblack@eecs.umich.edu if (fault == NoFault) { 614711Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 624276Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 634276Sgblack@eecs.umich.edu } 644276Sgblack@eecs.umich.edu 654276Sgblack@eecs.umich.edu if (fault == NoFault) { 664276Sgblack@eecs.umich.edu %(postacc_code)s; 674276Sgblack@eecs.umich.edu } 684276Sgblack@eecs.umich.edu 694276Sgblack@eecs.umich.edu if (fault == NoFault) { 704712Sgblack@eecs.umich.edu %(op_wb)s; 714711Sgblack@eecs.umich.edu } 724712Sgblack@eecs.umich.edu } 734828Sgblack@eecs.umich.edu 744712Sgblack@eecs.umich.edu return fault; 754276Sgblack@eecs.umich.edu } 764276Sgblack@eecs.umich.edu}}; 774276Sgblack@eecs.umich.edu 784276Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 794276Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 804276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 814712Sgblack@eecs.umich.edu { 824712Sgblack@eecs.umich.edu Addr EA; 834730Sgblack@eecs.umich.edu Fault fault = NoFault; 844760Sgblack@eecs.umich.edu 854730Sgblack@eecs.umich.edu %(op_decl)s; 864712Sgblack@eecs.umich.edu uint64_t memData = 0; 874712Sgblack@eecs.umich.edu %(op_rd)s; 884712Sgblack@eecs.umich.edu %(ea_code)s; 894276Sgblack@eecs.umich.edu 904760Sgblack@eecs.umich.edu if (%(predicate_test)s) 914760Sgblack@eecs.umich.edu { 924760Sgblack@eecs.umich.edu %(preacc_code)s; 934760Sgblack@eecs.umich.edu 944760Sgblack@eecs.umich.edu if (fault == NoFault) { 954760Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 964760Sgblack@eecs.umich.edu memAccessFlags, &memData); 974760Sgblack@eecs.umich.edu } 984760Sgblack@eecs.umich.edu 994760Sgblack@eecs.umich.edu if (fault == NoFault) { 1004760Sgblack@eecs.umich.edu %(op_wb)s; 1014760Sgblack@eecs.umich.edu } 1024760Sgblack@eecs.umich.edu } 1034760Sgblack@eecs.umich.edu 1044760Sgblack@eecs.umich.edu return fault; 1054760Sgblack@eecs.umich.edu } 1064760Sgblack@eecs.umich.edu}}; 1074760Sgblack@eecs.umich.edu 1084760Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1094760Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1104760Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1114760Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1124760Sgblack@eecs.umich.edu { 1134760Sgblack@eecs.umich.edu Fault fault = NoFault; 1144760Sgblack@eecs.umich.edu 1154760Sgblack@eecs.umich.edu %(op_decl)s; 1164760Sgblack@eecs.umich.edu %(op_rd)s; 1174760Sgblack@eecs.umich.edu 1184760Sgblack@eecs.umich.edu if (%(predicate_test)s) 1194760Sgblack@eecs.umich.edu { 1204760Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1214760Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1224760Sgblack@eecs.umich.edu 1234760Sgblack@eecs.umich.edu %(postacc_code)s; 1244760Sgblack@eecs.umich.edu 1254760Sgblack@eecs.umich.edu if (fault == NoFault) { 1264760Sgblack@eecs.umich.edu %(op_wb)s; 1274760Sgblack@eecs.umich.edu } 1284760Sgblack@eecs.umich.edu } 1294760Sgblack@eecs.umich.edu 1304760Sgblack@eecs.umich.edu return fault; 1314760Sgblack@eecs.umich.edu } 1324760Sgblack@eecs.umich.edu}}; 1334760Sgblack@eecs.umich.edu 1344760Sgblack@eecs.umich.edudef template LoadExecute {{ 1354760Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1364276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1374276Sgblack@eecs.umich.edu { 1384712Sgblack@eecs.umich.edu Addr EA; 1394712Sgblack@eecs.umich.edu Fault fault = NoFault; 1404712Sgblack@eecs.umich.edu 1414712Sgblack@eecs.umich.edu %(op_decl)s; 1424712Sgblack@eecs.umich.edu %(op_rd)s; 1434712Sgblack@eecs.umich.edu %(ea_code)s; 1444712Sgblack@eecs.umich.edu 1454712Sgblack@eecs.umich.edu if (%(predicate_test)s) 1464276Sgblack@eecs.umich.edu { 1474276Sgblack@eecs.umich.edu if (fault == NoFault) { 1484276Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1494276Sgblack@eecs.umich.edu %(memacc_code)s; 1504276Sgblack@eecs.umich.edu } 1514276Sgblack@eecs.umich.edu 1524276Sgblack@eecs.umich.edu if (fault == NoFault) { 1534276Sgblack@eecs.umich.edu %(op_wb)s; 1544276Sgblack@eecs.umich.edu } 1554276Sgblack@eecs.umich.edu } 1564276Sgblack@eecs.umich.edu 1574276Sgblack@eecs.umich.edu return fault; 1584276Sgblack@eecs.umich.edu } 1594276Sgblack@eecs.umich.edu}}; 1604276Sgblack@eecs.umich.edu 1614276Sgblack@eecs.umich.edudef template StoreExecute {{ 1624276Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1634276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1644276Sgblack@eecs.umich.edu { 1654276Sgblack@eecs.umich.edu Addr EA; 1664276Sgblack@eecs.umich.edu Fault fault = NoFault; 1674276Sgblack@eecs.umich.edu 1684712Sgblack@eecs.umich.edu %(op_decl)s; 1694712Sgblack@eecs.umich.edu %(op_rd)s; 1704712Sgblack@eecs.umich.edu %(ea_code)s; 1714712Sgblack@eecs.umich.edu 1724712Sgblack@eecs.umich.edu if (%(predicate_test)s) 1734712Sgblack@eecs.umich.edu { 1744730Sgblack@eecs.umich.edu if (fault == NoFault) { 1754712Sgblack@eecs.umich.edu %(memacc_code)s; 1764276Sgblack@eecs.umich.edu } 1774276Sgblack@eecs.umich.edu 1784712Sgblack@eecs.umich.edu if (fault == NoFault) { 1794712Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1804712Sgblack@eecs.umich.edu memAccessFlags, NULL); 1814712Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 1824712Sgblack@eecs.umich.edu } 1834712Sgblack@eecs.umich.edu 1844712Sgblack@eecs.umich.edu if (fault == NoFault) { 1854712Sgblack@eecs.umich.edu %(op_wb)s; 1864276Sgblack@eecs.umich.edu } 1874760Sgblack@eecs.umich.edu } 1884760Sgblack@eecs.umich.edu 1894760Sgblack@eecs.umich.edu return fault; 1904760Sgblack@eecs.umich.edu } 1914760Sgblack@eecs.umich.edu}}; 1924760Sgblack@eecs.umich.edu 1934760Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 1944760Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1954760Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1964760Sgblack@eecs.umich.edu { 1974760Sgblack@eecs.umich.edu Addr EA; 1984760Sgblack@eecs.umich.edu Fault fault = NoFault; 1994760Sgblack@eecs.umich.edu 2004760Sgblack@eecs.umich.edu %(op_decl)s; 2014760Sgblack@eecs.umich.edu %(op_rd)s; 2024760Sgblack@eecs.umich.edu %(ea_code)s; 2034760Sgblack@eecs.umich.edu 2044760Sgblack@eecs.umich.edu if (%(predicate_test)s) 2054760Sgblack@eecs.umich.edu { 2064760Sgblack@eecs.umich.edu if (fault == NoFault) { 2074760Sgblack@eecs.umich.edu %(memacc_code)s; 2084276Sgblack@eecs.umich.edu } 2094276Sgblack@eecs.umich.edu 2104276Sgblack@eecs.umich.edu if (fault == NoFault) { 2114276Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2124276Sgblack@eecs.umich.edu memAccessFlags, NULL); 2134276Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2144276Sgblack@eecs.umich.edu } 2154276Sgblack@eecs.umich.edu 2164276Sgblack@eecs.umich.edu // Need to write back any potential address register update 2174276Sgblack@eecs.umich.edu if (fault == NoFault) { 2184276Sgblack@eecs.umich.edu %(op_wb)s; 2194276Sgblack@eecs.umich.edu } 2204276Sgblack@eecs.umich.edu } 2214276Sgblack@eecs.umich.edu 2224276Sgblack@eecs.umich.edu return fault; 2234276Sgblack@eecs.umich.edu } 2244276Sgblack@eecs.umich.edu}}; 2254276Sgblack@eecs.umich.edu 2264276Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 2274276Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2284276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2294276Sgblack@eecs.umich.edu { 2304276Sgblack@eecs.umich.edu Addr EA; 2314276Sgblack@eecs.umich.edu Fault fault = NoFault; 2324276Sgblack@eecs.umich.edu 2334276Sgblack@eecs.umich.edu %(op_src_decl)s; 2344276Sgblack@eecs.umich.edu %(op_rd)s; 2354276Sgblack@eecs.umich.edu %(ea_code)s; 2364276Sgblack@eecs.umich.edu 2374276Sgblack@eecs.umich.edu if (%(predicate_test)s) 2384276Sgblack@eecs.umich.edu { 2394276Sgblack@eecs.umich.edu if (fault == NoFault) { 2404276Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2414276Sgblack@eecs.umich.edu } 2424276Sgblack@eecs.umich.edu } 2434276Sgblack@eecs.umich.edu 2444276Sgblack@eecs.umich.edu return fault; 2454276Sgblack@eecs.umich.edu } 2464276Sgblack@eecs.umich.edu}}; 2474276Sgblack@eecs.umich.edu 2484276Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 2494276Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2504276Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 2514276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2524276Sgblack@eecs.umich.edu { 2534276Sgblack@eecs.umich.edu Fault fault = NoFault; 2544276Sgblack@eecs.umich.edu 2554276Sgblack@eecs.umich.edu %(op_decl)s; 2564276Sgblack@eecs.umich.edu %(op_rd)s; 2574276Sgblack@eecs.umich.edu 2584276Sgblack@eecs.umich.edu if (%(predicate_test)s) 2594276Sgblack@eecs.umich.edu { 2604276Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 2614276Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 2624276Sgblack@eecs.umich.edu 2634276Sgblack@eecs.umich.edu if (fault == NoFault) { 2644276Sgblack@eecs.umich.edu %(memacc_code)s; 2654276Sgblack@eecs.umich.edu } 2664276Sgblack@eecs.umich.edu 2674276Sgblack@eecs.umich.edu if (fault == NoFault) { 2684276Sgblack@eecs.umich.edu %(op_wb)s; 2694727Sgblack@eecs.umich.edu } 2704727Sgblack@eecs.umich.edu } 2714727Sgblack@eecs.umich.edu 2724727Sgblack@eecs.umich.edu return fault; 2734727Sgblack@eecs.umich.edu } 2744727Sgblack@eecs.umich.edu}}; 2754727Sgblack@eecs.umich.edu 2764727Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 2774727Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2784727Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 2794727Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2804727Sgblack@eecs.umich.edu { 2814727Sgblack@eecs.umich.edu Fault fault = NoFault; 2824727Sgblack@eecs.umich.edu 2834727Sgblack@eecs.umich.edu %(op_decl)s; 2844727Sgblack@eecs.umich.edu %(op_rd)s; 2854727Sgblack@eecs.umich.edu 2864727Sgblack@eecs.umich.edu if (%(predicate_test)s) 2874727Sgblack@eecs.umich.edu { 2884727Sgblack@eecs.umich.edu if (fault == NoFault) { 2894727Sgblack@eecs.umich.edu %(op_wb)s; 2904760Sgblack@eecs.umich.edu } 2914760Sgblack@eecs.umich.edu } 2924760Sgblack@eecs.umich.edu 2934760Sgblack@eecs.umich.edu return fault; 2944760Sgblack@eecs.umich.edu } 2954760Sgblack@eecs.umich.edu}}; 2964760Sgblack@eecs.umich.edu 2974760Sgblack@eecs.umich.edudef template RfeDeclare {{ 2984760Sgblack@eecs.umich.edu /** 2994760Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3004760Sgblack@eecs.umich.edu */ 3014760Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3024760Sgblack@eecs.umich.edu { 3034760Sgblack@eecs.umich.edu public: 3044760Sgblack@eecs.umich.edu 3054760Sgblack@eecs.umich.edu /// Constructor. 3064760Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3074760Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 3084760Sgblack@eecs.umich.edu 3094760Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3104276Sgblack@eecs.umich.edu 3114276Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3124712Sgblack@eecs.umich.edu 3134712Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3144814Sgblack@eecs.umich.edu }; 3154712Sgblack@eecs.umich.edu}}; 3164712Sgblack@eecs.umich.edu 3174712Sgblack@eecs.umich.edudef template SwapDeclare {{ 3184712Sgblack@eecs.umich.edu /** 3194712Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3204276Sgblack@eecs.umich.edu */ 3214276Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3224712Sgblack@eecs.umich.edu { 3234712Sgblack@eecs.umich.edu public: 3244712Sgblack@eecs.umich.edu 3254712Sgblack@eecs.umich.edu /// Constructor. 3264712Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3274712Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 3284712Sgblack@eecs.umich.edu 3294724Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3304276Sgblack@eecs.umich.edu 3314276Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3324712Sgblack@eecs.umich.edu 3334712Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3344712Sgblack@eecs.umich.edu }; 3354712Sgblack@eecs.umich.edu}}; 3364712Sgblack@eecs.umich.edu 3374712Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 3384746Sgblack@eecs.umich.edu /** 3394746Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3404746Sgblack@eecs.umich.edu */ 3414746Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3424746Sgblack@eecs.umich.edu { 3434276Sgblack@eecs.umich.edu public: 3444276Sgblack@eecs.umich.edu 3454712Sgblack@eecs.umich.edu /// Constructor. 3464712Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3474712Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 3484712Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 3494712Sgblack@eecs.umich.edu 3504712Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3514746Sgblack@eecs.umich.edu 3524746Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3534746Sgblack@eecs.umich.edu 3544746Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3554746Sgblack@eecs.umich.edu }; 3564276Sgblack@eecs.umich.edu}}; 3574276Sgblack@eecs.umich.edu 3584276Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 3594276Sgblack@eecs.umich.edu /** 3604276Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3614276Sgblack@eecs.umich.edu */ 3624276Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3634276Sgblack@eecs.umich.edu { 3644276Sgblack@eecs.umich.edu public: 3654276Sgblack@eecs.umich.edu 3664276Sgblack@eecs.umich.edu /// Constructor. 3674726Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3684276Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 3694276Sgblack@eecs.umich.edu 3704276Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3714276Sgblack@eecs.umich.edu 3724276Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3734276Sgblack@eecs.umich.edu 3744276Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3754276Sgblack@eecs.umich.edu }; 3764276Sgblack@eecs.umich.edu}}; 3774276Sgblack@eecs.umich.edu 3784276Sgblack@eecs.umich.edudef template LoadStoreDRegDeclare {{ 3794276Sgblack@eecs.umich.edu /** 3804276Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3814276Sgblack@eecs.umich.edu */ 3824276Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 3834276Sgblack@eecs.umich.edu { 3844276Sgblack@eecs.umich.edu public: 3854276Sgblack@eecs.umich.edu 3864276Sgblack@eecs.umich.edu /// Constructor. 3874276Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 3884276Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 3894276Sgblack@eecs.umich.edu uint32_t _base, bool _add, 3904276Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 3914276Sgblack@eecs.umich.edu uint32_t _index); 3924276Sgblack@eecs.umich.edu 3934276Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3944276Sgblack@eecs.umich.edu 3954276Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 3964276Sgblack@eecs.umich.edu 3974276Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 3984276Sgblack@eecs.umich.edu }; 3994276Sgblack@eecs.umich.edu}}; 4004276Sgblack@eecs.umich.edu 4014276Sgblack@eecs.umich.edudef template LoadStoreRegDeclare {{ 4024276Sgblack@eecs.umich.edu /** 4034276Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4044276Sgblack@eecs.umich.edu */ 4054276Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 4064276Sgblack@eecs.umich.edu { 4074276Sgblack@eecs.umich.edu public: 4084276Sgblack@eecs.umich.edu 4094276Sgblack@eecs.umich.edu /// Constructor. 4104276Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 4114276Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 4124276Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 4134276Sgblack@eecs.umich.edu uint32_t _index); 4144276Sgblack@eecs.umich.edu 4154276Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4164276Sgblack@eecs.umich.edu 4174276Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 4184276Sgblack@eecs.umich.edu 4194276Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4204276Sgblack@eecs.umich.edu }; 4214276Sgblack@eecs.umich.edu}}; 4224276Sgblack@eecs.umich.edu 4234276Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 4244276Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 4254276Sgblack@eecs.umich.edu}}; 4264276Sgblack@eecs.umich.edu 4274276Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 4284276Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 4294276Sgblack@eecs.umich.edu}}; 4304276Sgblack@eecs.umich.edu 4314276Sgblack@eecs.umich.edudef template RfeConstructor {{ 4324276Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 4334276Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 434 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 435 (IntRegIndex)_base, (AddrMode)_mode, _wb) 436 { 437 %(constructor)s; 438 } 439}}; 440 441def template SwapConstructor {{ 442 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 443 uint32_t _dest, uint32_t _op1, uint32_t _base) 444 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 445 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 446 { 447 %(constructor)s; 448 } 449}}; 450 451def template LoadStoreDImmConstructor {{ 452 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 453 uint32_t _dest, uint32_t _dest2, 454 uint32_t _base, bool _add, int32_t _imm) 455 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 456 (IntRegIndex)_dest, (IntRegIndex)_dest2, 457 (IntRegIndex)_base, _add, _imm) 458 { 459 %(constructor)s; 460 } 461}}; 462 463def template LoadStoreImmConstructor {{ 464 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 465 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 466 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 467 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 468 { 469 %(constructor)s; 470 } 471}}; 472 473def template LoadStoreDRegConstructor {{ 474 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 475 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 476 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 477 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 478 (IntRegIndex)_dest, (IntRegIndex)_dest2, 479 (IntRegIndex)_base, _add, 480 _shiftAmt, (ArmShiftType)_shiftType, 481 (IntRegIndex)_index) 482 { 483 %(constructor)s; 484 } 485}}; 486 487def template LoadStoreRegConstructor {{ 488 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 489 uint32_t _dest, uint32_t _base, bool _add, 490 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 491 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 492 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 493 _shiftAmt, (ArmShiftType)_shiftType, 494 (IntRegIndex)_index) 495 { 496 %(constructor)s; 497 } 498}}; 499