mem.isa revision 9573
15331Sgblack@eecs.umich.edu// -*- mode:c++ -*- 25331Sgblack@eecs.umich.edu 35331Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 45331Sgblack@eecs.umich.edu// All rights reserved 55331Sgblack@eecs.umich.edu// 65331Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 75331Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 85331Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 95331Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 105331Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 115331Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 125331Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 135331Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 145331Sgblack@eecs.umich.edu// 155331Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 165331Sgblack@eecs.umich.edu// All rights reserved. 175331Sgblack@eecs.umich.edu// 185331Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 195331Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 205331Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 215331Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 225331Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 235331Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 245331Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 255331Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 265331Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 275331Sgblack@eecs.umich.edu// this software without specific prior written permission. 285331Sgblack@eecs.umich.edu// 295331Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304276Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314276Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324276Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334276Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344276Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354276Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364276Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374276Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384276Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394276Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404276Sgblack@eecs.umich.edu// 414276Sgblack@eecs.umich.edu// Authors: Stephen Hines 424276Sgblack@eecs.umich.edu 434276Sgblack@eecs.umich.edu 444276Sgblack@eecs.umich.edudef template PanicExecute {{ 454276Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 464276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474276Sgblack@eecs.umich.edu { 484276Sgblack@eecs.umich.edu panic("Execute function executed when it shouldn't be!\n"); 494276Sgblack@eecs.umich.edu return NoFault; 504276Sgblack@eecs.umich.edu } 514276Sgblack@eecs.umich.edu}}; 524276Sgblack@eecs.umich.edu 534276Sgblack@eecs.umich.edudef template PanicInitiateAcc {{ 544276Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 554276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 564276Sgblack@eecs.umich.edu { 574276Sgblack@eecs.umich.edu panic("InitiateAcc function executed when it shouldn't be!\n"); 584276Sgblack@eecs.umich.edu return NoFault; 594276Sgblack@eecs.umich.edu } 604276Sgblack@eecs.umich.edu}}; 614276Sgblack@eecs.umich.edu 624276Sgblack@eecs.umich.edudef template PanicCompleteAcc {{ 634276Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 644276Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 654276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 664276Sgblack@eecs.umich.edu { 674276Sgblack@eecs.umich.edu panic("CompleteAcc function executed when it shouldn't be!\n"); 684276Sgblack@eecs.umich.edu return NoFault; 694276Sgblack@eecs.umich.edu } 704276Sgblack@eecs.umich.edu}}; 714276Sgblack@eecs.umich.edu 724276Sgblack@eecs.umich.edu 734276Sgblack@eecs.umich.edudef template SwapExecute {{ 744276Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 754276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 764276Sgblack@eecs.umich.edu { 774276Sgblack@eecs.umich.edu Addr EA; 784276Sgblack@eecs.umich.edu Fault fault = NoFault; 794276Sgblack@eecs.umich.edu 804276Sgblack@eecs.umich.edu %(op_decl)s; 814276Sgblack@eecs.umich.edu uint64_t memData = 0; 824276Sgblack@eecs.umich.edu %(op_rd)s; 834276Sgblack@eecs.umich.edu %(ea_code)s; 844276Sgblack@eecs.umich.edu 854276Sgblack@eecs.umich.edu if (%(predicate_test)s) 864276Sgblack@eecs.umich.edu { 874276Sgblack@eecs.umich.edu %(preacc_code)s; 884276Sgblack@eecs.umich.edu 894711Sgblack@eecs.umich.edu if (fault == NoFault) { 904276Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 914276Sgblack@eecs.umich.edu &memData); 925238Sgblack@eecs.umich.edu } 935238Sgblack@eecs.umich.edu 945238Sgblack@eecs.umich.edu if (fault == NoFault) { 955238Sgblack@eecs.umich.edu %(postacc_code)s; 965937Sgblack@eecs.umich.edu } 975902Sgblack@eecs.umich.edu 985238Sgblack@eecs.umich.edu if (fault == NoFault) { 995238Sgblack@eecs.umich.edu %(op_wb)s; 1005238Sgblack@eecs.umich.edu } 1015238Sgblack@eecs.umich.edu } else { 1025238Sgblack@eecs.umich.edu xc->setPredicate(false); 1035238Sgblack@eecs.umich.edu } 1045238Sgblack@eecs.umich.edu 1055238Sgblack@eecs.umich.edu return fault; 1065238Sgblack@eecs.umich.edu } 1075238Sgblack@eecs.umich.edu}}; 1085238Sgblack@eecs.umich.edu 1095238Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 1105238Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1115238Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1125238Sgblack@eecs.umich.edu { 1135238Sgblack@eecs.umich.edu Addr EA; 1145238Sgblack@eecs.umich.edu Fault fault = NoFault; 1155238Sgblack@eecs.umich.edu 1165238Sgblack@eecs.umich.edu %(op_decl)s; 1175238Sgblack@eecs.umich.edu uint64_t memData = 0; 1185238Sgblack@eecs.umich.edu %(op_rd)s; 1195238Sgblack@eecs.umich.edu %(ea_code)s; 1205238Sgblack@eecs.umich.edu 1215238Sgblack@eecs.umich.edu if (%(predicate_test)s) 1225238Sgblack@eecs.umich.edu { 1235238Sgblack@eecs.umich.edu %(preacc_code)s; 1245238Sgblack@eecs.umich.edu 1255238Sgblack@eecs.umich.edu if (fault == NoFault) { 1265238Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1275238Sgblack@eecs.umich.edu &memData); 1285238Sgblack@eecs.umich.edu } 1296054Sgblack@eecs.umich.edu } else { 1305238Sgblack@eecs.umich.edu xc->setPredicate(false); 1315683Sgblack@eecs.umich.edu } 1325238Sgblack@eecs.umich.edu 1335238Sgblack@eecs.umich.edu return fault; 1345238Sgblack@eecs.umich.edu } 1355238Sgblack@eecs.umich.edu}}; 1365238Sgblack@eecs.umich.edu 1375238Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1385238Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1395238Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1405291Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1415291Sgblack@eecs.umich.edu { 1425291Sgblack@eecs.umich.edu Fault fault = NoFault; 1435291Sgblack@eecs.umich.edu 1445291Sgblack@eecs.umich.edu %(op_decl)s; 1455291Sgblack@eecs.umich.edu %(op_rd)s; 1465291Sgblack@eecs.umich.edu 1475291Sgblack@eecs.umich.edu if (%(predicate_test)s) 1485291Sgblack@eecs.umich.edu { 1495292Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1505292Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1515292Sgblack@eecs.umich.edu uint64_t memData = Mem; 1525292Sgblack@eecs.umich.edu 1535292Sgblack@eecs.umich.edu %(postacc_code)s; 1545292Sgblack@eecs.umich.edu 1555292Sgblack@eecs.umich.edu if (fault == NoFault) { 1565292Sgblack@eecs.umich.edu %(op_wb)s; 1575292Sgblack@eecs.umich.edu } 1585238Sgblack@eecs.umich.edu } 1596054Sgblack@eecs.umich.edu 1605359Sgblack@eecs.umich.edu return fault; 1615238Sgblack@eecs.umich.edu } 1625238Sgblack@eecs.umich.edu}}; 1635238Sgblack@eecs.umich.edu 1644276Sgblack@eecs.umich.edudef template LoadExecute {{ 1654276Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1665789Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1675789Sgblack@eecs.umich.edu { 1685789Sgblack@eecs.umich.edu Addr EA; 1695789Sgblack@eecs.umich.edu Fault fault = NoFault; 1705789Sgblack@eecs.umich.edu 1715789Sgblack@eecs.umich.edu %(op_decl)s; 1725789Sgblack@eecs.umich.edu %(op_rd)s; 1735789Sgblack@eecs.umich.edu %(ea_code)s; 1745789Sgblack@eecs.umich.edu 1755789Sgblack@eecs.umich.edu if (%(predicate_test)s) 1765789Sgblack@eecs.umich.edu { 1775789Sgblack@eecs.umich.edu if (fault == NoFault) { 1785789Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1795789Sgblack@eecs.umich.edu %(memacc_code)s; 1805789Sgblack@eecs.umich.edu } 1815789Sgblack@eecs.umich.edu 1825789Sgblack@eecs.umich.edu if (fault == NoFault) { 1835789Sgblack@eecs.umich.edu %(op_wb)s; 1845789Sgblack@eecs.umich.edu } 1855789Sgblack@eecs.umich.edu } else { 1865789Sgblack@eecs.umich.edu xc->setPredicate(false); 1875789Sgblack@eecs.umich.edu } 1885789Sgblack@eecs.umich.edu 1895789Sgblack@eecs.umich.edu return fault; 1905789Sgblack@eecs.umich.edu } 1915789Sgblack@eecs.umich.edu}}; 1925789Sgblack@eecs.umich.edu 1935789Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1945789Sgblack@eecs.umich.edu template <class Element> 1955789Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 1965789Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1975789Sgblack@eecs.umich.edu { 1985789Sgblack@eecs.umich.edu Addr EA; 1995789Sgblack@eecs.umich.edu Fault fault = NoFault; 2005789Sgblack@eecs.umich.edu 2015789Sgblack@eecs.umich.edu %(op_decl)s; 2025789Sgblack@eecs.umich.edu %(mem_decl)s; 2035789Sgblack@eecs.umich.edu %(op_rd)s; 2045789Sgblack@eecs.umich.edu %(ea_code)s; 2055789Sgblack@eecs.umich.edu 2065789Sgblack@eecs.umich.edu MemUnion memUnion; 2075789Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2085789Sgblack@eecs.umich.edu 2095789Sgblack@eecs.umich.edu if (%(predicate_test)s) 2105789Sgblack@eecs.umich.edu { 2115789Sgblack@eecs.umich.edu if (fault == NoFault) { 2125789Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 2135789Sgblack@eecs.umich.edu %(memacc_code)s; 2145789Sgblack@eecs.umich.edu } 2155789Sgblack@eecs.umich.edu 2165789Sgblack@eecs.umich.edu if (fault == NoFault) { 2175789Sgblack@eecs.umich.edu %(op_wb)s; 2185789Sgblack@eecs.umich.edu } 2195789Sgblack@eecs.umich.edu } else { 2205789Sgblack@eecs.umich.edu xc->setPredicate(false); 2215789Sgblack@eecs.umich.edu } 2225789Sgblack@eecs.umich.edu 2235789Sgblack@eecs.umich.edu return fault; 2245789Sgblack@eecs.umich.edu } 2255789Sgblack@eecs.umich.edu}}; 2265789Sgblack@eecs.umich.edu 2275789Sgblack@eecs.umich.edudef template StoreExecute {{ 2285789Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2295789Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2305789Sgblack@eecs.umich.edu { 2315789Sgblack@eecs.umich.edu Addr EA; 2325789Sgblack@eecs.umich.edu Fault fault = NoFault; 2335789Sgblack@eecs.umich.edu 2345789Sgblack@eecs.umich.edu %(op_decl)s; 2355789Sgblack@eecs.umich.edu %(op_rd)s; 2365789Sgblack@eecs.umich.edu %(ea_code)s; 2375789Sgblack@eecs.umich.edu 2385789Sgblack@eecs.umich.edu if (%(predicate_test)s) 2395789Sgblack@eecs.umich.edu { 2405789Sgblack@eecs.umich.edu if (fault == NoFault) { 2415789Sgblack@eecs.umich.edu %(memacc_code)s; 2425789Sgblack@eecs.umich.edu } 2435789Sgblack@eecs.umich.edu 2445789Sgblack@eecs.umich.edu if (fault == NoFault) { 2455789Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2465789Sgblack@eecs.umich.edu memAccessFlags, NULL); 2475789Sgblack@eecs.umich.edu } 2485789Sgblack@eecs.umich.edu 2495789Sgblack@eecs.umich.edu if (fault == NoFault) { 2505789Sgblack@eecs.umich.edu %(op_wb)s; 2515789Sgblack@eecs.umich.edu } 2525789Sgblack@eecs.umich.edu } else { 2535789Sgblack@eecs.umich.edu xc->setPredicate(false); 2545789Sgblack@eecs.umich.edu } 2555789Sgblack@eecs.umich.edu 2564712Sgblack@eecs.umich.edu return fault; 2575907Sgblack@eecs.umich.edu } 2585907Sgblack@eecs.umich.edu}}; 2595907Sgblack@eecs.umich.edu 2605907Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2615907Sgblack@eecs.umich.edu template <class Element> 2625907Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2635907Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2644712Sgblack@eecs.umich.edu { 2655659Sgblack@eecs.umich.edu Addr EA; 2664712Sgblack@eecs.umich.edu Fault fault = NoFault; 2675933Sgblack@eecs.umich.edu 2685908Sgblack@eecs.umich.edu %(op_decl)s; 2695908Sgblack@eecs.umich.edu %(mem_decl)s; 2705908Sgblack@eecs.umich.edu %(op_rd)s; 2715908Sgblack@eecs.umich.edu %(ea_code)s; 2725908Sgblack@eecs.umich.edu 2735908Sgblack@eecs.umich.edu MemUnion memUnion; 2745908Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2755908Sgblack@eecs.umich.edu 2765908Sgblack@eecs.umich.edu if (%(predicate_test)s) 2774276Sgblack@eecs.umich.edu { 2784276Sgblack@eecs.umich.edu if (fault == NoFault) { 2794712Sgblack@eecs.umich.edu %(memacc_code)s; 2804712Sgblack@eecs.umich.edu } 2814730Sgblack@eecs.umich.edu 2824760Sgblack@eecs.umich.edu if (fault == NoFault) { 2834730Sgblack@eecs.umich.edu fault = xc->writeMem(dataPtr, %(size)d, EA, 2845920Sgblack@eecs.umich.edu memAccessFlags, NULL); 2855422Sgblack@eecs.umich.edu } 2865422Sgblack@eecs.umich.edu 2874276Sgblack@eecs.umich.edu if (fault == NoFault) { 2884760Sgblack@eecs.umich.edu %(op_wb)s; 2894760Sgblack@eecs.umich.edu } 2904760Sgblack@eecs.umich.edu } else { 2915020Sgblack@eecs.umich.edu xc->setPredicate(false); 2925020Sgblack@eecs.umich.edu } 2935020Sgblack@eecs.umich.edu 2945020Sgblack@eecs.umich.edu return fault; 2955020Sgblack@eecs.umich.edu } 2965020Sgblack@eecs.umich.edu}}; 2975020Sgblack@eecs.umich.edu 2985020Sgblack@eecs.umich.edudef template StoreExExecute {{ 2995020Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3005020Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3015020Sgblack@eecs.umich.edu { 3025020Sgblack@eecs.umich.edu Addr EA; 3035020Sgblack@eecs.umich.edu Fault fault = NoFault; 3045020Sgblack@eecs.umich.edu 3054760Sgblack@eecs.umich.edu %(op_decl)s; 3064760Sgblack@eecs.umich.edu %(op_rd)s; 3074760Sgblack@eecs.umich.edu %(ea_code)s; 3085020Sgblack@eecs.umich.edu 3095020Sgblack@eecs.umich.edu if (%(predicate_test)s) 3105020Sgblack@eecs.umich.edu { 3115020Sgblack@eecs.umich.edu if (fault == NoFault) { 3125020Sgblack@eecs.umich.edu %(memacc_code)s; 3134760Sgblack@eecs.umich.edu } 3144760Sgblack@eecs.umich.edu 3154760Sgblack@eecs.umich.edu uint64_t writeResult; 3165020Sgblack@eecs.umich.edu 3175020Sgblack@eecs.umich.edu if (fault == NoFault) { 3185029Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3195029Sgblack@eecs.umich.edu &writeResult); 3205020Sgblack@eecs.umich.edu } 3215020Sgblack@eecs.umich.edu 3225020Sgblack@eecs.umich.edu if (fault == NoFault) { 3235020Sgblack@eecs.umich.edu %(postacc_code)s; 3244760Sgblack@eecs.umich.edu } 3254760Sgblack@eecs.umich.edu 3264760Sgblack@eecs.umich.edu if (fault == NoFault) { 3275030Sgblack@eecs.umich.edu %(op_wb)s; 3285030Sgblack@eecs.umich.edu } 3295020Sgblack@eecs.umich.edu } else { 3305020Sgblack@eecs.umich.edu xc->setPredicate(false); 3314760Sgblack@eecs.umich.edu } 3324760Sgblack@eecs.umich.edu 3334276Sgblack@eecs.umich.edu return fault; 3344276Sgblack@eecs.umich.edu } 3355331Sgblack@eecs.umich.edu}}; 3365331Sgblack@eecs.umich.edu 3375331Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3385920Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3395331Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3405331Sgblack@eecs.umich.edu { 3415331Sgblack@eecs.umich.edu Addr EA; 3425331Sgblack@eecs.umich.edu Fault fault = NoFault; 3435331Sgblack@eecs.umich.edu 3445331Sgblack@eecs.umich.edu %(op_decl)s; 3455331Sgblack@eecs.umich.edu %(op_rd)s; 3465331Sgblack@eecs.umich.edu %(ea_code)s; 3475331Sgblack@eecs.umich.edu 3485331Sgblack@eecs.umich.edu if (%(predicate_test)s) 3495331Sgblack@eecs.umich.edu { 3504276Sgblack@eecs.umich.edu if (fault == NoFault) { 3515020Sgblack@eecs.umich.edu %(memacc_code)s; 3525020Sgblack@eecs.umich.edu } 3535020Sgblack@eecs.umich.edu 3545296Sgblack@eecs.umich.edu if (fault == NoFault) { 3555931Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3565241Sgblack@eecs.umich.edu NULL); 3575931Sgblack@eecs.umich.edu } 3585020Sgblack@eecs.umich.edu } else { 3595020Sgblack@eecs.umich.edu xc->setPredicate(false); 3605020Sgblack@eecs.umich.edu } 3615020Sgblack@eecs.umich.edu 3625020Sgblack@eecs.umich.edu return fault; 3635020Sgblack@eecs.umich.edu } 3645020Sgblack@eecs.umich.edu}}; 3655020Sgblack@eecs.umich.edu 3665020Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3675020Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3684276Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3695020Sgblack@eecs.umich.edu { 3705020Sgblack@eecs.umich.edu Addr EA; 3715020Sgblack@eecs.umich.edu Fault fault = NoFault; 3725031Sgblack@eecs.umich.edu 3735031Sgblack@eecs.umich.edu %(op_decl)s; 3745031Sgblack@eecs.umich.edu %(op_rd)s; 3755031Sgblack@eecs.umich.edu %(ea_code)s; 3765020Sgblack@eecs.umich.edu 3775020Sgblack@eecs.umich.edu if (%(predicate_test)s) 3785020Sgblack@eecs.umich.edu { 3795020Sgblack@eecs.umich.edu if (fault == NoFault) { 3805020Sgblack@eecs.umich.edu %(memacc_code)s; 3815020Sgblack@eecs.umich.edu } 3825020Sgblack@eecs.umich.edu 3835020Sgblack@eecs.umich.edu if (fault == NoFault) { 3845020Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3855020Sgblack@eecs.umich.edu NULL); 3865020Sgblack@eecs.umich.edu } 3875020Sgblack@eecs.umich.edu } else { 3885020Sgblack@eecs.umich.edu xc->setPredicate(false); 3895020Sgblack@eecs.umich.edu } 3905020Sgblack@eecs.umich.edu 3915020Sgblack@eecs.umich.edu return fault; 3925020Sgblack@eecs.umich.edu } 3935020Sgblack@eecs.umich.edu}}; 3945020Sgblack@eecs.umich.edu 3955020Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3965020Sgblack@eecs.umich.edu template <class Element> 3975020Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 3985020Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 3995020Sgblack@eecs.umich.edu { 4005020Sgblack@eecs.umich.edu Addr EA; 4015020Sgblack@eecs.umich.edu Fault fault = NoFault; 4025020Sgblack@eecs.umich.edu 4035020Sgblack@eecs.umich.edu %(op_decl)s; 4045058Sgblack@eecs.umich.edu %(mem_decl)s; 4055020Sgblack@eecs.umich.edu %(op_rd)s; 4065020Sgblack@eecs.umich.edu %(ea_code)s; 4075020Sgblack@eecs.umich.edu 4085020Sgblack@eecs.umich.edu if (%(predicate_test)s) 4095046Sgblack@eecs.umich.edu { 4105046Sgblack@eecs.umich.edu MemUnion memUnion; 4115046Sgblack@eecs.umich.edu if (fault == NoFault) { 4125046Sgblack@eecs.umich.edu %(memacc_code)s; 4135020Sgblack@eecs.umich.edu } 4145020Sgblack@eecs.umich.edu 4155020Sgblack@eecs.umich.edu if (fault == NoFault) { 4165020Sgblack@eecs.umich.edu fault = xc->writeMem(memUnion.bytes, %(size)d, EA, 4174276Sgblack@eecs.umich.edu memAccessFlags, NULL); 4184276Sgblack@eecs.umich.edu } 4195149Sgblack@eecs.umich.edu } else { 4205409Sgblack@eecs.umich.edu xc->setPredicate(false); 4215149Sgblack@eecs.umich.edu } 4224712Sgblack@eecs.umich.edu 4235972Sgblack@eecs.umich.edu return fault; 4244712Sgblack@eecs.umich.edu } 4255972Sgblack@eecs.umich.edu}}; 4265972Sgblack@eecs.umich.edu 4275972Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4284712Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4294730Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4304712Sgblack@eecs.umich.edu { 4314276Sgblack@eecs.umich.edu Addr EA; 4324276Sgblack@eecs.umich.edu Fault fault = NoFault; 4334712Sgblack@eecs.umich.edu 4344712Sgblack@eecs.umich.edu %(op_src_decl)s; 4354712Sgblack@eecs.umich.edu %(op_rd)s; 4364712Sgblack@eecs.umich.edu %(ea_code)s; 4374712Sgblack@eecs.umich.edu 4384712Sgblack@eecs.umich.edu if (%(predicate_test)s) 4394712Sgblack@eecs.umich.edu { 4404712Sgblack@eecs.umich.edu if (fault == NoFault) { 4414276Sgblack@eecs.umich.edu fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 4424760Sgblack@eecs.umich.edu } 4434760Sgblack@eecs.umich.edu } else { 4444760Sgblack@eecs.umich.edu xc->setPredicate(false); 4454760Sgblack@eecs.umich.edu } 4464760Sgblack@eecs.umich.edu 4474760Sgblack@eecs.umich.edu return fault; 4484760Sgblack@eecs.umich.edu } 4494760Sgblack@eecs.umich.edu}}; 4504760Sgblack@eecs.umich.edu 4514760Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4524760Sgblack@eecs.umich.edu template <class Element> 4534760Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4544760Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4554760Sgblack@eecs.umich.edu { 4564760Sgblack@eecs.umich.edu Addr EA; 4574760Sgblack@eecs.umich.edu Fault fault = NoFault; 4584760Sgblack@eecs.umich.edu 4594760Sgblack@eecs.umich.edu %(op_decl)s; 4604760Sgblack@eecs.umich.edu %(mem_decl)s; 4614760Sgblack@eecs.umich.edu %(op_rd)s; 4624760Sgblack@eecs.umich.edu %(ea_code)s; 4634276Sgblack@eecs.umich.edu 4645020Sgblack@eecs.umich.edu MemUnion memUnion; 4655020Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 4665020Sgblack@eecs.umich.edu 4675020Sgblack@eecs.umich.edu if (%(predicate_test)s) 4685020Sgblack@eecs.umich.edu { 4695020Sgblack@eecs.umich.edu if (fault == NoFault) { 4705020Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 4715020Sgblack@eecs.umich.edu } 4725020Sgblack@eecs.umich.edu } else { 4735020Sgblack@eecs.umich.edu xc->setPredicate(false); 4745020Sgblack@eecs.umich.edu } 4755020Sgblack@eecs.umich.edu 4765020Sgblack@eecs.umich.edu return fault; 4775020Sgblack@eecs.umich.edu } 4785020Sgblack@eecs.umich.edu}}; 4795020Sgblack@eecs.umich.edu 4805020Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 4815020Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4825020Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4835020Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4845020Sgblack@eecs.umich.edu { 4855020Sgblack@eecs.umich.edu Fault fault = NoFault; 4865020Sgblack@eecs.umich.edu 4875020Sgblack@eecs.umich.edu %(op_decl)s; 4885020Sgblack@eecs.umich.edu %(op_rd)s; 4895020Sgblack@eecs.umich.edu 4905052Sgblack@eecs.umich.edu if (%(predicate_test)s) 4915052Sgblack@eecs.umich.edu { 4925052Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4935020Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 4945020Sgblack@eecs.umich.edu 4955059Sgblack@eecs.umich.edu if (fault == NoFault) { 4965059Sgblack@eecs.umich.edu %(memacc_code)s; 4975059Sgblack@eecs.umich.edu } 4985059Sgblack@eecs.umich.edu 4995059Sgblack@eecs.umich.edu if (fault == NoFault) { 5005059Sgblack@eecs.umich.edu %(op_wb)s; 5015059Sgblack@eecs.umich.edu } 5025020Sgblack@eecs.umich.edu } 5034276Sgblack@eecs.umich.edu 5045020Sgblack@eecs.umich.edu return fault; 5055020Sgblack@eecs.umich.edu } 5065020Sgblack@eecs.umich.edu}}; 5075020Sgblack@eecs.umich.edu 5085020Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5095020Sgblack@eecs.umich.edu template <class Element> 5105020Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5115020Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5125020Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5135020Sgblack@eecs.umich.edu { 5145020Sgblack@eecs.umich.edu Fault fault = NoFault; 5155020Sgblack@eecs.umich.edu 5165020Sgblack@eecs.umich.edu %(mem_decl)s; 5175020Sgblack@eecs.umich.edu %(op_decl)s; 5185020Sgblack@eecs.umich.edu %(op_rd)s; 5195020Sgblack@eecs.umich.edu 5205020Sgblack@eecs.umich.edu if (%(predicate_test)s) 5215020Sgblack@eecs.umich.edu { 5225020Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5235020Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5245020Sgblack@eecs.umich.edu 5255020Sgblack@eecs.umich.edu if (fault == NoFault) { 5265020Sgblack@eecs.umich.edu %(memacc_code)s; 5275020Sgblack@eecs.umich.edu } 5285020Sgblack@eecs.umich.edu 5295020Sgblack@eecs.umich.edu if (fault == NoFault) { 5305020Sgblack@eecs.umich.edu %(op_wb)s; 5315020Sgblack@eecs.umich.edu } 5325020Sgblack@eecs.umich.edu } 5335020Sgblack@eecs.umich.edu 5345020Sgblack@eecs.umich.edu return fault; 5355020Sgblack@eecs.umich.edu } 5365020Sgblack@eecs.umich.edu}}; 5375020Sgblack@eecs.umich.edu 5385020Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5395020Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5405047Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5415047Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5425020Sgblack@eecs.umich.edu { 5435047Sgblack@eecs.umich.edu return NoFault; 5445020Sgblack@eecs.umich.edu } 5455047Sgblack@eecs.umich.edu}}; 5465020Sgblack@eecs.umich.edu 5475020Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5485020Sgblack@eecs.umich.edu template <class Element> 5495020Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5504276Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5515020Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5525020Sgblack@eecs.umich.edu { 5535020Sgblack@eecs.umich.edu return NoFault; 5545020Sgblack@eecs.umich.edu } 5555020Sgblack@eecs.umich.edu}}; 5565020Sgblack@eecs.umich.edu 5575020Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 5585020Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5595020Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5605020Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5615020Sgblack@eecs.umich.edu { 5625020Sgblack@eecs.umich.edu Fault fault = NoFault; 5635020Sgblack@eecs.umich.edu 5645020Sgblack@eecs.umich.edu %(op_decl)s; 5655020Sgblack@eecs.umich.edu %(op_rd)s; 5665020Sgblack@eecs.umich.edu 5675020Sgblack@eecs.umich.edu if (%(predicate_test)s) 5685020Sgblack@eecs.umich.edu { 5695020Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5705020Sgblack@eecs.umich.edu %(postacc_code)s; 5715020Sgblack@eecs.umich.edu 5725020Sgblack@eecs.umich.edu if (fault == NoFault) { 5735020Sgblack@eecs.umich.edu %(op_wb)s; 5745020Sgblack@eecs.umich.edu } 5754276Sgblack@eecs.umich.edu } 5765020Sgblack@eecs.umich.edu 5775020Sgblack@eecs.umich.edu return fault; 5785020Sgblack@eecs.umich.edu } 5795020Sgblack@eecs.umich.edu}}; 5805020Sgblack@eecs.umich.edu 5815020Sgblack@eecs.umich.edudef template RfeDeclare {{ 5825020Sgblack@eecs.umich.edu /** 5835020Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5845020Sgblack@eecs.umich.edu */ 5855020Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5865020Sgblack@eecs.umich.edu { 5875020Sgblack@eecs.umich.edu public: 5885020Sgblack@eecs.umich.edu 5895020Sgblack@eecs.umich.edu /// Constructor. 5905020Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5915020Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5925020Sgblack@eecs.umich.edu 5935020Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5945020Sgblack@eecs.umich.edu 5955020Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5965020Sgblack@eecs.umich.edu 5975020Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5985020Sgblack@eecs.umich.edu }; 5995020Sgblack@eecs.umich.edu}}; 6005020Sgblack@eecs.umich.edu 6015020Sgblack@eecs.umich.edudef template SrsDeclare {{ 6025020Sgblack@eecs.umich.edu /** 6035020Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6044276Sgblack@eecs.umich.edu */ 6055020Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6065020Sgblack@eecs.umich.edu { 6075020Sgblack@eecs.umich.edu public: 6085020Sgblack@eecs.umich.edu 6095238Sgblack@eecs.umich.edu /// Constructor. 6105238Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6115238Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6125238Sgblack@eecs.umich.edu 6135238Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6145238Sgblack@eecs.umich.edu 6155238Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6165238Sgblack@eecs.umich.edu 6175238Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6185238Sgblack@eecs.umich.edu }; 6195238Sgblack@eecs.umich.edu}}; 6205238Sgblack@eecs.umich.edu 6215238Sgblack@eecs.umich.edudef template SwapDeclare {{ 6225238Sgblack@eecs.umich.edu /** 6235238Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6245238Sgblack@eecs.umich.edu */ 6255238Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6265238Sgblack@eecs.umich.edu { 6275238Sgblack@eecs.umich.edu public: 6285238Sgblack@eecs.umich.edu 6295238Sgblack@eecs.umich.edu /// Constructor. 6305238Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6315238Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6325238Sgblack@eecs.umich.edu 6335238Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6345238Sgblack@eecs.umich.edu 6355238Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6365238Sgblack@eecs.umich.edu 6375238Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6385238Sgblack@eecs.umich.edu }; 6395238Sgblack@eecs.umich.edu}}; 6405238Sgblack@eecs.umich.edu 6415238Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6425238Sgblack@eecs.umich.edu /** 6435238Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6445238Sgblack@eecs.umich.edu */ 6455238Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6465238Sgblack@eecs.umich.edu { 6475238Sgblack@eecs.umich.edu public: 6485238Sgblack@eecs.umich.edu 6495238Sgblack@eecs.umich.edu /// Constructor. 6505238Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6515238Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6525238Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6535238Sgblack@eecs.umich.edu 6545238Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6555238Sgblack@eecs.umich.edu 6565238Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6575238Sgblack@eecs.umich.edu 6585238Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6595238Sgblack@eecs.umich.edu }; 6605238Sgblack@eecs.umich.edu}}; 6615020Sgblack@eecs.umich.edu 6625020Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6635020Sgblack@eecs.umich.edu /** 6645020Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6655020Sgblack@eecs.umich.edu */ 6665020Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6675020Sgblack@eecs.umich.edu { 6685020Sgblack@eecs.umich.edu public: 6695020Sgblack@eecs.umich.edu 6705020Sgblack@eecs.umich.edu /// Constructor. 6715020Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6725020Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6735020Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6745238Sgblack@eecs.umich.edu 6755238Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6765238Sgblack@eecs.umich.edu 6775238Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6785238Sgblack@eecs.umich.edu 6795238Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6805238Sgblack@eecs.umich.edu }; 6815238Sgblack@eecs.umich.edu}}; 6825238Sgblack@eecs.umich.edu 6835238Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6845238Sgblack@eecs.umich.edu /** 6855238Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6865238Sgblack@eecs.umich.edu */ 6875238Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6885238Sgblack@eecs.umich.edu { 6895238Sgblack@eecs.umich.edu public: 6905238Sgblack@eecs.umich.edu 6915238Sgblack@eecs.umich.edu /// Constructor. 6925238Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6935238Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6945238Sgblack@eecs.umich.edu 6955238Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6965238Sgblack@eecs.umich.edu 6975238Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6985238Sgblack@eecs.umich.edu 6995238Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7005238Sgblack@eecs.umich.edu }; 7015238Sgblack@eecs.umich.edu}}; 7025238Sgblack@eecs.umich.edu 7035238Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7045238Sgblack@eecs.umich.edu /** 7055238Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7065238Sgblack@eecs.umich.edu */ 7075238Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7085238Sgblack@eecs.umich.edu { 7095238Sgblack@eecs.umich.edu public: 7105238Sgblack@eecs.umich.edu 7115238Sgblack@eecs.umich.edu /// Constructor. 7125238Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7135238Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7145238Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7155238Sgblack@eecs.umich.edu 7165238Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7175238Sgblack@eecs.umich.edu 7185238Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7195238Sgblack@eecs.umich.edu 7205238Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7215238Sgblack@eecs.umich.edu }; 7225238Sgblack@eecs.umich.edu}}; 7235238Sgblack@eecs.umich.edu 7245238Sgblack@eecs.umich.edudef template StoreDRegDeclare {{ 7255238Sgblack@eecs.umich.edu /** 7265020Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7275020Sgblack@eecs.umich.edu */ 7285020Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7295020Sgblack@eecs.umich.edu { 7305020Sgblack@eecs.umich.edu public: 7315020Sgblack@eecs.umich.edu 7325020Sgblack@eecs.umich.edu /// Constructor. 7335020Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7345020Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7355020Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7365020Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7374276Sgblack@eecs.umich.edu uint32_t _index); 7385020Sgblack@eecs.umich.edu 7395020Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7405020Sgblack@eecs.umich.edu 7415020Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7425020Sgblack@eecs.umich.edu 7435020Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7445020Sgblack@eecs.umich.edu }; 7455020Sgblack@eecs.umich.edu}}; 7465020Sgblack@eecs.umich.edu 7475020Sgblack@eecs.umich.edudef template StoreRegDeclare {{ 7485020Sgblack@eecs.umich.edu /** 7495020Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7505020Sgblack@eecs.umich.edu */ 7515020Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7525020Sgblack@eecs.umich.edu { 7535020Sgblack@eecs.umich.edu public: 7545020Sgblack@eecs.umich.edu 7555020Sgblack@eecs.umich.edu /// Constructor. 7565020Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7575020Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7585020Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7595020Sgblack@eecs.umich.edu uint32_t _index); 7605020Sgblack@eecs.umich.edu 7615020Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7625020Sgblack@eecs.umich.edu 7635020Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7645020Sgblack@eecs.umich.edu 7655020Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7665020Sgblack@eecs.umich.edu }; 7675020Sgblack@eecs.umich.edu}}; 7684276Sgblack@eecs.umich.edu 7694727Sgblack@eecs.umich.edudef template LoadDRegDeclare {{ 7704727Sgblack@eecs.umich.edu /** 7714727Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7724727Sgblack@eecs.umich.edu */ 7734727Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7744727Sgblack@eecs.umich.edu { 7754727Sgblack@eecs.umich.edu public: 7764727Sgblack@eecs.umich.edu 7774727Sgblack@eecs.umich.edu /// Constructor. 7784727Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7794727Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7804727Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7814727Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7824727Sgblack@eecs.umich.edu uint32_t _index); 7834727Sgblack@eecs.umich.edu 7844727Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7854727Sgblack@eecs.umich.edu 7864727Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7874727Sgblack@eecs.umich.edu 7884727Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7894727Sgblack@eecs.umich.edu }; 7904760Sgblack@eecs.umich.edu}}; 7914760Sgblack@eecs.umich.edu 7924760Sgblack@eecs.umich.edudef template LoadRegDeclare {{ 7934760Sgblack@eecs.umich.edu /** 7944760Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7954760Sgblack@eecs.umich.edu */ 7964760Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7974760Sgblack@eecs.umich.edu { 7984760Sgblack@eecs.umich.edu public: 7994760Sgblack@eecs.umich.edu 8004760Sgblack@eecs.umich.edu /// Constructor. 8014760Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8024760Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 8034760Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8044760Sgblack@eecs.umich.edu uint32_t _index); 8054760Sgblack@eecs.umich.edu 8064760Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8074760Sgblack@eecs.umich.edu 8084760Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8094760Sgblack@eecs.umich.edu 8104276Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8114276Sgblack@eecs.umich.edu }; 8124712Sgblack@eecs.umich.edu}}; 8134712Sgblack@eecs.umich.edu 8145659Sgblack@eecs.umich.edudef template LoadImmDeclare {{ 8155659Sgblack@eecs.umich.edu /** 8166052Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8175659Sgblack@eecs.umich.edu */ 8185659Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8195659Sgblack@eecs.umich.edu { 8205659Sgblack@eecs.umich.edu public: 8215659Sgblack@eecs.umich.edu 8225240Sgblack@eecs.umich.edu /// Constructor. 8234712Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8244712Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8254712Sgblack@eecs.umich.edu 8264712Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8274276Sgblack@eecs.umich.edu 8284276Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8294712Sgblack@eecs.umich.edu 8304712Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8314712Sgblack@eecs.umich.edu }; 8325240Sgblack@eecs.umich.edu}}; 8335977Sgblack@eecs.umich.edu 8344712Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 8355238Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8365967Sgblack@eecs.umich.edu}}; 8375967Sgblack@eecs.umich.edu 8385967Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 8395967Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 8405967Sgblack@eecs.umich.edu}}; 8415967Sgblack@eecs.umich.edu 8425967Sgblack@eecs.umich.edudef template RfeConstructor {{ 8435967Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8445923Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 8455238Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8465238Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 8475967Sgblack@eecs.umich.edu { 8485967Sgblack@eecs.umich.edu %(constructor)s; 8495967Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 8505967Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 8515967Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8525967Sgblack@eecs.umich.edu } 8535967Sgblack@eecs.umich.edu } 8545967Sgblack@eecs.umich.edu#if %(use_uops)d 8555238Sgblack@eecs.umich.edu uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8565238Sgblack@eecs.umich.edu int uopIdx = 0; 8575238Sgblack@eecs.umich.edu uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8584724Sgblack@eecs.umich.edu uops[uopIdx]->setDelayedCommit(); 8594276Sgblack@eecs.umich.edu#if %(use_wb)d 8604276Sgblack@eecs.umich.edu uops[++uopIdx] = new %(wb_decl)s; 8614864Sgblack@eecs.umich.edu uops[uopIdx]->setDelayedCommit(); 8624864Sgblack@eecs.umich.edu#endif 8634712Sgblack@eecs.umich.edu#if %(use_pc)d 8645240Sgblack@eecs.umich.edu uops[++uopIdx] = new %(pc_decl)s; 8654712Sgblack@eecs.umich.edu#endif 8664712Sgblack@eecs.umich.edu uops[uopIdx]->setLastMicroop(); 8674746Sgblack@eecs.umich.edu#endif 8684746Sgblack@eecs.umich.edu } 8694746Sgblack@eecs.umich.edu}}; 8704746Sgblack@eecs.umich.edu 8714746Sgblack@eecs.umich.edudef template SrsConstructor {{ 8724276Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8734276Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8744712Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8755240Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8765240Sgblack@eecs.umich.edu { 8775240Sgblack@eecs.umich.edu %(constructor)s; 8785240Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 8795240Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 8805240Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8815240Sgblack@eecs.umich.edu } 8825240Sgblack@eecs.umich.edu } 8835240Sgblack@eecs.umich.edu#if %(use_uops)d 8845240Sgblack@eecs.umich.edu assert(numMicroops >= 2); 8855240Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 8865240Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 8875238Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 8885332Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 8895332Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 8904746Sgblack@eecs.umich.edu#endif 8914746Sgblack@eecs.umich.edu } 8924746Sgblack@eecs.umich.edu}}; 8934746Sgblack@eecs.umich.edu 8944746Sgblack@eecs.umich.edudef template SwapConstructor {{ 8954276Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8964276Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 8975815Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8985815Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 8995238Sgblack@eecs.umich.edu { 9005238Sgblack@eecs.umich.edu %(constructor)s; 9015238Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9025238Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9035238Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9045238Sgblack@eecs.umich.edu } 9055238Sgblack@eecs.umich.edu } 9065238Sgblack@eecs.umich.edu } 9075238Sgblack@eecs.umich.edu}}; 9085238Sgblack@eecs.umich.edu 9095238Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 9105238Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9115238Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9125020Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9135020Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9145020Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9155020Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9165020Sgblack@eecs.umich.edu { 9175020Sgblack@eecs.umich.edu %(constructor)s; 9185020Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9195020Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9205020Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9215020Sgblack@eecs.umich.edu } 9225020Sgblack@eecs.umich.edu } 9235020Sgblack@eecs.umich.edu#if %(use_uops)d 9245020Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9255020Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9265020Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 9275020Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9285020Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9295020Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9305020Sgblack@eecs.umich.edu#endif 9315020Sgblack@eecs.umich.edu } 9325020Sgblack@eecs.umich.edu}}; 9335020Sgblack@eecs.umich.edu 9345020Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 9355020Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9365020Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9375020Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9385020Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9395020Sgblack@eecs.umich.edu (IntRegIndex)_result, 9405020Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9414276Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9425814Sgblack@eecs.umich.edu { 9435814Sgblack@eecs.umich.edu %(constructor)s; 9445814Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9455814Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9465814Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9475020Sgblack@eecs.umich.edu } 9485020Sgblack@eecs.umich.edu } 9495020Sgblack@eecs.umich.edu#if %(use_uops)d 9505020Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9515020Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9525020Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9535020Sgblack@eecs.umich.edu _base, _add, _imm); 9545020Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9555020Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9565020Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9575020Sgblack@eecs.umich.edu#endif 9585020Sgblack@eecs.umich.edu } 9595020Sgblack@eecs.umich.edu}}; 9605020Sgblack@eecs.umich.edu 9615020Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 9625020Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9635020Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9645020Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9655020Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9665020Sgblack@eecs.umich.edu { 9675020Sgblack@eecs.umich.edu %(constructor)s; 9685020Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9695020Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9705020Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9715020Sgblack@eecs.umich.edu } 9725020Sgblack@eecs.umich.edu } 9735020Sgblack@eecs.umich.edu#if %(use_uops)d 9745020Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9755020Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9765020Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9775020Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9785020Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9795020Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9805020Sgblack@eecs.umich.edu#endif 9815020Sgblack@eecs.umich.edu } 9825020Sgblack@eecs.umich.edu}}; 9835020Sgblack@eecs.umich.edu 9844276Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 9855020Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9865020Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 9875020Sgblack@eecs.umich.edu bool _add, int32_t _imm) 9885020Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9895020Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 9905020Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9915020Sgblack@eecs.umich.edu { 9925020Sgblack@eecs.umich.edu %(constructor)s; 9935020Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9945020Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9955020Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9965020Sgblack@eecs.umich.edu } 9975020Sgblack@eecs.umich.edu } 9985020Sgblack@eecs.umich.edu#if %(use_uops)d 9995020Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10005020Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10015020Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _result, _dest, 10025020Sgblack@eecs.umich.edu _base, _add, _imm); 10035020Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10045020Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10055020Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10065020Sgblack@eecs.umich.edu#endif 10075020Sgblack@eecs.umich.edu } 10085020Sgblack@eecs.umich.edu}}; 10094276Sgblack@eecs.umich.edu 10105022Sgblack@eecs.umich.edudef template StoreDRegConstructor {{ 10115022Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10125022Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10135022Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10145022Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10155022Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10165022Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10175022Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10185022Sgblack@eecs.umich.edu (IntRegIndex)_index) 10195022Sgblack@eecs.umich.edu { 10205022Sgblack@eecs.umich.edu %(constructor)s; 10215022Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 10225022Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 10235022Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10245022Sgblack@eecs.umich.edu } 10255022Sgblack@eecs.umich.edu } 10265022Sgblack@eecs.umich.edu#if %(use_uops)d 10275022Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10285022Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10295022Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10305022Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 10315022Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10325022Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10335022Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10345022Sgblack@eecs.umich.edu#endif 10355022Sgblack@eecs.umich.edu } 10365022Sgblack@eecs.umich.edu}}; 10375022Sgblack@eecs.umich.edu 10385022Sgblack@eecs.umich.edudef template StoreRegConstructor {{ 10395022Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10405022Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10415022Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10425022Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10435022Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10444276Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10455020Sgblack@eecs.umich.edu (IntRegIndex)_index) 10465020Sgblack@eecs.umich.edu { 10475020Sgblack@eecs.umich.edu %(constructor)s; 10485020Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 10495020Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 10505020Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10515020Sgblack@eecs.umich.edu } 10525020Sgblack@eecs.umich.edu } 10535020Sgblack@eecs.umich.edu#if %(use_uops)d 10545020Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10555020Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10565020Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10575020Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 10585020Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10595020Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10605020Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10615020Sgblack@eecs.umich.edu#endif 10625020Sgblack@eecs.umich.edu } 10635020Sgblack@eecs.umich.edu}}; 10645020Sgblack@eecs.umich.edu 10655020Sgblack@eecs.umich.edudef template LoadDRegConstructor {{ 10665020Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10675020Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10685020Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10694276Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10704276Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10715022Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10725022Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10735022Sgblack@eecs.umich.edu (IntRegIndex)_index) 10745022Sgblack@eecs.umich.edu { 10755022Sgblack@eecs.umich.edu %(constructor)s; 10765022Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 10775022Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 10785022Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10795022Sgblack@eecs.umich.edu } 10805022Sgblack@eecs.umich.edu } 10815022Sgblack@eecs.umich.edu#if %(use_uops)d 10825022Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10835022Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10845022Sgblack@eecs.umich.edu if ((_dest == _index) || (_dest2 == _index)) { 10855022Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = INTREG_UREG0; 10865022Sgblack@eecs.umich.edu uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 10875022Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10885022Sgblack@eecs.umich.edu uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10895022Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 10905022Sgblack@eecs.umich.edu uops[1]->setDelayedCommit(); 10915022Sgblack@eecs.umich.edu uops[2] = new %(wb_decl)s; 10925022Sgblack@eecs.umich.edu uops[2]->setLastMicroop(); 10935022Sgblack@eecs.umich.edu } else { 10945022Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = index; 10955022Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10965022Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 10975022Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10985022Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10994276Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 11005020Sgblack@eecs.umich.edu } 11015020Sgblack@eecs.umich.edu#endif 11025020Sgblack@eecs.umich.edu } 11035020Sgblack@eecs.umich.edu}}; 11045020Sgblack@eecs.umich.edu 11055020Sgblack@eecs.umich.edudef template LoadRegConstructor {{ 11065020Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11075020Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 11085020Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11095020Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11105020Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11115020Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 11125020Sgblack@eecs.umich.edu (IntRegIndex)_index) 11135020Sgblack@eecs.umich.edu { 11145020Sgblack@eecs.umich.edu %(constructor)s; 11155020Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11165020Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 11175020Sgblack@eecs.umich.edu conditional = true; 11185020Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 11195020Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11205020Sgblack@eecs.umich.edu } 11215020Sgblack@eecs.umich.edu } 11225020Sgblack@eecs.umich.edu#if %(use_uops)d 11235020Sgblack@eecs.umich.edu assert(numMicroops >= 2); 11244276Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 11254276Sgblack@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 11264276Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = index; 11274276Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11284276Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 11294276Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 11304276Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 1131 uops[1]->setDelayedCommit(); 1132 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 1133 uops[2]->setFlag(StaticInst::IsControl); 1134 uops[2]->setFlag(StaticInst::IsIndirectControl); 1135 if (conditional) 1136 uops[2]->setFlag(StaticInst::IsCondControl); 1137 else 1138 uops[2]->setFlag(StaticInst::IsUncondControl); 1139 uops[2]->setLastMicroop(); 1140 } else if(_dest == _index) { 1141 IntRegIndex wbIndexReg = INTREG_UREG0; 1142 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 1143 uops[0]->setDelayedCommit(); 1144 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 1145 _shiftAmt, _shiftType, _index); 1146 uops[1]->setDelayedCommit(); 1147 uops[2] = new %(wb_decl)s; 1148 uops[2]->setLastMicroop(); 1149 } else { 1150 IntRegIndex wbIndexReg = index; 1151 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 1152 _shiftAmt, _shiftType, _index); 1153 uops[0]->setDelayedCommit(); 1154 uops[1] = new %(wb_decl)s; 1155 uops[1]->setLastMicroop(); 1156 1157 } 1158#else 1159 if (_dest == INTREG_PC && !isFloating()) { 1160 flags[IsControl] = true; 1161 flags[IsIndirectControl] = true; 1162 if (conditional) 1163 flags[IsCondControl] = true; 1164 else 1165 flags[IsUncondControl] = true; 1166 } 1167#endif 1168 } 1169}}; 1170 1171def template LoadImmConstructor {{ 1172 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1173 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1174 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1175 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1176 { 1177 %(constructor)s; 1178 bool conditional M5_VAR_USED = false; 1179 if (!(condCode == COND_AL || condCode == COND_UC)) { 1180 conditional = true; 1181 for (int x = 0; x < _numDestRegs; x++) { 1182 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1183 } 1184 } 1185#if %(use_uops)d 1186 assert(numMicroops >= 2); 1187 uops = new StaticInstPtr[numMicroops]; 1188 if (_dest == INTREG_PC && !isFloating()) { 1189 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1190 _imm); 1191 uops[0]->setDelayedCommit(); 1192 uops[1] = new %(wb_decl)s; 1193 uops[1]->setDelayedCommit(); 1194 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 1195 uops[2]->setFlag(StaticInst::IsControl); 1196 uops[2]->setFlag(StaticInst::IsIndirectControl); 1197 if (conditional) 1198 uops[2]->setFlag(StaticInst::IsCondControl); 1199 else 1200 uops[2]->setFlag(StaticInst::IsUncondControl); 1201 if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) 1202 uops[2]->setFlag(StaticInst::IsReturn); 1203 uops[2]->setLastMicroop(); 1204 } else { 1205 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 1206 uops[0]->setDelayedCommit(); 1207 uops[1] = new %(wb_decl)s; 1208 uops[1]->setLastMicroop(); 1209 } 1210#else 1211 if (_dest == INTREG_PC && !isFloating()) { 1212 flags[IsControl] = true; 1213 flags[IsIndirectControl] = true; 1214 if (conditional) 1215 flags[IsCondControl] = true; 1216 else 1217 flags[IsUncondControl] = true; 1218 } 1219#endif 1220 } 1221}}; 1222 1223