mem.isa revision 8207
19814Sandreas.hansson@arm.com// -*- mode:c++ -*- 22292SN/A 310333Smitch.hayenga@arm.com// Copyright (c) 2010 ARM Limited 410239Sbinhpham@cs.rutgers.edu// All rights reserved 57597Sminkyu.jeong@arm.com// 67597Sminkyu.jeong@arm.com// The license below extends only to copyright in the software and shall 77597Sminkyu.jeong@arm.com// not be construed as granting a license to any other intellectual 87597Sminkyu.jeong@arm.com// property including but not limited to intellectual property relating 97597Sminkyu.jeong@arm.com// to a hardware implementation of the functionality of the software 107597Sminkyu.jeong@arm.com// licensed hereunder. You may use the software subject to the license 117597Sminkyu.jeong@arm.com// terms below provided that you ensure that this notice is replicated 127597Sminkyu.jeong@arm.com// unmodified and in its entirety in all distributions of the software, 137597Sminkyu.jeong@arm.com// modified or unmodified, in source code or in binary form. 147597Sminkyu.jeong@arm.com// 157597Sminkyu.jeong@arm.com// Copyright (c) 2007-2008 The Florida State University 162292SN/A// All rights reserved. 172292SN/A// 182292SN/A// Redistribution and use in source and binary forms, with or without 192292SN/A// modification, are permitted provided that the following conditions are 202292SN/A// met: redistributions of source code must retain the above copyright 212292SN/A// notice, this list of conditions and the following disclaimer; 222292SN/A// redistributions in binary form must reproduce the above copyright 232292SN/A// notice, this list of conditions and the following disclaimer in the 242292SN/A// documentation and/or other materials provided with the distribution; 252292SN/A// neither the name of the copyright holders nor the names of its 262292SN/A// contributors may be used to endorse or promote products derived from 272292SN/A// this software without specific prior written permission. 282292SN/A// 292292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302292SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332292SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352292SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362292SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392292SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402292SN/A// 412689Sktlim@umich.edu// Authors: Stephen Hines 422689Sktlim@umich.edu 432689Sktlim@umich.edu 442292SN/Adef template PanicExecute {{ 452292SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 469944Smatt.horsnell@ARM.com Trace::InstRecord *traceData) const 479944Smatt.horsnell@ARM.com { 489944Smatt.horsnell@ARM.com panic("Execute function executed when it shouldn't be!\n"); 498591Sgblack@eecs.umich.edu return NoFault; 503326Sktlim@umich.edu } 518229Snate@binkert.org}}; 526658Snate@binkert.org 538887Sgeoffrey.blake@arm.comdef template PanicInitiateAcc {{ 542907Sktlim@umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 552292SN/A Trace::InstRecord *traceData) const 568232Snate@binkert.org { 578232Snate@binkert.org panic("InitiateAcc function executed when it shouldn't be!\n"); 588232Snate@binkert.org return NoFault; 599527SMatt.Horsnell@arm.com } 602722Sktlim@umich.edu}}; 612669Sktlim@umich.edu 622292SN/Adef template PanicCompleteAcc {{ 632669Sktlim@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 642678Sktlim@umich.edu %(CPU_exec_context)s *xc, 652678Sktlim@umich.edu Trace::InstRecord *traceData) const 668581Ssteve.reinhardt@amd.com { 678581Ssteve.reinhardt@amd.com panic("CompleteAcc function executed when it shouldn't be!\n"); 682292SN/A return NoFault; 692292SN/A } 702292SN/A}}; 712669Sktlim@umich.edu 722292SN/A 732678Sktlim@umich.edudef template SwapExecute {{ 742292SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 759444SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData) const 769444SAndreas.Sandberg@ARM.com { 779444SAndreas.Sandberg@ARM.com Addr EA; 784319Sktlim@umich.edu Fault fault = NoFault; 794319Sktlim@umich.edu 804319Sktlim@umich.edu %(op_decl)s; 814319Sktlim@umich.edu uint64_t memData = 0; 824319Sktlim@umich.edu %(op_rd)s; 832678Sktlim@umich.edu %(ea_code)s; 842678Sktlim@umich.edu 852292SN/A if (%(predicate_test)s) 862678Sktlim@umich.edu { 872678Sktlim@umich.edu %(preacc_code)s; 885336Shines@cs.fsu.edu 892678Sktlim@umich.edu if (fault == NoFault) { 904873Sstever@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 912678Sktlim@umich.edu EA, memAccessFlags, &memData); 922292SN/A } 932678Sktlim@umich.edu 942678Sktlim@umich.edu if (fault == NoFault) { 952678Sktlim@umich.edu %(postacc_code)s; 962678Sktlim@umich.edu } 972678Sktlim@umich.edu 982678Sktlim@umich.edu if (fault == NoFault) { 997852SMatt.Horsnell@arm.com %(op_wb)s; 1007852SMatt.Horsnell@arm.com } 1012344SN/A } else { 10210333Smitch.hayenga@arm.com xc->setPredicate(false); 10310333Smitch.hayenga@arm.com } 10410333Smitch.hayenga@arm.com 10510333Smitch.hayenga@arm.com return fault; 10610333Smitch.hayenga@arm.com } 10710333Smitch.hayenga@arm.com}}; 10810333Smitch.hayenga@arm.com 10910333Smitch.hayenga@arm.comdef template SwapInitiateAcc {{ 1102678Sktlim@umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1116974Stjones1@inf.ed.ac.uk Trace::InstRecord *traceData) const 1126974Stjones1@inf.ed.ac.uk { 1136974Stjones1@inf.ed.ac.uk Addr EA; 1146974Stjones1@inf.ed.ac.uk Fault fault = NoFault; 1156974Stjones1@inf.ed.ac.uk 1169444SAndreas.Sandberg@ARM.com %(op_decl)s; 11710327Smitch.hayenga@arm.com uint64_t memData = 0; 1182678Sktlim@umich.edu %(op_rd)s; 1196974Stjones1@inf.ed.ac.uk %(ea_code)s; 1206974Stjones1@inf.ed.ac.uk 1216974Stjones1@inf.ed.ac.uk if (%(predicate_test)s) 1226974Stjones1@inf.ed.ac.uk { 1236974Stjones1@inf.ed.ac.uk %(preacc_code)s; 1246974Stjones1@inf.ed.ac.uk 1252678Sktlim@umich.edu if (fault == NoFault) { 1262678Sktlim@umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1272678Sktlim@umich.edu memAccessFlags, &memData); 1282678Sktlim@umich.edu } 1292678Sktlim@umich.edu } else { 1302344SN/A xc->setPredicate(false); 1312307SN/A } 1326974Stjones1@inf.ed.ac.uk 1336974Stjones1@inf.ed.ac.uk return fault; 1346974Stjones1@inf.ed.ac.uk } 1356974Stjones1@inf.ed.ac.uk}}; 13610020Smatt.horsnell@ARM.com 13710020Smatt.horsnell@ARM.comdef template SwapCompleteAcc {{ 13810023Smatt.horsnell@ARM.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 13910023Smatt.horsnell@ARM.com %(CPU_exec_context)s *xc, 1402678Sktlim@umich.edu Trace::InstRecord *traceData) const 1412292SN/A { 1422292SN/A Fault fault = NoFault; 1432292SN/A 1442292SN/A %(op_decl)s; 1458545Ssaidi@eecs.umich.edu %(op_rd)s; 14610333Smitch.hayenga@arm.com 1472292SN/A if (%(predicate_test)s) 1482292SN/A { 1492292SN/A // ARM instructions will not have a pkt if the predicate is false 1502292SN/A uint64_t memData = pkt->get<typeof(Mem)>(); 1512292SN/A 1525529Snate@binkert.org %(postacc_code)s; 1535529Snate@binkert.org 1545529Snate@binkert.org if (fault == NoFault) { 1552292SN/A %(op_wb)s; 1564329Sktlim@umich.edu } 1574329Sktlim@umich.edu } 1584329Sktlim@umich.edu 1592907Sktlim@umich.edu return fault; 1602907Sktlim@umich.edu } 1612292SN/A}}; 1622292SN/A 16310175SMitch.Hayenga@ARM.comdef template LoadExecute {{ 16410175SMitch.Hayenga@ARM.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1652329SN/A Trace::InstRecord *traceData) const 1662329SN/A { 1672329SN/A Addr EA; 1682292SN/A Fault fault = NoFault; 1699936SFaissal.Sleiman@arm.com 1709936SFaissal.Sleiman@arm.com %(op_decl)s; 1719936SFaissal.Sleiman@arm.com %(op_rd)s; 1729936SFaissal.Sleiman@arm.com %(ea_code)s; 1732292SN/A 1742292SN/A if (%(predicate_test)s) 1752292SN/A { 1768199SAli.Saidi@ARM.com if (fault == NoFault) { 1778199SAli.Saidi@ARM.com fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1789444SAndreas.Sandberg@ARM.com %(memacc_code)s; 1799444SAndreas.Sandberg@ARM.com } 1809444SAndreas.Sandberg@ARM.com 1819444SAndreas.Sandberg@ARM.com if (fault == NoFault) { 1829444SAndreas.Sandberg@ARM.com %(op_wb)s; 1839444SAndreas.Sandberg@ARM.com } 1849444SAndreas.Sandberg@ARM.com } else { 1859444SAndreas.Sandberg@ARM.com xc->setPredicate(false); 1869444SAndreas.Sandberg@ARM.com } 1879444SAndreas.Sandberg@ARM.com 1889444SAndreas.Sandberg@ARM.com return fault; 1899444SAndreas.Sandberg@ARM.com } 1908199SAli.Saidi@ARM.com}}; 1912292SN/A 1922292SN/Adef template NeonLoadExecute {{ 1932292SN/A template <class Element> 1942292SN/A Fault %(class_name)s<Element>::execute( 1952292SN/A %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1962292SN/A { 1973492Sktlim@umich.edu Addr EA; 1982329SN/A Fault fault = NoFault; 1992292SN/A 2009444SAndreas.Sandberg@ARM.com %(op_decl)s; 2019444SAndreas.Sandberg@ARM.com %(mem_decl)s; 2029814Sandreas.hansson@arm.com %(op_rd)s; 2032292SN/A %(ea_code)s; 2042292SN/A 2052292SN/A MemUnion memUnion; 2062292SN/A uint8_t *dataPtr = memUnion.bytes; 2072292SN/A 2082292SN/A if (%(predicate_test)s) 2092292SN/A { 2102292SN/A if (fault == NoFault) { 2112292SN/A fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 21210386Sandreas.hansson@arm.com %(memacc_code)s; 2132292SN/A } 2142292SN/A 2152292SN/A if (fault == NoFault) { 2162292SN/A %(op_wb)s; 2172292SN/A } 2182727Sktlim@umich.edu } else { 2192727Sktlim@umich.edu xc->setPredicate(false); 2202727Sktlim@umich.edu } 2212727Sktlim@umich.edu 2222727Sktlim@umich.edu return fault; 2232727Sktlim@umich.edu } 2242727Sktlim@umich.edu}}; 2252727Sktlim@umich.edu 2262727Sktlim@umich.edudef template StoreExecute {{ 2272727Sktlim@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2282727Sktlim@umich.edu Trace::InstRecord *traceData) const 2292727Sktlim@umich.edu { 2302727Sktlim@umich.edu Addr EA; 2312727Sktlim@umich.edu Fault fault = NoFault; 2322727Sktlim@umich.edu 2332727Sktlim@umich.edu %(op_decl)s; 2342727Sktlim@umich.edu %(op_rd)s; 2352727Sktlim@umich.edu %(ea_code)s; 2362361SN/A 2372361SN/A if (%(predicate_test)s) 2382361SN/A { 2392361SN/A if (fault == NoFault) { 2402727Sktlim@umich.edu %(memacc_code)s; 2412727Sktlim@umich.edu } 2422727Sktlim@umich.edu 2432727Sktlim@umich.edu if (fault == NoFault) { 2442727Sktlim@umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2452727Sktlim@umich.edu memAccessFlags, NULL); 2462727Sktlim@umich.edu } 2472727Sktlim@umich.edu 2482727Sktlim@umich.edu if (fault == NoFault) { 2492727Sktlim@umich.edu %(op_wb)s; 2502727Sktlim@umich.edu } 2512727Sktlim@umich.edu } else { 2522727Sktlim@umich.edu xc->setPredicate(false); 2532727Sktlim@umich.edu } 2542727Sktlim@umich.edu 2552727Sktlim@umich.edu return fault; 2562727Sktlim@umich.edu } 2572727Sktlim@umich.edu}}; 2582727Sktlim@umich.edu 2592727Sktlim@umich.edudef template NeonStoreExecute {{ 2602727Sktlim@umich.edu template <class Element> 2612727Sktlim@umich.edu Fault %(class_name)s<Element>::execute( 2622727Sktlim@umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2638922Swilliam.wang@arm.com { 2644329Sktlim@umich.edu Addr EA; 2654329Sktlim@umich.edu Fault fault = NoFault; 2664329Sktlim@umich.edu 2674329Sktlim@umich.edu %(op_decl)s; 2684329Sktlim@umich.edu %(mem_decl)s; 2694329Sktlim@umich.edu %(op_rd)s; 2702292SN/A %(ea_code)s; 2712292SN/A 2722292SN/A MemUnion memUnion; 2732292SN/A uint8_t *dataPtr = memUnion.bytes; 2742292SN/A 2752292SN/A if (%(predicate_test)s) 2762292SN/A { 2772292SN/A if (fault == NoFault) { 2782292SN/A %(memacc_code)s; 2792292SN/A } 2802292SN/A 2812292SN/A if (fault == NoFault) { 2822292SN/A fault = xc->writeBytes(dataPtr, %(size)d, EA, 2832292SN/A memAccessFlags, NULL); 2849444SAndreas.Sandberg@ARM.com } 2852307SN/A 2869444SAndreas.Sandberg@ARM.com if (fault == NoFault) { 2872367SN/A %(op_wb)s; 2882307SN/A } 2892329SN/A } else { 2909444SAndreas.Sandberg@ARM.com xc->setPredicate(false); 2912307SN/A } 2922307SN/A 2932307SN/A return fault; 2942307SN/A } 2952307SN/A}}; 2962307SN/A 2979444SAndreas.Sandberg@ARM.comdef template StoreExExecute {{ 2982307SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2992307SN/A Trace::InstRecord *traceData) const 3002307SN/A { 3012307SN/A Addr EA; 3022292SN/A Fault fault = NoFault; 3032292SN/A 3042329SN/A %(op_decl)s; 3052329SN/A %(op_rd)s; 3062292SN/A %(ea_code)s; 3072329SN/A 3082329SN/A if (%(predicate_test)s) 3092292SN/A { 3102292SN/A if (fault == NoFault) { 3112292SN/A %(memacc_code)s; 3122292SN/A } 3132292SN/A 3142329SN/A uint64_t writeResult; 3152292SN/A 3162292SN/A if (fault == NoFault) { 3179936SFaissal.Sleiman@arm.com fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3182292SN/A memAccessFlags, &writeResult); 3192292SN/A } 3202292SN/A 3212292SN/A if (fault == NoFault) { 3222292SN/A %(postacc_code)s; 3232292SN/A } 3242329SN/A 3252329SN/A if (fault == NoFault) { 3262329SN/A %(op_wb)s; 3272292SN/A } 3282292SN/A } else { 3292292SN/A xc->setPredicate(false); 3302292SN/A } 3312292SN/A 3322329SN/A return fault; 3332292SN/A } 3349936SFaissal.Sleiman@arm.com}}; 3359936SFaissal.Sleiman@arm.com 3362292SN/Adef template StoreExInitiateAcc {{ 3372292SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3382292SN/A Trace::InstRecord *traceData) const 3392292SN/A { 3402292SN/A Addr EA; 3412292SN/A Fault fault = NoFault; 3422292SN/A 3432292SN/A %(op_decl)s; 3442292SN/A %(op_rd)s; 3452292SN/A %(ea_code)s; 3462292SN/A 3472292SN/A if (%(predicate_test)s) 3482292SN/A { 3492292SN/A if (fault == NoFault) { 3502292SN/A %(memacc_code)s; 3512292SN/A } 3522292SN/A 3532292SN/A if (fault == NoFault) { 3542292SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3552292SN/A memAccessFlags, NULL); 3562292SN/A } 3572292SN/A } else { 3582292SN/A xc->setPredicate(false); 3592329SN/A } 3602329SN/A 3612292SN/A return fault; 3627720Sgblack@eecs.umich.edu } 3637720Sgblack@eecs.umich.edu}}; 3642292SN/A 3652292SN/Adef template StoreInitiateAcc {{ 3662292SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3672292SN/A Trace::InstRecord *traceData) const 3682292SN/A { 3692292SN/A Addr EA; 3702292SN/A Fault fault = NoFault; 3712292SN/A 3722292SN/A %(op_decl)s; 3732292SN/A %(op_rd)s; 3742292SN/A %(ea_code)s; 3752292SN/A 3762292SN/A if (%(predicate_test)s) 3772292SN/A { 3782292SN/A if (fault == NoFault) { 3792292SN/A %(memacc_code)s; 3802292SN/A } 3812292SN/A 3822292SN/A if (fault == NoFault) { 3832292SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3842292SN/A memAccessFlags, NULL); 3852292SN/A } 3862292SN/A } else { 3872292SN/A xc->setPredicate(false); 3887720Sgblack@eecs.umich.edu } 3897720Sgblack@eecs.umich.edu 3902292SN/A return fault; 3912292SN/A } 3922292SN/A}}; 3932292SN/A 3942292SN/Adef template NeonStoreInitiateAcc {{ 3952292SN/A template <class Element> 3962292SN/A Fault %(class_name)s<Element>::initiateAcc( 3972292SN/A %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 3982292SN/A { 3992292SN/A Addr EA; 4002292SN/A Fault fault = NoFault; 4012292SN/A 4022292SN/A %(op_decl)s; 4032292SN/A %(mem_decl)s; 4042292SN/A %(op_rd)s; 4052292SN/A %(ea_code)s; 4062292SN/A 4072292SN/A if (%(predicate_test)s) 4082292SN/A { 4092292SN/A MemUnion memUnion; 4102292SN/A if (fault == NoFault) { 4112292SN/A %(memacc_code)s; 4122292SN/A } 4132292SN/A 41410239Sbinhpham@cs.rutgers.edu if (fault == NoFault) { 4152292SN/A fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 41610239Sbinhpham@cs.rutgers.edu memAccessFlags, NULL); 41710239Sbinhpham@cs.rutgers.edu } 41810239Sbinhpham@cs.rutgers.edu } else { 41910239Sbinhpham@cs.rutgers.edu xc->setPredicate(false); 42010239Sbinhpham@cs.rutgers.edu } 4212292SN/A 42210239Sbinhpham@cs.rutgers.edu return fault; 42310239Sbinhpham@cs.rutgers.edu } 42410239Sbinhpham@cs.rutgers.edu}}; 42510239Sbinhpham@cs.rutgers.edu 42610239Sbinhpham@cs.rutgers.edudef template LoadInitiateAcc {{ 42710239Sbinhpham@cs.rutgers.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 42810239Sbinhpham@cs.rutgers.edu Trace::InstRecord *traceData) const 42910239Sbinhpham@cs.rutgers.edu { 43010239Sbinhpham@cs.rutgers.edu Addr EA; 43110239Sbinhpham@cs.rutgers.edu Fault fault = NoFault; 4322292SN/A 4332292SN/A %(op_src_decl)s; 4348545Ssaidi@eecs.umich.edu %(op_rd)s; 4358545Ssaidi@eecs.umich.edu %(ea_code)s; 4368545Ssaidi@eecs.umich.edu 4378545Ssaidi@eecs.umich.edu if (%(predicate_test)s) 43810030SAli.Saidi@ARM.com { 4398545Ssaidi@eecs.umich.edu if (fault == NoFault) { 4409383SAli.Saidi@ARM.com fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 4419383SAli.Saidi@ARM.com } 4429383SAli.Saidi@ARM.com } else { 4439383SAli.Saidi@ARM.com xc->setPredicate(false); 44410030SAli.Saidi@ARM.com } 4459383SAli.Saidi@ARM.com 4469383SAli.Saidi@ARM.com return fault; 4479383SAli.Saidi@ARM.com } 4489383SAli.Saidi@ARM.com}}; 4499383SAli.Saidi@ARM.com 4509383SAli.Saidi@ARM.comdef template NeonLoadInitiateAcc {{ 4519383SAli.Saidi@ARM.com template <class Element> 45210030SAli.Saidi@ARM.com Fault %(class_name)s<Element>::initiateAcc( 45310030SAli.Saidi@ARM.com %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 45410030SAli.Saidi@ARM.com { 45510030SAli.Saidi@ARM.com Addr EA; 45611097Songal@cs.wisc.edu Fault fault = NoFault; 45711097Songal@cs.wisc.edu 45811097Songal@cs.wisc.edu %(op_decl)s; 45910030SAli.Saidi@ARM.com %(mem_decl)s; 46011097Songal@cs.wisc.edu %(op_rd)s; 46111097Songal@cs.wisc.edu %(ea_code)s; 46211097Songal@cs.wisc.edu 46310030SAli.Saidi@ARM.com MemUnion memUnion; 46410030SAli.Saidi@ARM.com uint8_t *dataPtr = memUnion.bytes; 46510030SAli.Saidi@ARM.com 4668545Ssaidi@eecs.umich.edu if (%(predicate_test)s) 4678545Ssaidi@eecs.umich.edu { 4688545Ssaidi@eecs.umich.edu if (fault == NoFault) { 46910030SAli.Saidi@ARM.com fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 4708545Ssaidi@eecs.umich.edu } 4718545Ssaidi@eecs.umich.edu } else { 47210149Smarco.elver@ed.ac.uk xc->setPredicate(false); 47310149Smarco.elver@ed.ac.uk } 4748545Ssaidi@eecs.umich.edu 4758545Ssaidi@eecs.umich.edu return fault; 4768545Ssaidi@eecs.umich.edu } 47710824SAndreas.Sandberg@ARM.com}}; 4788545Ssaidi@eecs.umich.edu 4798545Ssaidi@eecs.umich.edudef template LoadCompleteAcc {{ 4808545Ssaidi@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4818545Ssaidi@eecs.umich.edu %(CPU_exec_context)s *xc, 48211097Songal@cs.wisc.edu Trace::InstRecord *traceData) const 48311097Songal@cs.wisc.edu { 48411097Songal@cs.wisc.edu Fault fault = NoFault; 4858545Ssaidi@eecs.umich.edu 48611097Songal@cs.wisc.edu %(op_decl)s; 4878545Ssaidi@eecs.umich.edu %(op_rd)s; 48811097Songal@cs.wisc.edu 48911097Songal@cs.wisc.edu if (%(predicate_test)s) 49010149Smarco.elver@ed.ac.uk { 49110149Smarco.elver@ed.ac.uk // ARM instructions will not have a pkt if the predicate is false 49210149Smarco.elver@ed.ac.uk Mem = pkt->get<typeof(Mem)>(); 49310149Smarco.elver@ed.ac.uk 49410149Smarco.elver@ed.ac.uk if (fault == NoFault) { 49510149Smarco.elver@ed.ac.uk %(memacc_code)s; 49610149Smarco.elver@ed.ac.uk } 4978545Ssaidi@eecs.umich.edu 49810030SAli.Saidi@ARM.com if (fault == NoFault) { 4998545Ssaidi@eecs.umich.edu %(op_wb)s; 5008545Ssaidi@eecs.umich.edu } 50110474Sandreas.hansson@arm.com } 5028545Ssaidi@eecs.umich.edu 50310030SAli.Saidi@ARM.com return fault; 50410030SAli.Saidi@ARM.com } 50510030SAli.Saidi@ARM.com}}; 50610030SAli.Saidi@ARM.com 50710030SAli.Saidi@ARM.comdef template NeonLoadCompleteAcc {{ 50810030SAli.Saidi@ARM.com template <class Element> 50910030SAli.Saidi@ARM.com Fault %(class_name)s<Element>::completeAcc( 51010030SAli.Saidi@ARM.com PacketPtr pkt, %(CPU_exec_context)s *xc, 51110030SAli.Saidi@ARM.com Trace::InstRecord *traceData) const 5128545Ssaidi@eecs.umich.edu { 5138545Ssaidi@eecs.umich.edu Fault fault = NoFault; 5148545Ssaidi@eecs.umich.edu 5159046SAli.Saidi@ARM.com %(mem_decl)s; 5168545Ssaidi@eecs.umich.edu %(op_decl)s; 5178545Ssaidi@eecs.umich.edu %(op_rd)s; 5188545Ssaidi@eecs.umich.edu 5198545Ssaidi@eecs.umich.edu if (%(predicate_test)s) 5208545Ssaidi@eecs.umich.edu { 5218545Ssaidi@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5228545Ssaidi@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5238545Ssaidi@eecs.umich.edu 5242292SN/A if (fault == NoFault) { 5258199SAli.Saidi@ARM.com %(memacc_code)s; 5268199SAli.Saidi@ARM.com } 5278199SAli.Saidi@ARM.com 5288199SAli.Saidi@ARM.com if (fault == NoFault) { 5298199SAli.Saidi@ARM.com %(op_wb)s; 5308199SAli.Saidi@ARM.com } 5318199SAli.Saidi@ARM.com } 5328199SAli.Saidi@ARM.com 5338199SAli.Saidi@ARM.com return fault; 5348199SAli.Saidi@ARM.com } 5358199SAli.Saidi@ARM.com}}; 5368199SAli.Saidi@ARM.com 53710824SAndreas.Sandberg@ARM.comdef template StoreCompleteAcc {{ 5388199SAli.Saidi@ARM.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 5398199SAli.Saidi@ARM.com %(CPU_exec_context)s *xc, 5408199SAli.Saidi@ARM.com Trace::InstRecord *traceData) const 5418199SAli.Saidi@ARM.com { 5428199SAli.Saidi@ARM.com return NoFault; 5438199SAli.Saidi@ARM.com } 5448199SAli.Saidi@ARM.com}}; 5458199SAli.Saidi@ARM.com 5468272SAli.Saidi@ARM.comdef template NeonStoreCompleteAcc {{ 5478545Ssaidi@eecs.umich.edu template <class Element> 5488545Ssaidi@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5498545Ssaidi@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5508545Ssaidi@eecs.umich.edu Trace::InstRecord *traceData) const 5519046SAli.Saidi@ARM.com { 5528545Ssaidi@eecs.umich.edu return NoFault; 5538545Ssaidi@eecs.umich.edu } 5548545Ssaidi@eecs.umich.edu}}; 5558592Sgblack@eecs.umich.edu 5568592Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 5578545Ssaidi@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5588199SAli.Saidi@ARM.com %(CPU_exec_context)s *xc, 5598545Ssaidi@eecs.umich.edu Trace::InstRecord *traceData) const 5608199SAli.Saidi@ARM.com { 56110474Sandreas.hansson@arm.com Fault fault = NoFault; 56210474Sandreas.hansson@arm.com 56310474Sandreas.hansson@arm.com %(op_decl)s; 56410474Sandreas.hansson@arm.com %(op_rd)s; 5658545Ssaidi@eecs.umich.edu 5668545Ssaidi@eecs.umich.edu if (%(predicate_test)s) 5678199SAli.Saidi@ARM.com { 5688545Ssaidi@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5698545Ssaidi@eecs.umich.edu %(postacc_code)s; 5709046SAli.Saidi@ARM.com 57110575SMarco.Elver@ARM.com if (fault == NoFault) { 5728545Ssaidi@eecs.umich.edu %(op_wb)s; 5738545Ssaidi@eecs.umich.edu } 5748545Ssaidi@eecs.umich.edu } 5758545Ssaidi@eecs.umich.edu 5768545Ssaidi@eecs.umich.edu return fault; 5778545Ssaidi@eecs.umich.edu } 5788545Ssaidi@eecs.umich.edu}}; 5798545Ssaidi@eecs.umich.edu 5808545Ssaidi@eecs.umich.edudef template RfeDeclare {{ 5818592Sgblack@eecs.umich.edu /** 5828592Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5838592Sgblack@eecs.umich.edu */ 5848545Ssaidi@eecs.umich.edu class %(class_name)s : public %(base_class)s 5858545Ssaidi@eecs.umich.edu { 5868545Ssaidi@eecs.umich.edu public: 5878545Ssaidi@eecs.umich.edu 58810474Sandreas.hansson@arm.com /// Constructor. 58910474Sandreas.hansson@arm.com %(class_name)s(ExtMachInst machInst, 59010474Sandreas.hansson@arm.com uint32_t _base, int _mode, bool _wb); 59110474Sandreas.hansson@arm.com 5928545Ssaidi@eecs.umich.edu %(BasicExecDeclare)s 5938199SAli.Saidi@ARM.com 5948199SAli.Saidi@ARM.com %(InitiateAccDeclare)s 5958199SAli.Saidi@ARM.com 5968199SAli.Saidi@ARM.com %(CompleteAccDeclare)s 5978199SAli.Saidi@ARM.com }; 5988199SAli.Saidi@ARM.com}}; 5998199SAli.Saidi@ARM.com 6008199SAli.Saidi@ARM.comdef template SrsDeclare {{ 6018199SAli.Saidi@ARM.com /** 6028199SAli.Saidi@ARM.com * Static instruction class for "%(mnemonic)s". 6038199SAli.Saidi@ARM.com */ 6048199SAli.Saidi@ARM.com class %(class_name)s : public %(base_class)s 6052292SN/A { 6062292SN/A public: 6074032Sktlim@umich.edu 6082292SN/A /// Constructor. 6092292SN/A %(class_name)s(ExtMachInst machInst, 6102292SN/A uint32_t _regMode, int _mode, bool _wb); 6117720Sgblack@eecs.umich.edu 6127944SGiacomo.Gabrielli@arm.com %(BasicExecDeclare)s 6132292SN/A 6144032Sktlim@umich.edu %(InitiateAccDeclare)s 6154032Sktlim@umich.edu 6162669Sktlim@umich.edu %(CompleteAccDeclare)s 6172292SN/A }; 6187944SGiacomo.Gabrielli@arm.com}}; 6197944SGiacomo.Gabrielli@arm.com 6207944SGiacomo.Gabrielli@arm.comdef template SwapDeclare {{ 6217944SGiacomo.Gabrielli@arm.com /** 6227597Sminkyu.jeong@arm.com * Static instruction class for "%(mnemonic)s". 6237597Sminkyu.jeong@arm.com */ 62410231Ssteve.reinhardt@amd.com class %(class_name)s : public %(base_class)s 6252329SN/A { 62610824SAndreas.Sandberg@ARM.com public: 62710824SAndreas.Sandberg@ARM.com 62810824SAndreas.Sandberg@ARM.com /// Constructor. 62910231Ssteve.reinhardt@amd.com %(class_name)s(ExtMachInst machInst, 6307848SAli.Saidi@ARM.com uint32_t _dest, uint32_t _op1, uint32_t _base); 6317600Sminkyu.jeong@arm.com 6327600Sminkyu.jeong@arm.com %(BasicExecDeclare)s 6337600Sminkyu.jeong@arm.com 63410824SAndreas.Sandberg@ARM.com %(InitiateAccDeclare)s 6353731Sktlim@umich.edu 6362367SN/A %(CompleteAccDeclare)s 6372367SN/A }; 6382292SN/A}}; 6392292SN/A 64010333Smitch.hayenga@arm.comdef template LoadStoreDImmDeclare {{ 6419046SAli.Saidi@ARM.com /** 6424032Sktlim@umich.edu * Static instruction class for "%(mnemonic)s". 6434032Sktlim@umich.edu */ 6444032Sktlim@umich.edu class %(class_name)s : public %(base_class)s 6458199SAli.Saidi@ARM.com { 6468199SAli.Saidi@ARM.com public: 6472292SN/A 6482292SN/A /// Constructor. 6492292SN/A %(class_name)s(ExtMachInst machInst, 6502292SN/A uint32_t _dest, uint32_t _dest2, 6512292SN/A uint32_t _base, bool _add, int32_t _imm); 6522292SN/A 6532292SN/A %(BasicExecDeclare)s 6542292SN/A 6552292SN/A %(InitiateAccDeclare)s 6562292SN/A 6572292SN/A %(CompleteAccDeclare)s 6582292SN/A }; 6592292SN/A}}; 6602292SN/A 6612292SN/Adef template StoreExDImmDeclare {{ 6627720Sgblack@eecs.umich.edu /** 6637720Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6642292SN/A */ 6654032Sktlim@umich.edu class %(class_name)s : public %(base_class)s 6664032Sktlim@umich.edu { 6672292SN/A public: 6682292SN/A 6692292SN/A /// Constructor. 6702292SN/A %(class_name)s(ExtMachInst machInst, 6712292SN/A uint32_t _result, uint32_t _dest, uint32_t _dest2, 6722292SN/A uint32_t _base, bool _add, int32_t _imm); 6737944SGiacomo.Gabrielli@arm.com 6747944SGiacomo.Gabrielli@arm.com %(BasicExecDeclare)s 6757944SGiacomo.Gabrielli@arm.com 6767944SGiacomo.Gabrielli@arm.com %(InitiateAccDeclare)s 67710231Ssteve.reinhardt@amd.com 6787848SAli.Saidi@ARM.com %(CompleteAccDeclare)s 6797848SAli.Saidi@ARM.com }; 6802329SN/A}}; 6817782Sminkyu.jeong@arm.com 6827720Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6832292SN/A /** 6842292SN/A * Static instruction class for "%(mnemonic)s". 68510231Ssteve.reinhardt@amd.com */ 6867782Sminkyu.jeong@arm.com class %(class_name)s : public %(base_class)s 6877782Sminkyu.jeong@arm.com { 6887782Sminkyu.jeong@arm.com public: 6892292SN/A 6902292SN/A /// Constructor. 6912292SN/A %(class_name)s(ExtMachInst machInst, 6922292SN/A uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6932336SN/A 6942336SN/A %(BasicExecDeclare)s 6952336SN/A 6962329SN/A %(InitiateAccDeclare)s 6972292SN/A 6982329SN/A %(CompleteAccDeclare)s 6992292SN/A }; 7002292SN/A}}; 7018199SAli.Saidi@ARM.com 7022292SN/Adef template StoreExImmDeclare {{ 7032292SN/A /** 7042292SN/A * Static instruction class for "%(mnemonic)s". 7052292SN/A */ 7062292SN/A class %(class_name)s : public %(base_class)s 7072292SN/A { 7082292SN/A public: 7092292SN/A 7102292SN/A /// Constructor. 7117720Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7127720Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7132292SN/A bool _add, int32_t _imm); 7142292SN/A 7152292SN/A %(BasicExecDeclare)s 7162292SN/A 7172292SN/A %(InitiateAccDeclare)s 7182292SN/A 7192292SN/A %(CompleteAccDeclare)s 7202292SN/A }; 7212292SN/A}}; 7222292SN/A 7232292SN/Adef template StoreDRegDeclare {{ 7242292SN/A /** 7252292SN/A * Static instruction class for "%(mnemonic)s". 7262292SN/A */ 7272292SN/A class %(class_name)s : public %(base_class)s 7282292SN/A { 7292292SN/A public: 7302292SN/A 7312292SN/A /// Constructor. 7322292SN/A %(class_name)s(ExtMachInst machInst, 7332292SN/A uint32_t _dest, uint32_t _dest2, 7342292SN/A uint32_t _base, bool _add, 7352292SN/A int32_t _shiftAmt, uint32_t _shiftType, 7362292SN/A uint32_t _index); 7372292SN/A 7382292SN/A %(BasicExecDeclare)s 7392292SN/A 7402292SN/A %(InitiateAccDeclare)s 7412292SN/A 7422329SN/A %(CompleteAccDeclare)s 7432329SN/A }; 7442292SN/A}}; 7452292SN/A 7462292SN/Adef template StoreRegDeclare {{ 7472292SN/A /** 7482292SN/A * Static instruction class for "%(mnemonic)s". 7497720Sgblack@eecs.umich.edu */ 7507720Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7512292SN/A { 7522292SN/A public: 7532292SN/A 7542292SN/A /// Constructor. 7552292SN/A %(class_name)s(ExtMachInst machInst, 7562292SN/A uint32_t _dest, uint32_t _base, bool _add, 7572292SN/A int32_t _shiftAmt, uint32_t _shiftType, 7582292SN/A uint32_t _index); 7592292SN/A 7602292SN/A %(BasicExecDeclare)s 7612292SN/A 7622292SN/A %(InitiateAccDeclare)s 7632292SN/A 7646974Stjones1@inf.ed.ac.uk %(CompleteAccDeclare)s 7656974Stjones1@inf.ed.ac.uk }; 7666974Stjones1@inf.ed.ac.uk}}; 7676974Stjones1@inf.ed.ac.uk 7686974Stjones1@inf.ed.ac.ukdef template LoadDRegDeclare {{ 7696974Stjones1@inf.ed.ac.uk /** 7706974Stjones1@inf.ed.ac.uk * Static instruction class for "%(mnemonic)s". 7716974Stjones1@inf.ed.ac.uk */ 7726974Stjones1@inf.ed.ac.uk class %(class_name)s : public %(base_class)s 7736974Stjones1@inf.ed.ac.uk { 7746974Stjones1@inf.ed.ac.uk public: 7756974Stjones1@inf.ed.ac.uk 7766974Stjones1@inf.ed.ac.uk /// Constructor. 7776974Stjones1@inf.ed.ac.uk %(class_name)s(ExtMachInst machInst, 7786974Stjones1@inf.ed.ac.uk uint32_t _dest, uint32_t _dest2, 7796974Stjones1@inf.ed.ac.uk uint32_t _base, bool _add, 7802292SN/A int32_t _shiftAmt, uint32_t _shiftType, 7812292SN/A uint32_t _index); 7826974Stjones1@inf.ed.ac.uk 7836974Stjones1@inf.ed.ac.uk %(BasicExecDeclare)s 7846974Stjones1@inf.ed.ac.uk 7856974Stjones1@inf.ed.ac.uk %(InitiateAccDeclare)s 7866974Stjones1@inf.ed.ac.uk 7876974Stjones1@inf.ed.ac.uk %(CompleteAccDeclare)s 7882292SN/A }; 7892292SN/A}}; 7902292SN/A 7912292SN/Adef template LoadRegDeclare {{ 7928727Snilay@cs.wisc.edu /** 7932292SN/A * Static instruction class for "%(mnemonic)s". 7942292SN/A */ 79510333Smitch.hayenga@arm.com class %(class_name)s : public %(base_class)s 7962678Sktlim@umich.edu { 7972678Sktlim@umich.edu public: 7982678Sktlim@umich.edu 7992678Sktlim@umich.edu /// Constructor. 8002678Sktlim@umich.edu %(class_name)s(ExtMachInst machInst, 8012329SN/A uint32_t _dest, uint32_t _base, bool _add, 8022329SN/A int32_t _shiftAmt, uint32_t _shiftType, 8032292SN/A uint32_t _index); 8042292SN/A 8052292SN/A %(BasicExecDeclare)s 8062292SN/A 8072292SN/A %(InitiateAccDeclare)s 8082292SN/A 8092292SN/A %(CompleteAccDeclare)s 8102678Sktlim@umich.edu }; 8112292SN/A}}; 8122292SN/A 8132292SN/Adef template LoadImmDeclare {{ 8142292SN/A /** 8152292SN/A * Static instruction class for "%(mnemonic)s". 8162292SN/A */ 8172292SN/A class %(class_name)s : public %(base_class)s 8182292SN/A { 8192292SN/A public: 8202292SN/A 8212292SN/A /// Constructor. 8226974Stjones1@inf.ed.ac.uk %(class_name)s(ExtMachInst machInst, 8236974Stjones1@inf.ed.ac.uk uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8246974Stjones1@inf.ed.ac.uk 8256974Stjones1@inf.ed.ac.uk %(BasicExecDeclare)s 8266974Stjones1@inf.ed.ac.uk 8272669Sktlim@umich.edu %(InitiateAccDeclare)s 8282669Sktlim@umich.edu 8292669Sktlim@umich.edu %(CompleteAccDeclare)s 8308481Sgblack@eecs.umich.edu }; 8318481Sgblack@eecs.umich.edu}}; 8328481Sgblack@eecs.umich.edu 8332292SN/Adef template InitiateAccDeclare {{ 8342292SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8352669Sktlim@umich.edu}}; 83610031SAli.Saidi@ARM.com 8373772Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 83810031SAli.Saidi@ARM.com Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 83910031SAli.Saidi@ARM.com}}; 84010031SAli.Saidi@ARM.com 84110031SAli.Saidi@ARM.comdef template RfeConstructor {{ 8422669Sktlim@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8436974Stjones1@inf.ed.ac.uk uint32_t _base, int _mode, bool _wb) 8446974Stjones1@inf.ed.ac.uk : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8452292SN/A (IntRegIndex)_base, (AddrMode)_mode, _wb) 8462678Sktlim@umich.edu { 8472678Sktlim@umich.edu %(constructor)s; 8482678Sktlim@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 8492678Sktlim@umich.edu for (int x = 0; x < _numDestRegs; x++) { 8506974Stjones1@inf.ed.ac.uk _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8516974Stjones1@inf.ed.ac.uk } 8526974Stjones1@inf.ed.ac.uk } 8536974Stjones1@inf.ed.ac.uk#if %(use_uops)d 85410342SCurtis.Dunham@arm.com uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8556974Stjones1@inf.ed.ac.uk int uopIdx = 0; 8566974Stjones1@inf.ed.ac.uk uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8576974Stjones1@inf.ed.ac.uk uops[uopIdx]->setDelayedCommit(); 8586974Stjones1@inf.ed.ac.uk#if %(use_wb)d 85910342SCurtis.Dunham@arm.com uops[++uopIdx] = new %(wb_decl)s; 86010342SCurtis.Dunham@arm.com uops[uopIdx]->setDelayedCommit(); 8616974Stjones1@inf.ed.ac.uk#endif 8626974Stjones1@inf.ed.ac.uk#if %(use_pc)d 8636974Stjones1@inf.ed.ac.uk uops[++uopIdx] = new %(pc_decl)s; 8646974Stjones1@inf.ed.ac.uk#endif 8656974Stjones1@inf.ed.ac.uk uops[uopIdx]->setLastMicroop(); 8666974Stjones1@inf.ed.ac.uk#endif 8676974Stjones1@inf.ed.ac.uk } 8686974Stjones1@inf.ed.ac.uk}}; 8696974Stjones1@inf.ed.ac.uk 8706974Stjones1@inf.ed.ac.ukdef template SrsConstructor {{ 8716974Stjones1@inf.ed.ac.uk inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8726974Stjones1@inf.ed.ac.uk uint32_t _regMode, int _mode, bool _wb) 8736974Stjones1@inf.ed.ac.uk : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8746974Stjones1@inf.ed.ac.uk (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8752678Sktlim@umich.edu { 8767720Sgblack@eecs.umich.edu %(constructor)s; 8772292SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 8787720Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 8793797Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8803221Sktlim@umich.edu } 8812292SN/A } 8822693Sktlim@umich.edu#if %(use_uops)d 8834350Sgblack@eecs.umich.edu assert(numMicroops >= 2); 8846974Stjones1@inf.ed.ac.uk uops = new StaticInstPtr[numMicroops]; 8853326Sktlim@umich.edu uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 8863326Sktlim@umich.edu uops[0]->setDelayedCommit(); 8873326Sktlim@umich.edu uops[1] = new %(wb_decl)s; 8889046SAli.Saidi@ARM.com uops[1]->setLastMicroop(); 88910030SAli.Saidi@ARM.com#endif 8909046SAli.Saidi@ARM.com } 8913326Sktlim@umich.edu}}; 8923326Sktlim@umich.edu 8933326Sktlim@umich.edudef template SwapConstructor {{ 8943326Sktlim@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 8953326Sktlim@umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 8963326Sktlim@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8973326Sktlim@umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 8987823Ssteve.reinhardt@amd.com { 8998887Sgeoffrey.blake@arm.com %(constructor)s; 9008887Sgeoffrey.blake@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9018887Sgeoffrey.blake@arm.com for (int x = 0; x < _numDestRegs; x++) { 9028887Sgeoffrey.blake@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9038887Sgeoffrey.blake@arm.com } 9048887Sgeoffrey.blake@arm.com } 9053326Sktlim@umich.edu } 9063326Sktlim@umich.edu}}; 9073326Sktlim@umich.edu 9082693Sktlim@umich.edudef template LoadStoreDImmConstructor {{ 9092693Sktlim@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9102693Sktlim@umich.edu uint32_t _dest, uint32_t _dest2, 9112693Sktlim@umich.edu uint32_t _base, bool _add, int32_t _imm) 9122693Sktlim@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9132693Sktlim@umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9148481Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9158481Sgblack@eecs.umich.edu { 9168481Sgblack@eecs.umich.edu %(constructor)s; 9178481Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9188481Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9198481Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9208481Sgblack@eecs.umich.edu } 9218481Sgblack@eecs.umich.edu } 9228481Sgblack@eecs.umich.edu#if %(use_uops)d 9238481Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9248481Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9258481Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 9268481Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9278481Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9288481Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9298481Sgblack@eecs.umich.edu#endif 9308481Sgblack@eecs.umich.edu } 9318481Sgblack@eecs.umich.edu}}; 9328481Sgblack@eecs.umich.edu 9338481Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 9348481Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9354032Sktlim@umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9363221Sktlim@umich.edu uint32_t _base, bool _add, int32_t _imm) 9373221Sktlim@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9386974Stjones1@inf.ed.ac.uk (IntRegIndex)_result, 9396974Stjones1@inf.ed.ac.uk (IntRegIndex)_dest, (IntRegIndex)_dest2, 9408481Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9416974Stjones1@inf.ed.ac.uk { 9426974Stjones1@inf.ed.ac.uk %(constructor)s; 9436974Stjones1@inf.ed.ac.uk if (!(condCode == COND_AL || condCode == COND_UC)) { 9442669Sktlim@umich.edu for (int x = 0; x < _numDestRegs; x++) { 9456974Stjones1@inf.ed.ac.uk _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9466974Stjones1@inf.ed.ac.uk } 9478481Sgblack@eecs.umich.edu } 9486974Stjones1@inf.ed.ac.uk#if %(use_uops)d 9496974Stjones1@inf.ed.ac.uk assert(numMicroops >= 2); 9506974Stjones1@inf.ed.ac.uk uops = new StaticInstPtr[numMicroops]; 9516974Stjones1@inf.ed.ac.uk uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9526974Stjones1@inf.ed.ac.uk _base, _add, _imm); 9536974Stjones1@inf.ed.ac.uk uops[0]->setDelayedCommit(); 9546974Stjones1@inf.ed.ac.uk uops[1] = new %(wb_decl)s; 9556974Stjones1@inf.ed.ac.uk uops[1]->setLastMicroop(); 9566974Stjones1@inf.ed.ac.uk#endif 9576974Stjones1@inf.ed.ac.uk } 9586974Stjones1@inf.ed.ac.uk}}; 9596974Stjones1@inf.ed.ac.uk 9606974Stjones1@inf.ed.ac.ukdef template LoadStoreImmConstructor {{ 9616974Stjones1@inf.ed.ac.uk inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9626974Stjones1@inf.ed.ac.uk uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9636974Stjones1@inf.ed.ac.uk : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9646974Stjones1@inf.ed.ac.uk (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9656974Stjones1@inf.ed.ac.uk { 9666974Stjones1@inf.ed.ac.uk %(constructor)s; 9676974Stjones1@inf.ed.ac.uk if (!(condCode == COND_AL || condCode == COND_UC)) { 9686974Stjones1@inf.ed.ac.uk for (int x = 0; x < _numDestRegs; x++) { 9696974Stjones1@inf.ed.ac.uk _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9706974Stjones1@inf.ed.ac.uk } 9716974Stjones1@inf.ed.ac.uk } 9722292SN/A#if %(use_uops)d 9732292SN/A assert(numMicroops >= 2); 9742292SN/A uops = new StaticInstPtr[numMicroops]; 9752292SN/A uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9762292SN/A uops[0]->setDelayedCommit(); 9772292SN/A uops[1] = new %(wb_decl)s; 9782292SN/A uops[1]->setLastMicroop(); 9792292SN/A#endif 9802292SN/A } 9812292SN/A}}; 9822292SN/A 9832292SN/Adef template StoreExImmConstructor {{ 9842292SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9852292SN/A uint32_t _result, uint32_t _dest, uint32_t _base, 9862292SN/A bool _add, int32_t _imm) 9872292SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9882292SN/A (IntRegIndex)_result, (IntRegIndex)_dest, 9892292SN/A (IntRegIndex)_base, _add, _imm) 9902292SN/A { 9912292SN/A %(constructor)s; 9922292SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 9932292SN/A for (int x = 0; x < _numDestRegs; x++) { 9942292SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9952292SN/A } 9962292SN/A } 9972292SN/A#if %(use_uops)d 9982292SN/A assert(numMicroops >= 2); 9992292SN/A uops = new StaticInstPtr[numMicroops]; 10002329SN/A uops[0] = new %(acc_name)s(machInst, _result, _dest, 10012292SN/A _base, _add, _imm); 10022292SN/A uops[0]->setDelayedCommit(); 10032292SN/A uops[1] = new %(wb_decl)s; 10042292SN/A uops[1]->setLastMicroop(); 10052292SN/A#endif 10067720Sgblack@eecs.umich.edu } 10072292SN/A}}; 10087720Sgblack@eecs.umich.edu 10092292SN/Adef template StoreDRegConstructor {{ 10102292SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10112292SN/A uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10122292SN/A int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10132292SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10142292SN/A (IntRegIndex)_dest, (IntRegIndex)_dest2, 10152292SN/A (IntRegIndex)_base, _add, 10162292SN/A _shiftAmt, (ArmShiftType)_shiftType, 10172329SN/A (IntRegIndex)_index) 10182731Sktlim@umich.edu { 10192292SN/A %(constructor)s; 10202292SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 10212292SN/A for (int x = 0; x < _numDestRegs; x++) { 10222292SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10232292SN/A } 10242292SN/A } 10252292SN/A#if %(use_uops)d 10262727Sktlim@umich.edu assert(numMicroops >= 2); 10272292SN/A uops = new StaticInstPtr[numMicroops]; 10282292SN/A uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10294032Sktlim@umich.edu _shiftAmt, _shiftType, _index); 10304032Sktlim@umich.edu uops[0]->setDelayedCommit(); 10314032Sktlim@umich.edu uops[1] = new %(wb_decl)s; 10324032Sktlim@umich.edu uops[1]->setLastMicroop(); 10332292SN/A#endif 10342292SN/A } 10352292SN/A}}; 10362292SN/A 10372292SN/Adef template StoreRegConstructor {{ 10382329SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10392292SN/A uint32_t _dest, uint32_t _base, bool _add, 10402292SN/A int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10412292SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10422292SN/A (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10437720Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10442292SN/A (IntRegIndex)_index) 10457720Sgblack@eecs.umich.edu { 10462292SN/A %(constructor)s; 10472292SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 10482329SN/A for (int x = 0; x < _numDestRegs; x++) { 10492329SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10502292SN/A } 10512292SN/A } 10522292SN/A#if %(use_uops)d 10532292SN/A assert(numMicroops >= 2); 10542292SN/A uops = new StaticInstPtr[numMicroops]; 10552292SN/A uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10562292SN/A _shiftAmt, _shiftType, _index); 10572329SN/A uops[0]->setDelayedCommit(); 10582731Sktlim@umich.edu uops[1] = new %(wb_decl)s; 10592292SN/A uops[1]->setLastMicroop(); 10602292SN/A#endif 10612292SN/A } 10624032Sktlim@umich.edu}}; 10634032Sktlim@umich.edu 10644032Sktlim@umich.edudef template LoadDRegConstructor {{ 10654032Sktlim@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10666974Stjones1@inf.ed.ac.uk uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10676974Stjones1@inf.ed.ac.uk int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10686974Stjones1@inf.ed.ac.uk : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10696974Stjones1@inf.ed.ac.uk (IntRegIndex)_dest, (IntRegIndex)_dest2, 10706974Stjones1@inf.ed.ac.uk (IntRegIndex)_base, _add, 10716974Stjones1@inf.ed.ac.uk _shiftAmt, (ArmShiftType)_shiftType, 10726974Stjones1@inf.ed.ac.uk (IntRegIndex)_index) 10734032Sktlim@umich.edu { 10742292SN/A %(constructor)s; 10752292SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 10762292SN/A for (int x = 0; x < _numDestRegs; x++) { 10772292SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10782292SN/A } 10792292SN/A } 10802292SN/A#if %(use_uops)d 10812727Sktlim@umich.edu assert(numMicroops >= 2); 10822292SN/A uops = new StaticInstPtr[numMicroops]; 10832292SN/A if ((_dest == _index) || (_dest2 == _index)) { 10842292SN/A IntRegIndex wbIndexReg = INTREG_UREG0; 10852292SN/A uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 10862292SN/A uops[0]->setDelayedCommit(); 10873349Sbinkertn@umich.edu uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10882693Sktlim@umich.edu _shiftAmt, _shiftType, _index); 10892693Sktlim@umich.edu uops[1]->setDelayedCommit(); 10902693Sktlim@umich.edu uops[2] = new %(wb_decl)s; 10912693Sktlim@umich.edu uops[2]->setLastMicroop(); 10922693Sktlim@umich.edu } else { 10932693Sktlim@umich.edu IntRegIndex wbIndexReg = index; 10942693Sktlim@umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10952693Sktlim@umich.edu _shiftAmt, _shiftType, _index); 10962693Sktlim@umich.edu uops[0]->setDelayedCommit(); 10972693Sktlim@umich.edu uops[1] = new %(wb_decl)s; 10982693Sktlim@umich.edu uops[1]->setLastMicroop(); 10992693Sktlim@umich.edu } 11002693Sktlim@umich.edu#endif 11012693Sktlim@umich.edu } 11022693Sktlim@umich.edu}}; 11032693Sktlim@umich.edu 11048887Sgeoffrey.blake@arm.comdef template LoadRegConstructor {{ 11052693Sktlim@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11062732Sktlim@umich.edu uint32_t _dest, uint32_t _base, bool _add, 11072693Sktlim@umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11082693Sktlim@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11092693Sktlim@umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11108727Snilay@cs.wisc.edu _shiftAmt, (ArmShiftType)_shiftType, 11118727Snilay@cs.wisc.edu (IntRegIndex)_index) 11128727Snilay@cs.wisc.edu { 11138727Snilay@cs.wisc.edu %(constructor)s; 11142693Sktlim@umich.edu bool conditional = false; 11152693Sktlim@umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 11162693Sktlim@umich.edu conditional = true; 11172693Sktlim@umich.edu for (int x = 0; x < _numDestRegs; x++) { 11182693Sktlim@umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11192678Sktlim@umich.edu } 11202678Sktlim@umich.edu } 11212678Sktlim@umich.edu#if %(use_uops)d 11222678Sktlim@umich.edu assert(numMicroops >= 2); 11232678Sktlim@umich.edu uops = new StaticInstPtr[numMicroops]; 11242678Sktlim@umich.edu if (_dest == INTREG_PC) { 11252678Sktlim@umich.edu IntRegIndex wbIndexReg = index; 11262727Sktlim@umich.edu uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11272678Sktlim@umich.edu _shiftAmt, _shiftType, _index); 11282678Sktlim@umich.edu uops[0]->setDelayedCommit(); 11292678Sktlim@umich.edu uops[1] = new %(wb_decl)s; 11302678Sktlim@umich.edu uops[1]->setDelayedCommit(); 11312678Sktlim@umich.edu uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11322678Sktlim@umich.edu uops[2]->setFlag(StaticInst::IsControl); 113310575SMarco.Elver@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 113410575SMarco.Elver@ARM.com if (conditional) 113510575SMarco.Elver@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 113610575SMarco.Elver@ARM.com else 113710575SMarco.Elver@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 113810575SMarco.Elver@ARM.com uops[2]->setLastMicroop(); 113910575SMarco.Elver@ARM.com } else if(_dest == _index) { 114010575SMarco.Elver@ARM.com IntRegIndex wbIndexReg = INTREG_UREG0; 114110575SMarco.Elver@ARM.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 114210575SMarco.Elver@ARM.com uops[0]->setDelayedCommit(); 114310575SMarco.Elver@ARM.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 114410575SMarco.Elver@ARM.com _shiftAmt, _shiftType, _index); 114510575SMarco.Elver@ARM.com uops[1]->setDelayedCommit(); 114610575SMarco.Elver@ARM.com uops[2] = new %(wb_decl)s; 11472678Sktlim@umich.edu uops[2]->setLastMicroop(); 11482678Sktlim@umich.edu } else { 11492678Sktlim@umich.edu IntRegIndex wbIndexReg = index; 11502678Sktlim@umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11512678Sktlim@umich.edu _shiftAmt, _shiftType, _index); 11522678Sktlim@umich.edu uops[0]->setDelayedCommit(); 11537598Sminkyu.jeong@arm.com uops[1] = new %(wb_decl)s; 11547598Sminkyu.jeong@arm.com uops[1]->setLastMicroop(); 11557598Sminkyu.jeong@arm.com 11562678Sktlim@umich.edu } 11572678Sktlim@umich.edu#endif 11582678Sktlim@umich.edu } 11592678Sktlim@umich.edu}}; 11602292SN/A 11612292SN/Adef template LoadImmConstructor {{ 11622292SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11632292SN/A uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 11642292SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11652292SN/A (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 11662292SN/A { 11672292SN/A %(constructor)s; 11683126Sktlim@umich.edu bool conditional = false; 11692292SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 11702292SN/A conditional = true; 11712292SN/A for (int x = 0; x < _numDestRegs; x++) { 11722292SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11732292SN/A } 11742292SN/A } 11752292SN/A#if %(use_uops)d 11762292SN/A assert(numMicroops >= 2); 11772292SN/A uops = new StaticInstPtr[numMicroops]; 11782292SN/A if (_dest == INTREG_PC) { 11792292SN/A uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11802292SN/A _imm); 11812292SN/A uops[0]->setDelayedCommit(); 11822329SN/A uops[1] = new %(wb_decl)s; 11832329SN/A uops[1]->setDelayedCommit(); 11842329SN/A uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11852292SN/A uops[2]->setFlag(StaticInst::IsControl); 11869527SMatt.Horsnell@arm.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11879527SMatt.Horsnell@arm.com if (conditional) 11889527SMatt.Horsnell@arm.com uops[2]->setFlag(StaticInst::IsCondControl); 11899527SMatt.Horsnell@arm.com else 11909527SMatt.Horsnell@arm.com uops[2]->setFlag(StaticInst::IsUncondControl); 11919527SMatt.Horsnell@arm.com if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) 11929527SMatt.Horsnell@arm.com uops[2]->setFlag(StaticInst::IsReturn); 11932292SN/A uops[2]->setLastMicroop(); 11942292SN/A } else { 11952292SN/A uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 11962292SN/A uops[0]->setDelayedCommit(); 11972292SN/A uops[1] = new %(wb_decl)s; 11982292SN/A uops[1]->setLastMicroop(); 11992292SN/A } 12002292SN/A#endif 12012292SN/A } 12022316SN/A}}; 12032316SN/A 12042329SN/A