mem.isa revision 8072
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 457646Sgene.wu@arm.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 547646Sgene.wu@arm.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 637646Sgene.wu@arm.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 647646Sgene.wu@arm.com %(CPU_exec_context)s *xc, 657646Sgene.wu@arm.com Trace::InstRecord *traceData) const 667646Sgene.wu@arm.com { 677646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 687646Sgene.wu@arm.com return NoFault; 697646Sgene.wu@arm.com } 707646Sgene.wu@arm.com}}; 717646Sgene.wu@arm.com 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edudef template SwapExecute {{ 747205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 757205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767205Sgblack@eecs.umich.edu { 777205Sgblack@eecs.umich.edu Addr EA; 787205Sgblack@eecs.umich.edu Fault fault = NoFault; 797205Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu %(op_decl)s; 817205Sgblack@eecs.umich.edu uint64_t memData = 0; 827205Sgblack@eecs.umich.edu %(op_rd)s; 837205Sgblack@eecs.umich.edu %(ea_code)s; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu if (%(predicate_test)s) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu %(preacc_code)s; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu if (fault == NoFault) { 907205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 917205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 927205Sgblack@eecs.umich.edu } 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu %(postacc_code)s; 967205Sgblack@eecs.umich.edu } 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu %(op_wb)s; 1007205Sgblack@eecs.umich.edu } 1017597Sminkyu.jeong@arm.com } else { 1027597Sminkyu.jeong@arm.com xc->setPredicate(false); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 1067646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 1077408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1087408Sgblack@eecs.umich.edu } 1097408Sgblack@eecs.umich.edu 1107205Sgblack@eecs.umich.edu return fault; 1117205Sgblack@eecs.umich.edu } 1127205Sgblack@eecs.umich.edu}}; 1137205Sgblack@eecs.umich.edu 1147205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 1157205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1167205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1177205Sgblack@eecs.umich.edu { 1187205Sgblack@eecs.umich.edu Addr EA; 1197205Sgblack@eecs.umich.edu Fault fault = NoFault; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu %(op_decl)s; 1227205Sgblack@eecs.umich.edu uint64_t memData = 0; 1237205Sgblack@eecs.umich.edu %(op_rd)s; 1247205Sgblack@eecs.umich.edu %(ea_code)s; 1257205Sgblack@eecs.umich.edu 1267205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1277205Sgblack@eecs.umich.edu { 1287205Sgblack@eecs.umich.edu %(preacc_code)s; 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu if (fault == NoFault) { 1317205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1327205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1337205Sgblack@eecs.umich.edu } 1347597Sminkyu.jeong@arm.com } else { 1357597Sminkyu.jeong@arm.com xc->setPredicate(false); 1367205Sgblack@eecs.umich.edu } 1377205Sgblack@eecs.umich.edu 1387646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 1397646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 1407408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1417408Sgblack@eecs.umich.edu } 1427408Sgblack@eecs.umich.edu 1437205Sgblack@eecs.umich.edu return fault; 1447205Sgblack@eecs.umich.edu } 1457205Sgblack@eecs.umich.edu}}; 1467205Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1487205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1497205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1507205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1517205Sgblack@eecs.umich.edu { 1527205Sgblack@eecs.umich.edu Fault fault = NoFault; 1537205Sgblack@eecs.umich.edu 1547205Sgblack@eecs.umich.edu %(op_decl)s; 1557205Sgblack@eecs.umich.edu %(op_rd)s; 1567205Sgblack@eecs.umich.edu 1577205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1587205Sgblack@eecs.umich.edu { 1597205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1607205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1617205Sgblack@eecs.umich.edu 1627205Sgblack@eecs.umich.edu %(postacc_code)s; 1637205Sgblack@eecs.umich.edu 1647205Sgblack@eecs.umich.edu if (fault == NoFault) { 1657205Sgblack@eecs.umich.edu %(op_wb)s; 1667205Sgblack@eecs.umich.edu } 1677205Sgblack@eecs.umich.edu } 1687205Sgblack@eecs.umich.edu 1697408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1707408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1717408Sgblack@eecs.umich.edu } 1727408Sgblack@eecs.umich.edu 1737205Sgblack@eecs.umich.edu return fault; 1747205Sgblack@eecs.umich.edu } 1757205Sgblack@eecs.umich.edu}}; 1767205Sgblack@eecs.umich.edu 1777119Sgblack@eecs.umich.edudef template LoadExecute {{ 1787119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1797119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1807119Sgblack@eecs.umich.edu { 1817119Sgblack@eecs.umich.edu Addr EA; 1827119Sgblack@eecs.umich.edu Fault fault = NoFault; 1837119Sgblack@eecs.umich.edu 1847119Sgblack@eecs.umich.edu %(op_decl)s; 1857119Sgblack@eecs.umich.edu %(op_rd)s; 1867119Sgblack@eecs.umich.edu %(ea_code)s; 1877119Sgblack@eecs.umich.edu 1887119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1897119Sgblack@eecs.umich.edu { 1907119Sgblack@eecs.umich.edu if (fault == NoFault) { 1917119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1927119Sgblack@eecs.umich.edu %(memacc_code)s; 1937119Sgblack@eecs.umich.edu } 1947119Sgblack@eecs.umich.edu 1957119Sgblack@eecs.umich.edu if (fault == NoFault) { 1967119Sgblack@eecs.umich.edu %(op_wb)s; 1977119Sgblack@eecs.umich.edu } 1987597Sminkyu.jeong@arm.com } else { 1997597Sminkyu.jeong@arm.com xc->setPredicate(false); 2007119Sgblack@eecs.umich.edu } 2017119Sgblack@eecs.umich.edu 2027646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2037646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2047408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2057408Sgblack@eecs.umich.edu } 2067408Sgblack@eecs.umich.edu 2077119Sgblack@eecs.umich.edu return fault; 2087119Sgblack@eecs.umich.edu } 2097119Sgblack@eecs.umich.edu}}; 2107119Sgblack@eecs.umich.edu 2117639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 2127639Sgblack@eecs.umich.edu template <class Element> 2137639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2147639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2157639Sgblack@eecs.umich.edu { 2167639Sgblack@eecs.umich.edu Addr EA; 2177639Sgblack@eecs.umich.edu Fault fault = NoFault; 2187639Sgblack@eecs.umich.edu 2197639Sgblack@eecs.umich.edu %(op_decl)s; 2207639Sgblack@eecs.umich.edu %(mem_decl)s; 2217639Sgblack@eecs.umich.edu %(op_rd)s; 2227639Sgblack@eecs.umich.edu %(ea_code)s; 2237639Sgblack@eecs.umich.edu 2247639Sgblack@eecs.umich.edu MemUnion memUnion; 2257639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2267639Sgblack@eecs.umich.edu 2277639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2287639Sgblack@eecs.umich.edu { 2297639Sgblack@eecs.umich.edu if (fault == NoFault) { 2307639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 2317639Sgblack@eecs.umich.edu %(memacc_code)s; 2327639Sgblack@eecs.umich.edu } 2337639Sgblack@eecs.umich.edu 2347639Sgblack@eecs.umich.edu if (fault == NoFault) { 2357639Sgblack@eecs.umich.edu %(op_wb)s; 2367639Sgblack@eecs.umich.edu } 2378072SGiacomo.Gabrielli@arm.com } else { 2388072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2397639Sgblack@eecs.umich.edu } 2407639Sgblack@eecs.umich.edu 2417646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2427646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2437639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2447639Sgblack@eecs.umich.edu } 2457639Sgblack@eecs.umich.edu 2467639Sgblack@eecs.umich.edu return fault; 2477639Sgblack@eecs.umich.edu } 2487639Sgblack@eecs.umich.edu}}; 2497639Sgblack@eecs.umich.edu 2507120Sgblack@eecs.umich.edudef template StoreExecute {{ 2517120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2527120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2537120Sgblack@eecs.umich.edu { 2547120Sgblack@eecs.umich.edu Addr EA; 2557120Sgblack@eecs.umich.edu Fault fault = NoFault; 2567120Sgblack@eecs.umich.edu 2577120Sgblack@eecs.umich.edu %(op_decl)s; 2587120Sgblack@eecs.umich.edu %(op_rd)s; 2597120Sgblack@eecs.umich.edu %(ea_code)s; 2607120Sgblack@eecs.umich.edu 2617120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2627120Sgblack@eecs.umich.edu { 2637120Sgblack@eecs.umich.edu if (fault == NoFault) { 2647120Sgblack@eecs.umich.edu %(memacc_code)s; 2657120Sgblack@eecs.umich.edu } 2667120Sgblack@eecs.umich.edu 2677120Sgblack@eecs.umich.edu if (fault == NoFault) { 2687120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2697120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2707120Sgblack@eecs.umich.edu } 2717120Sgblack@eecs.umich.edu 2727120Sgblack@eecs.umich.edu if (fault == NoFault) { 2737120Sgblack@eecs.umich.edu %(op_wb)s; 2747120Sgblack@eecs.umich.edu } 2757597Sminkyu.jeong@arm.com } else { 2767597Sminkyu.jeong@arm.com xc->setPredicate(false); 2777120Sgblack@eecs.umich.edu } 2787120Sgblack@eecs.umich.edu 2797646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2807646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2817408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2827408Sgblack@eecs.umich.edu } 2837408Sgblack@eecs.umich.edu 2847120Sgblack@eecs.umich.edu return fault; 2857120Sgblack@eecs.umich.edu } 2867120Sgblack@eecs.umich.edu}}; 2877120Sgblack@eecs.umich.edu 2887639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2897639Sgblack@eecs.umich.edu template <class Element> 2907639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2917639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2927639Sgblack@eecs.umich.edu { 2937639Sgblack@eecs.umich.edu Addr EA; 2947639Sgblack@eecs.umich.edu Fault fault = NoFault; 2957639Sgblack@eecs.umich.edu 2967639Sgblack@eecs.umich.edu %(op_decl)s; 2977639Sgblack@eecs.umich.edu %(mem_decl)s; 2987639Sgblack@eecs.umich.edu %(op_rd)s; 2997639Sgblack@eecs.umich.edu %(ea_code)s; 3007639Sgblack@eecs.umich.edu 3017639Sgblack@eecs.umich.edu MemUnion memUnion; 3027639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 3037639Sgblack@eecs.umich.edu 3047639Sgblack@eecs.umich.edu if (%(predicate_test)s) 3057639Sgblack@eecs.umich.edu { 3067639Sgblack@eecs.umich.edu if (fault == NoFault) { 3077639Sgblack@eecs.umich.edu %(memacc_code)s; 3087639Sgblack@eecs.umich.edu } 3097639Sgblack@eecs.umich.edu 3107639Sgblack@eecs.umich.edu if (fault == NoFault) { 3117639Sgblack@eecs.umich.edu fault = xc->writeBytes(dataPtr, %(size)d, EA, 3127639Sgblack@eecs.umich.edu memAccessFlags, NULL); 3137639Sgblack@eecs.umich.edu } 3147639Sgblack@eecs.umich.edu 3157639Sgblack@eecs.umich.edu if (fault == NoFault) { 3167639Sgblack@eecs.umich.edu %(op_wb)s; 3177639Sgblack@eecs.umich.edu } 3188072SGiacomo.Gabrielli@arm.com } else { 3198072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 3207639Sgblack@eecs.umich.edu } 3217639Sgblack@eecs.umich.edu 3227646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3237646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3247639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3257639Sgblack@eecs.umich.edu } 3267639Sgblack@eecs.umich.edu 3277639Sgblack@eecs.umich.edu return fault; 3287639Sgblack@eecs.umich.edu } 3297639Sgblack@eecs.umich.edu}}; 3307639Sgblack@eecs.umich.edu 3317303Sgblack@eecs.umich.edudef template StoreExExecute {{ 3327303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3337303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3347303Sgblack@eecs.umich.edu { 3357303Sgblack@eecs.umich.edu Addr EA; 3367303Sgblack@eecs.umich.edu Fault fault = NoFault; 3377303Sgblack@eecs.umich.edu 3387303Sgblack@eecs.umich.edu %(op_decl)s; 3397303Sgblack@eecs.umich.edu %(op_rd)s; 3407303Sgblack@eecs.umich.edu %(ea_code)s; 3417303Sgblack@eecs.umich.edu 3427303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3437303Sgblack@eecs.umich.edu { 3447303Sgblack@eecs.umich.edu if (fault == NoFault) { 3457303Sgblack@eecs.umich.edu %(memacc_code)s; 3467303Sgblack@eecs.umich.edu } 3477303Sgblack@eecs.umich.edu 3487303Sgblack@eecs.umich.edu uint64_t writeResult; 3497303Sgblack@eecs.umich.edu 3507303Sgblack@eecs.umich.edu if (fault == NoFault) { 3517303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3527303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 3537303Sgblack@eecs.umich.edu } 3547303Sgblack@eecs.umich.edu 3557303Sgblack@eecs.umich.edu if (fault == NoFault) { 3567303Sgblack@eecs.umich.edu %(postacc_code)s; 3577303Sgblack@eecs.umich.edu } 3587303Sgblack@eecs.umich.edu 3597303Sgblack@eecs.umich.edu if (fault == NoFault) { 3607303Sgblack@eecs.umich.edu %(op_wb)s; 3617303Sgblack@eecs.umich.edu } 3627597Sminkyu.jeong@arm.com } else { 3637597Sminkyu.jeong@arm.com xc->setPredicate(false); 3647303Sgblack@eecs.umich.edu } 3657303Sgblack@eecs.umich.edu 3667646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3677646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3687408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3697408Sgblack@eecs.umich.edu } 3707408Sgblack@eecs.umich.edu 3717303Sgblack@eecs.umich.edu return fault; 3727303Sgblack@eecs.umich.edu } 3737303Sgblack@eecs.umich.edu}}; 3747303Sgblack@eecs.umich.edu 3757303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3767303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3777303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3787303Sgblack@eecs.umich.edu { 3797303Sgblack@eecs.umich.edu Addr EA; 3807303Sgblack@eecs.umich.edu Fault fault = NoFault; 3817303Sgblack@eecs.umich.edu 3827303Sgblack@eecs.umich.edu %(op_decl)s; 3837303Sgblack@eecs.umich.edu %(op_rd)s; 3847303Sgblack@eecs.umich.edu %(ea_code)s; 3857303Sgblack@eecs.umich.edu 3867303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3877303Sgblack@eecs.umich.edu { 3887303Sgblack@eecs.umich.edu if (fault == NoFault) { 3897303Sgblack@eecs.umich.edu %(memacc_code)s; 3907303Sgblack@eecs.umich.edu } 3917303Sgblack@eecs.umich.edu 3927303Sgblack@eecs.umich.edu if (fault == NoFault) { 3937303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3947303Sgblack@eecs.umich.edu memAccessFlags, NULL); 3957303Sgblack@eecs.umich.edu } 3967597Sminkyu.jeong@arm.com } else { 3977597Sminkyu.jeong@arm.com xc->setPredicate(false); 3987303Sgblack@eecs.umich.edu } 3997646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4007646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4017408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4027408Sgblack@eecs.umich.edu } 4037408Sgblack@eecs.umich.edu 4047303Sgblack@eecs.umich.edu return fault; 4057303Sgblack@eecs.umich.edu } 4067303Sgblack@eecs.umich.edu}}; 4077303Sgblack@eecs.umich.edu 4087120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 4097120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4107120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4117120Sgblack@eecs.umich.edu { 4127120Sgblack@eecs.umich.edu Addr EA; 4137120Sgblack@eecs.umich.edu Fault fault = NoFault; 4147120Sgblack@eecs.umich.edu 4157120Sgblack@eecs.umich.edu %(op_decl)s; 4167120Sgblack@eecs.umich.edu %(op_rd)s; 4177120Sgblack@eecs.umich.edu %(ea_code)s; 4187120Sgblack@eecs.umich.edu 4197120Sgblack@eecs.umich.edu if (%(predicate_test)s) 4207120Sgblack@eecs.umich.edu { 4217120Sgblack@eecs.umich.edu if (fault == NoFault) { 4227120Sgblack@eecs.umich.edu %(memacc_code)s; 4237120Sgblack@eecs.umich.edu } 4247120Sgblack@eecs.umich.edu 4257120Sgblack@eecs.umich.edu if (fault == NoFault) { 4267120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 4277120Sgblack@eecs.umich.edu memAccessFlags, NULL); 4287120Sgblack@eecs.umich.edu } 4297597Sminkyu.jeong@arm.com } else { 4307597Sminkyu.jeong@arm.com xc->setPredicate(false); 4317120Sgblack@eecs.umich.edu } 4327120Sgblack@eecs.umich.edu 4337646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4347646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4357408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4367408Sgblack@eecs.umich.edu } 4377408Sgblack@eecs.umich.edu 4387120Sgblack@eecs.umich.edu return fault; 4397120Sgblack@eecs.umich.edu } 4407120Sgblack@eecs.umich.edu}}; 4417120Sgblack@eecs.umich.edu 4427639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 4437639Sgblack@eecs.umich.edu template <class Element> 4447639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4457639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4467639Sgblack@eecs.umich.edu { 4477639Sgblack@eecs.umich.edu Addr EA; 4487639Sgblack@eecs.umich.edu Fault fault = NoFault; 4497639Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edu %(op_decl)s; 4517639Sgblack@eecs.umich.edu %(mem_decl)s; 4527639Sgblack@eecs.umich.edu %(op_rd)s; 4537639Sgblack@eecs.umich.edu %(ea_code)s; 4547639Sgblack@eecs.umich.edu 4557639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4567639Sgblack@eecs.umich.edu { 4577639Sgblack@eecs.umich.edu MemUnion memUnion; 4587639Sgblack@eecs.umich.edu if (fault == NoFault) { 4597639Sgblack@eecs.umich.edu %(memacc_code)s; 4607639Sgblack@eecs.umich.edu } 4617639Sgblack@eecs.umich.edu 4627639Sgblack@eecs.umich.edu if (fault == NoFault) { 4637639Sgblack@eecs.umich.edu fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 4647639Sgblack@eecs.umich.edu memAccessFlags, NULL); 4657639Sgblack@eecs.umich.edu } 4668072SGiacomo.Gabrielli@arm.com } else { 4678072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4687639Sgblack@eecs.umich.edu } 4697639Sgblack@eecs.umich.edu 4707646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4717646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4727639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4737639Sgblack@eecs.umich.edu } 4747639Sgblack@eecs.umich.edu 4757639Sgblack@eecs.umich.edu return fault; 4767639Sgblack@eecs.umich.edu } 4777639Sgblack@eecs.umich.edu}}; 4787639Sgblack@eecs.umich.edu 4797119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4807119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4817119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4827119Sgblack@eecs.umich.edu { 4837119Sgblack@eecs.umich.edu Addr EA; 4847119Sgblack@eecs.umich.edu Fault fault = NoFault; 4857119Sgblack@eecs.umich.edu 4867119Sgblack@eecs.umich.edu %(op_src_decl)s; 4877119Sgblack@eecs.umich.edu %(op_rd)s; 4887119Sgblack@eecs.umich.edu %(ea_code)s; 4897119Sgblack@eecs.umich.edu 4907119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4917119Sgblack@eecs.umich.edu { 4927119Sgblack@eecs.umich.edu if (fault == NoFault) { 4937119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 4947119Sgblack@eecs.umich.edu } 4957597Sminkyu.jeong@arm.com } else { 4967597Sminkyu.jeong@arm.com xc->setPredicate(false); 4977646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4987646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4997597Sminkyu.jeong@arm.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5007597Sminkyu.jeong@arm.com } 5017119Sgblack@eecs.umich.edu } 5027119Sgblack@eecs.umich.edu 5037119Sgblack@eecs.umich.edu return fault; 5047119Sgblack@eecs.umich.edu } 5057119Sgblack@eecs.umich.edu}}; 5067119Sgblack@eecs.umich.edu 5077639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 5087639Sgblack@eecs.umich.edu template <class Element> 5097639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 5107639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 5117639Sgblack@eecs.umich.edu { 5127639Sgblack@eecs.umich.edu Addr EA; 5137639Sgblack@eecs.umich.edu Fault fault = NoFault; 5147639Sgblack@eecs.umich.edu 5157639Sgblack@eecs.umich.edu %(op_src_decl)s; 5167639Sgblack@eecs.umich.edu %(op_rd)s; 5177639Sgblack@eecs.umich.edu %(ea_code)s; 5187639Sgblack@eecs.umich.edu 5197639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5207639Sgblack@eecs.umich.edu { 5217639Sgblack@eecs.umich.edu if (fault == NoFault) { 5227639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 5237639Sgblack@eecs.umich.edu } 5248072SGiacomo.Gabrielli@arm.com } else { 5258072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 5268072SGiacomo.Gabrielli@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 5278072SGiacomo.Gabrielli@arm.com (!isMicroop() || isLastMicroop())) { 5288072SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5298072SGiacomo.Gabrielli@arm.com } 5307639Sgblack@eecs.umich.edu } 5317639Sgblack@eecs.umich.edu 5327639Sgblack@eecs.umich.edu return fault; 5337639Sgblack@eecs.umich.edu } 5347639Sgblack@eecs.umich.edu}}; 5357639Sgblack@eecs.umich.edu 5367119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 5377119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5387119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5397119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5407119Sgblack@eecs.umich.edu { 5417119Sgblack@eecs.umich.edu Fault fault = NoFault; 5427119Sgblack@eecs.umich.edu 5437119Sgblack@eecs.umich.edu %(op_decl)s; 5447119Sgblack@eecs.umich.edu %(op_rd)s; 5457119Sgblack@eecs.umich.edu 5467119Sgblack@eecs.umich.edu if (%(predicate_test)s) 5477119Sgblack@eecs.umich.edu { 5487119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5497119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 5507119Sgblack@eecs.umich.edu 5517119Sgblack@eecs.umich.edu if (fault == NoFault) { 5527119Sgblack@eecs.umich.edu %(memacc_code)s; 5537119Sgblack@eecs.umich.edu } 5547119Sgblack@eecs.umich.edu 5557119Sgblack@eecs.umich.edu if (fault == NoFault) { 5567119Sgblack@eecs.umich.edu %(op_wb)s; 5577119Sgblack@eecs.umich.edu } 5587119Sgblack@eecs.umich.edu } 5597119Sgblack@eecs.umich.edu 5607408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5617408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5627408Sgblack@eecs.umich.edu } 5637408Sgblack@eecs.umich.edu 5647119Sgblack@eecs.umich.edu return fault; 5657119Sgblack@eecs.umich.edu } 5667119Sgblack@eecs.umich.edu}}; 5677119Sgblack@eecs.umich.edu 5687639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5697639Sgblack@eecs.umich.edu template <class Element> 5707639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5717639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5727639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5737639Sgblack@eecs.umich.edu { 5747639Sgblack@eecs.umich.edu Fault fault = NoFault; 5757639Sgblack@eecs.umich.edu 5767639Sgblack@eecs.umich.edu %(mem_decl)s; 5777639Sgblack@eecs.umich.edu %(op_decl)s; 5787639Sgblack@eecs.umich.edu %(op_rd)s; 5797639Sgblack@eecs.umich.edu 5807639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5817639Sgblack@eecs.umich.edu { 5827639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5837639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5847639Sgblack@eecs.umich.edu 5857639Sgblack@eecs.umich.edu if (fault == NoFault) { 5867639Sgblack@eecs.umich.edu %(memacc_code)s; 5877639Sgblack@eecs.umich.edu } 5887639Sgblack@eecs.umich.edu 5897639Sgblack@eecs.umich.edu if (fault == NoFault) { 5907639Sgblack@eecs.umich.edu %(op_wb)s; 5917639Sgblack@eecs.umich.edu } 5927639Sgblack@eecs.umich.edu } 5937639Sgblack@eecs.umich.edu 5947639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5957639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5967639Sgblack@eecs.umich.edu } 5977639Sgblack@eecs.umich.edu 5987639Sgblack@eecs.umich.edu return fault; 5997639Sgblack@eecs.umich.edu } 6007639Sgblack@eecs.umich.edu}}; 6017639Sgblack@eecs.umich.edu 6027120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 6037120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6047120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 6057120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6067120Sgblack@eecs.umich.edu { 6077712Sgblack@eecs.umich.edu if (machInst.itstateMask != 0) { 6087712Sgblack@eecs.umich.edu warn_once("Complete acc isn't called on normal stores in O3."); 6097408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6107408Sgblack@eecs.umich.edu } 6117712Sgblack@eecs.umich.edu return NoFault; 6127120Sgblack@eecs.umich.edu } 6137120Sgblack@eecs.umich.edu}}; 6147120Sgblack@eecs.umich.edu 6157639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 6167639Sgblack@eecs.umich.edu template <class Element> 6177639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 6187639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 6197639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6207639Sgblack@eecs.umich.edu { 6217712Sgblack@eecs.umich.edu if (machInst.itstateMask != 0) { 6227712Sgblack@eecs.umich.edu warn_once("Complete acc isn't called on normal stores in O3."); 6237639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6247639Sgblack@eecs.umich.edu } 6257712Sgblack@eecs.umich.edu return NoFault; 6267639Sgblack@eecs.umich.edu } 6277639Sgblack@eecs.umich.edu}}; 6287639Sgblack@eecs.umich.edu 6297303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 6307303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6317303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 6327303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6337303Sgblack@eecs.umich.edu { 6347303Sgblack@eecs.umich.edu Fault fault = NoFault; 6357303Sgblack@eecs.umich.edu 6367303Sgblack@eecs.umich.edu %(op_decl)s; 6377303Sgblack@eecs.umich.edu %(op_rd)s; 6387303Sgblack@eecs.umich.edu 6397303Sgblack@eecs.umich.edu if (%(predicate_test)s) 6407303Sgblack@eecs.umich.edu { 6417303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 6427303Sgblack@eecs.umich.edu %(postacc_code)s; 6437303Sgblack@eecs.umich.edu 6447303Sgblack@eecs.umich.edu if (fault == NoFault) { 6457303Sgblack@eecs.umich.edu %(op_wb)s; 6467303Sgblack@eecs.umich.edu } 6477303Sgblack@eecs.umich.edu } 6487303Sgblack@eecs.umich.edu 6497408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6507408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6517408Sgblack@eecs.umich.edu } 6527408Sgblack@eecs.umich.edu 6537303Sgblack@eecs.umich.edu return fault; 6547303Sgblack@eecs.umich.edu } 6557303Sgblack@eecs.umich.edu}}; 6567303Sgblack@eecs.umich.edu 6577291Sgblack@eecs.umich.edudef template RfeDeclare {{ 6587291Sgblack@eecs.umich.edu /** 6597291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6607291Sgblack@eecs.umich.edu */ 6617291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6627291Sgblack@eecs.umich.edu { 6637291Sgblack@eecs.umich.edu public: 6647291Sgblack@eecs.umich.edu 6657291Sgblack@eecs.umich.edu /// Constructor. 6667291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6677291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 6687291Sgblack@eecs.umich.edu 6697291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6707291Sgblack@eecs.umich.edu 6717291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6727291Sgblack@eecs.umich.edu 6737291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6747291Sgblack@eecs.umich.edu }; 6757291Sgblack@eecs.umich.edu}}; 6767291Sgblack@eecs.umich.edu 6777312Sgblack@eecs.umich.edudef template SrsDeclare {{ 6787312Sgblack@eecs.umich.edu /** 6797312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6807312Sgblack@eecs.umich.edu */ 6817312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6827312Sgblack@eecs.umich.edu { 6837312Sgblack@eecs.umich.edu public: 6847312Sgblack@eecs.umich.edu 6857312Sgblack@eecs.umich.edu /// Constructor. 6867312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6877312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6887312Sgblack@eecs.umich.edu 6897312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6907312Sgblack@eecs.umich.edu 6917312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6927312Sgblack@eecs.umich.edu 6937312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6947312Sgblack@eecs.umich.edu }; 6957312Sgblack@eecs.umich.edu}}; 6967312Sgblack@eecs.umich.edu 6977205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6987205Sgblack@eecs.umich.edu /** 6997205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7007205Sgblack@eecs.umich.edu */ 7017205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7027205Sgblack@eecs.umich.edu { 7037205Sgblack@eecs.umich.edu public: 7047205Sgblack@eecs.umich.edu 7057205Sgblack@eecs.umich.edu /// Constructor. 7067205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7077205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 7087205Sgblack@eecs.umich.edu 7097205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7107205Sgblack@eecs.umich.edu 7117205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7127205Sgblack@eecs.umich.edu 7137205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7147205Sgblack@eecs.umich.edu }; 7157205Sgblack@eecs.umich.edu}}; 7167205Sgblack@eecs.umich.edu 7177279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 7187279Sgblack@eecs.umich.edu /** 7197279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7207279Sgblack@eecs.umich.edu */ 7217279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7227279Sgblack@eecs.umich.edu { 7237279Sgblack@eecs.umich.edu public: 7247279Sgblack@eecs.umich.edu 7257279Sgblack@eecs.umich.edu /// Constructor. 7267279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7277279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7287279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7297279Sgblack@eecs.umich.edu 7307279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7317279Sgblack@eecs.umich.edu 7327279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7337279Sgblack@eecs.umich.edu 7347279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7357279Sgblack@eecs.umich.edu }; 7367279Sgblack@eecs.umich.edu}}; 7377279Sgblack@eecs.umich.edu 7387303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 7397303Sgblack@eecs.umich.edu /** 7407303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7417303Sgblack@eecs.umich.edu */ 7427303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7437303Sgblack@eecs.umich.edu { 7447303Sgblack@eecs.umich.edu public: 7457303Sgblack@eecs.umich.edu 7467303Sgblack@eecs.umich.edu /// Constructor. 7477303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7487303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 7497303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7507303Sgblack@eecs.umich.edu 7517303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7527303Sgblack@eecs.umich.edu 7537303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7547303Sgblack@eecs.umich.edu 7557303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7567303Sgblack@eecs.umich.edu }; 7577303Sgblack@eecs.umich.edu}}; 7587303Sgblack@eecs.umich.edu 7597119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 7607119Sgblack@eecs.umich.edu /** 7617119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7627119Sgblack@eecs.umich.edu */ 7637119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7647119Sgblack@eecs.umich.edu { 7657119Sgblack@eecs.umich.edu public: 7667119Sgblack@eecs.umich.edu 7677119Sgblack@eecs.umich.edu /// Constructor. 7687119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7697119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 7707119Sgblack@eecs.umich.edu 7717119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7727119Sgblack@eecs.umich.edu 7737119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7747119Sgblack@eecs.umich.edu 7757119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7767119Sgblack@eecs.umich.edu }; 7777119Sgblack@eecs.umich.edu}}; 7787119Sgblack@eecs.umich.edu 7797303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7807303Sgblack@eecs.umich.edu /** 7817303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7827303Sgblack@eecs.umich.edu */ 7837303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7847303Sgblack@eecs.umich.edu { 7857303Sgblack@eecs.umich.edu public: 7867303Sgblack@eecs.umich.edu 7877303Sgblack@eecs.umich.edu /// Constructor. 7887303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7897303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7907303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7917303Sgblack@eecs.umich.edu 7927303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7937303Sgblack@eecs.umich.edu 7947303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7957303Sgblack@eecs.umich.edu 7967303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7977303Sgblack@eecs.umich.edu }; 7987303Sgblack@eecs.umich.edu}}; 7997303Sgblack@eecs.umich.edu 8007646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 8017279Sgblack@eecs.umich.edu /** 8027279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8037279Sgblack@eecs.umich.edu */ 8047279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8057279Sgblack@eecs.umich.edu { 8067279Sgblack@eecs.umich.edu public: 8077279Sgblack@eecs.umich.edu 8087279Sgblack@eecs.umich.edu /// Constructor. 8097279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8107279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 8117279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 8127279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8137279Sgblack@eecs.umich.edu uint32_t _index); 8147279Sgblack@eecs.umich.edu 8157279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8167279Sgblack@eecs.umich.edu 8177279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8187279Sgblack@eecs.umich.edu 8197279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8207279Sgblack@eecs.umich.edu }; 8217279Sgblack@eecs.umich.edu}}; 8227279Sgblack@eecs.umich.edu 8237646Sgene.wu@arm.comdef template StoreRegDeclare {{ 8247119Sgblack@eecs.umich.edu /** 8257119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8267119Sgblack@eecs.umich.edu */ 8277119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8287119Sgblack@eecs.umich.edu { 8297119Sgblack@eecs.umich.edu public: 8307119Sgblack@eecs.umich.edu 8317119Sgblack@eecs.umich.edu /// Constructor. 8327119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8337119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 8347119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8357119Sgblack@eecs.umich.edu uint32_t _index); 8367119Sgblack@eecs.umich.edu 8377119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8387119Sgblack@eecs.umich.edu 8397119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8407119Sgblack@eecs.umich.edu 8417119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8427119Sgblack@eecs.umich.edu }; 8437119Sgblack@eecs.umich.edu}}; 8447119Sgblack@eecs.umich.edu 8457646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 8467646Sgene.wu@arm.com /** 8477646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8487646Sgene.wu@arm.com */ 8497646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8507646Sgene.wu@arm.com { 8517646Sgene.wu@arm.com public: 8527646Sgene.wu@arm.com 8537646Sgene.wu@arm.com /// Constructor. 8547646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8557646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 8567646Sgene.wu@arm.com uint32_t _base, bool _add, 8577646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8587646Sgene.wu@arm.com uint32_t _index); 8597646Sgene.wu@arm.com 8607646Sgene.wu@arm.com %(BasicExecDeclare)s 8617646Sgene.wu@arm.com 8627646Sgene.wu@arm.com %(InitiateAccDeclare)s 8637646Sgene.wu@arm.com 8647646Sgene.wu@arm.com %(CompleteAccDeclare)s 8657646Sgene.wu@arm.com }; 8667646Sgene.wu@arm.com}}; 8677646Sgene.wu@arm.com 8687646Sgene.wu@arm.comdef template LoadRegDeclare {{ 8697646Sgene.wu@arm.com /** 8707646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8717646Sgene.wu@arm.com */ 8727646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8737646Sgene.wu@arm.com { 8747646Sgene.wu@arm.com public: 8757646Sgene.wu@arm.com 8767646Sgene.wu@arm.com /// Constructor. 8777646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8787646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 8797646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8807646Sgene.wu@arm.com uint32_t _index); 8817646Sgene.wu@arm.com 8827646Sgene.wu@arm.com %(BasicExecDeclare)s 8837646Sgene.wu@arm.com 8847646Sgene.wu@arm.com %(InitiateAccDeclare)s 8857646Sgene.wu@arm.com 8867646Sgene.wu@arm.com %(CompleteAccDeclare)s 8877646Sgene.wu@arm.com }; 8887646Sgene.wu@arm.com}}; 8897646Sgene.wu@arm.com 8907646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8917646Sgene.wu@arm.com /** 8927646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8937646Sgene.wu@arm.com */ 8947646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8957646Sgene.wu@arm.com { 8967646Sgene.wu@arm.com public: 8977646Sgene.wu@arm.com 8987646Sgene.wu@arm.com /// Constructor. 8997646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 9007646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 9017646Sgene.wu@arm.com 9027646Sgene.wu@arm.com %(BasicExecDeclare)s 9037646Sgene.wu@arm.com 9047646Sgene.wu@arm.com %(InitiateAccDeclare)s 9057646Sgene.wu@arm.com 9067646Sgene.wu@arm.com %(CompleteAccDeclare)s 9077646Sgene.wu@arm.com }; 9087646Sgene.wu@arm.com}}; 9097646Sgene.wu@arm.com 9107119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 9117119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 9127119Sgblack@eecs.umich.edu}}; 9137119Sgblack@eecs.umich.edu 9147119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 9157119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 9167119Sgblack@eecs.umich.edu}}; 9177119Sgblack@eecs.umich.edu 9187291Sgblack@eecs.umich.edudef template RfeConstructor {{ 9197291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9207291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 9217291Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9227291Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 9237291Sgblack@eecs.umich.edu { 9247291Sgblack@eecs.umich.edu %(constructor)s; 9257848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9267848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9277848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9287848SAli.Saidi@ARM.com } 9297848SAli.Saidi@ARM.com } 9307646Sgene.wu@arm.com#if %(use_uops)d 9317646Sgene.wu@arm.com assert(numMicroops >= 2); 9327646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9337646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); 9347724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9357646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9367646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9377646Sgene.wu@arm.com#endif 9387291Sgblack@eecs.umich.edu } 9397291Sgblack@eecs.umich.edu}}; 9407291Sgblack@eecs.umich.edu 9417312Sgblack@eecs.umich.edudef template SrsConstructor {{ 9427312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9437312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 9447312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9457312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 9467312Sgblack@eecs.umich.edu { 9477312Sgblack@eecs.umich.edu %(constructor)s; 9487848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9497848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9507848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9517848SAli.Saidi@ARM.com } 9527848SAli.Saidi@ARM.com } 9537646Sgene.wu@arm.com#if %(use_uops)d 9547646Sgene.wu@arm.com assert(numMicroops >= 2); 9557646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9567646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9577724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9587646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9597646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9607646Sgene.wu@arm.com#endif 9617312Sgblack@eecs.umich.edu } 9627312Sgblack@eecs.umich.edu}}; 9637312Sgblack@eecs.umich.edu 9647205Sgblack@eecs.umich.edudef template SwapConstructor {{ 9657205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9667205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9677205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9687205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9697205Sgblack@eecs.umich.edu { 9707205Sgblack@eecs.umich.edu %(constructor)s; 9717848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9727848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9737848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9747848SAli.Saidi@ARM.com } 9757848SAli.Saidi@ARM.com } 9767205Sgblack@eecs.umich.edu } 9777205Sgblack@eecs.umich.edu}}; 9787205Sgblack@eecs.umich.edu 9797279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 9807279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9817279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9827279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9837279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9847279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9857279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9867279Sgblack@eecs.umich.edu { 9877279Sgblack@eecs.umich.edu %(constructor)s; 9887848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9897848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9907848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9917848SAli.Saidi@ARM.com } 9927848SAli.Saidi@ARM.com } 9937646Sgene.wu@arm.com#if %(use_uops)d 9947646Sgene.wu@arm.com assert(numMicroops >= 2); 9957646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9967646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 9977724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9987646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9997646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10007646Sgene.wu@arm.com#endif 10017279Sgblack@eecs.umich.edu } 10027279Sgblack@eecs.umich.edu}}; 10037279Sgblack@eecs.umich.edu 10047303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 10057303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10067303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 10077303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 10087303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10097303Sgblack@eecs.umich.edu (IntRegIndex)_result, 10107303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10117303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10127303Sgblack@eecs.umich.edu { 10137303Sgblack@eecs.umich.edu %(constructor)s; 10147848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10157848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10167848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10177848SAli.Saidi@ARM.com } 10187848SAli.Saidi@ARM.com } 10197646Sgene.wu@arm.com#if %(use_uops)d 10207646Sgene.wu@arm.com assert(numMicroops >= 2); 10217646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10227646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 10237646Sgene.wu@arm.com _base, _add, _imm); 10247724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10257646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10267646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10277646Sgene.wu@arm.com#endif 10287303Sgblack@eecs.umich.edu } 10297303Sgblack@eecs.umich.edu}}; 10307303Sgblack@eecs.umich.edu 10317119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 10327119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10337119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 10347119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10357119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 10367119Sgblack@eecs.umich.edu { 10377119Sgblack@eecs.umich.edu %(constructor)s; 10387848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10397848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10407848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10417848SAli.Saidi@ARM.com } 10427848SAli.Saidi@ARM.com } 10437646Sgene.wu@arm.com#if %(use_uops)d 10447646Sgene.wu@arm.com assert(numMicroops >= 2); 10457646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10467646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 10477724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10487646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10497646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10507646Sgene.wu@arm.com#endif 10517119Sgblack@eecs.umich.edu } 10527119Sgblack@eecs.umich.edu}}; 10537119Sgblack@eecs.umich.edu 10547303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 10557303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10567303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10577303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10587303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10597303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10607303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10617303Sgblack@eecs.umich.edu { 10627303Sgblack@eecs.umich.edu %(constructor)s; 10637848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10647848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10657848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10667848SAli.Saidi@ARM.com } 10677848SAli.Saidi@ARM.com } 10687646Sgene.wu@arm.com#if %(use_uops)d 10697646Sgene.wu@arm.com assert(numMicroops >= 2); 10707646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10717646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10727646Sgene.wu@arm.com _base, _add, _imm); 10737724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 10747646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10757646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10767646Sgene.wu@arm.com#endif 10777303Sgblack@eecs.umich.edu } 10787303Sgblack@eecs.umich.edu}}; 10797303Sgblack@eecs.umich.edu 10807646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 10817279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10827279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10837279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10847279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10857279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10867279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10877279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10887279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10897279Sgblack@eecs.umich.edu { 10907279Sgblack@eecs.umich.edu %(constructor)s; 10917848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10927848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10937848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10947848SAli.Saidi@ARM.com } 10957848SAli.Saidi@ARM.com } 10967646Sgene.wu@arm.com#if %(use_uops)d 10977646Sgene.wu@arm.com assert(numMicroops >= 2); 10987646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10997646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11007646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11017724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11027646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11037646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11047646Sgene.wu@arm.com#endif 11057279Sgblack@eecs.umich.edu } 11067279Sgblack@eecs.umich.edu}}; 11077279Sgblack@eecs.umich.edu 11087646Sgene.wu@arm.comdef template StoreRegConstructor {{ 11097119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11107119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 11117119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11127119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11137119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11147119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 11157119Sgblack@eecs.umich.edu (IntRegIndex)_index) 11167119Sgblack@eecs.umich.edu { 11177119Sgblack@eecs.umich.edu %(constructor)s; 11187848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11197848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11207848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11217848SAli.Saidi@ARM.com } 11227848SAli.Saidi@ARM.com } 11237646Sgene.wu@arm.com#if %(use_uops)d 11247646Sgene.wu@arm.com assert(numMicroops >= 2); 11257646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11267646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11277646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11287724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11297646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11307646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11317646Sgene.wu@arm.com#endif 11327119Sgblack@eecs.umich.edu } 11337119Sgblack@eecs.umich.edu}}; 11347646Sgene.wu@arm.com 11357646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 11367646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11377646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 11387646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11397646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11407646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 11417646Sgene.wu@arm.com (IntRegIndex)_base, _add, 11427646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11437646Sgene.wu@arm.com (IntRegIndex)_index) 11447646Sgene.wu@arm.com { 11457646Sgene.wu@arm.com %(constructor)s; 11467848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11477848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11487848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11497848SAli.Saidi@ARM.com } 11507848SAli.Saidi@ARM.com } 11517646Sgene.wu@arm.com#if %(use_uops)d 11527646Sgene.wu@arm.com assert(numMicroops >= 2); 11537646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11547646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 11557646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11567646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11577724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11587646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11597646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11607724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11617646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11627646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11637646Sgene.wu@arm.com } else { 11647646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11657646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11667646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11677724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11687646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11697646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11707646Sgene.wu@arm.com } 11717646Sgene.wu@arm.com#endif 11727646Sgene.wu@arm.com } 11737646Sgene.wu@arm.com}}; 11747646Sgene.wu@arm.com 11757646Sgene.wu@arm.comdef template LoadRegConstructor {{ 11767646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11777646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11787646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11797646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11807646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11817646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11827646Sgene.wu@arm.com (IntRegIndex)_index) 11837646Sgene.wu@arm.com { 11847646Sgene.wu@arm.com %(constructor)s; 11857848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11867848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11877848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11887848SAli.Saidi@ARM.com } 11897848SAli.Saidi@ARM.com } 11907646Sgene.wu@arm.com#if %(use_uops)d 11917646Sgene.wu@arm.com assert(numMicroops >= 2); 11927646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11937646Sgene.wu@arm.com if (_dest == INTREG_PC) { 11947646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11957646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11967646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11977724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 11987646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11997724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12007646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12017646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12027646Sgene.wu@arm.com } else if(_dest == _index) { 12037646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 12047646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 12057724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12067646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 12077646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 12087724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12097646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 12107646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12117646Sgene.wu@arm.com } else { 12127646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 12137646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 12147646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 12157724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12167646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12177646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12187646Sgene.wu@arm.com 12197646Sgene.wu@arm.com } 12207646Sgene.wu@arm.com#endif 12217646Sgene.wu@arm.com } 12227646Sgene.wu@arm.com}}; 12237646Sgene.wu@arm.com 12247646Sgene.wu@arm.comdef template LoadImmConstructor {{ 12257646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 12267646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 12277646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 12287646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 12297646Sgene.wu@arm.com { 12307646Sgene.wu@arm.com %(constructor)s; 12317848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 12327848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 12337848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12347848SAli.Saidi@ARM.com } 12357848SAli.Saidi@ARM.com } 12367646Sgene.wu@arm.com#if %(use_uops)d 12377646Sgene.wu@arm.com assert(numMicroops >= 2); 12387646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 12397646Sgene.wu@arm.com if (_dest == INTREG_PC) { 12407646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 12417646Sgene.wu@arm.com _imm); 12427724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12437646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12447724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12457646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12467646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12477646Sgene.wu@arm.com } else { 12487646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12497724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 12507646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12517646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12527646Sgene.wu@arm.com } 12537646Sgene.wu@arm.com#endif 12547646Sgene.wu@arm.com } 12557646Sgene.wu@arm.com}}; 12567646Sgene.wu@arm.com 1257