mem.isa revision 7646
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 457646Sgene.wu@arm.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 547646Sgene.wu@arm.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 637646Sgene.wu@arm.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 647646Sgene.wu@arm.com %(CPU_exec_context)s *xc, 657646Sgene.wu@arm.com Trace::InstRecord *traceData) const 667646Sgene.wu@arm.com { 677646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 687646Sgene.wu@arm.com return NoFault; 697646Sgene.wu@arm.com } 707646Sgene.wu@arm.com}}; 717646Sgene.wu@arm.com 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edudef template SwapExecute {{ 747205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 757205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767205Sgblack@eecs.umich.edu { 777205Sgblack@eecs.umich.edu Addr EA; 787205Sgblack@eecs.umich.edu Fault fault = NoFault; 797205Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu %(op_decl)s; 817205Sgblack@eecs.umich.edu uint64_t memData = 0; 827205Sgblack@eecs.umich.edu %(op_rd)s; 837205Sgblack@eecs.umich.edu %(ea_code)s; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu if (%(predicate_test)s) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu %(preacc_code)s; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu if (fault == NoFault) { 907205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 917205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 927205Sgblack@eecs.umich.edu } 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu %(postacc_code)s; 967205Sgblack@eecs.umich.edu } 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu %(op_wb)s; 1007205Sgblack@eecs.umich.edu } 1017597Sminkyu.jeong@arm.com } else { 1027597Sminkyu.jeong@arm.com xc->setPredicate(false); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 1067646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 1077408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1087408Sgblack@eecs.umich.edu } 1097408Sgblack@eecs.umich.edu 1107205Sgblack@eecs.umich.edu return fault; 1117205Sgblack@eecs.umich.edu } 1127205Sgblack@eecs.umich.edu}}; 1137205Sgblack@eecs.umich.edu 1147205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 1157205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1167205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1177205Sgblack@eecs.umich.edu { 1187205Sgblack@eecs.umich.edu Addr EA; 1197205Sgblack@eecs.umich.edu Fault fault = NoFault; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu %(op_decl)s; 1227205Sgblack@eecs.umich.edu uint64_t memData = 0; 1237205Sgblack@eecs.umich.edu %(op_rd)s; 1247205Sgblack@eecs.umich.edu %(ea_code)s; 1257205Sgblack@eecs.umich.edu 1267205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1277205Sgblack@eecs.umich.edu { 1287205Sgblack@eecs.umich.edu %(preacc_code)s; 1297205Sgblack@eecs.umich.edu 1307205Sgblack@eecs.umich.edu if (fault == NoFault) { 1317205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1327205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1337205Sgblack@eecs.umich.edu } 1347205Sgblack@eecs.umich.edu 1357205Sgblack@eecs.umich.edu if (fault == NoFault) { 1367205Sgblack@eecs.umich.edu %(op_wb)s; 1377205Sgblack@eecs.umich.edu } 1387597Sminkyu.jeong@arm.com } else { 1397597Sminkyu.jeong@arm.com xc->setPredicate(false); 1407205Sgblack@eecs.umich.edu } 1417205Sgblack@eecs.umich.edu 1427646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 1437646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 1447408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1457408Sgblack@eecs.umich.edu } 1467408Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edu return fault; 1487205Sgblack@eecs.umich.edu } 1497205Sgblack@eecs.umich.edu}}; 1507205Sgblack@eecs.umich.edu 1517205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1527205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1537205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1547205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1557205Sgblack@eecs.umich.edu { 1567205Sgblack@eecs.umich.edu Fault fault = NoFault; 1577205Sgblack@eecs.umich.edu 1587205Sgblack@eecs.umich.edu %(op_decl)s; 1597205Sgblack@eecs.umich.edu %(op_rd)s; 1607205Sgblack@eecs.umich.edu 1617205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1627205Sgblack@eecs.umich.edu { 1637205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1647205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1657205Sgblack@eecs.umich.edu 1667205Sgblack@eecs.umich.edu %(postacc_code)s; 1677205Sgblack@eecs.umich.edu 1687205Sgblack@eecs.umich.edu if (fault == NoFault) { 1697205Sgblack@eecs.umich.edu %(op_wb)s; 1707205Sgblack@eecs.umich.edu } 1717205Sgblack@eecs.umich.edu } 1727205Sgblack@eecs.umich.edu 1737408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1747408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1757408Sgblack@eecs.umich.edu } 1767408Sgblack@eecs.umich.edu 1777205Sgblack@eecs.umich.edu return fault; 1787205Sgblack@eecs.umich.edu } 1797205Sgblack@eecs.umich.edu}}; 1807205Sgblack@eecs.umich.edu 1817119Sgblack@eecs.umich.edudef template LoadExecute {{ 1827119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1837119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1847119Sgblack@eecs.umich.edu { 1857119Sgblack@eecs.umich.edu Addr EA; 1867119Sgblack@eecs.umich.edu Fault fault = NoFault; 1877119Sgblack@eecs.umich.edu 1887119Sgblack@eecs.umich.edu %(op_decl)s; 1897119Sgblack@eecs.umich.edu %(op_rd)s; 1907119Sgblack@eecs.umich.edu %(ea_code)s; 1917119Sgblack@eecs.umich.edu 1927119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1937119Sgblack@eecs.umich.edu { 1947119Sgblack@eecs.umich.edu if (fault == NoFault) { 1957119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1967119Sgblack@eecs.umich.edu %(memacc_code)s; 1977119Sgblack@eecs.umich.edu } 1987119Sgblack@eecs.umich.edu 1997119Sgblack@eecs.umich.edu if (fault == NoFault) { 2007119Sgblack@eecs.umich.edu %(op_wb)s; 2017119Sgblack@eecs.umich.edu } 2027597Sminkyu.jeong@arm.com } else { 2037597Sminkyu.jeong@arm.com xc->setPredicate(false); 2047119Sgblack@eecs.umich.edu } 2057119Sgblack@eecs.umich.edu 2067646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2077646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2087408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2097408Sgblack@eecs.umich.edu } 2107408Sgblack@eecs.umich.edu 2117119Sgblack@eecs.umich.edu return fault; 2127119Sgblack@eecs.umich.edu } 2137119Sgblack@eecs.umich.edu}}; 2147119Sgblack@eecs.umich.edu 2157639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 2167639Sgblack@eecs.umich.edu template <class Element> 2177639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2187639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2197639Sgblack@eecs.umich.edu { 2207639Sgblack@eecs.umich.edu Addr EA; 2217639Sgblack@eecs.umich.edu Fault fault = NoFault; 2227639Sgblack@eecs.umich.edu 2237639Sgblack@eecs.umich.edu %(op_decl)s; 2247639Sgblack@eecs.umich.edu %(mem_decl)s; 2257639Sgblack@eecs.umich.edu %(op_rd)s; 2267639Sgblack@eecs.umich.edu %(ea_code)s; 2277639Sgblack@eecs.umich.edu 2287639Sgblack@eecs.umich.edu MemUnion memUnion; 2297639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2307639Sgblack@eecs.umich.edu 2317639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2327639Sgblack@eecs.umich.edu { 2337639Sgblack@eecs.umich.edu if (fault == NoFault) { 2347639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 2357639Sgblack@eecs.umich.edu %(memacc_code)s; 2367639Sgblack@eecs.umich.edu } 2377639Sgblack@eecs.umich.edu 2387639Sgblack@eecs.umich.edu if (fault == NoFault) { 2397639Sgblack@eecs.umich.edu %(op_wb)s; 2407639Sgblack@eecs.umich.edu } 2417639Sgblack@eecs.umich.edu } 2427639Sgblack@eecs.umich.edu 2437646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2447646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2457639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2467639Sgblack@eecs.umich.edu } 2477639Sgblack@eecs.umich.edu 2487639Sgblack@eecs.umich.edu return fault; 2497639Sgblack@eecs.umich.edu } 2507639Sgblack@eecs.umich.edu}}; 2517639Sgblack@eecs.umich.edu 2527120Sgblack@eecs.umich.edudef template StoreExecute {{ 2537120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2547120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2557120Sgblack@eecs.umich.edu { 2567120Sgblack@eecs.umich.edu Addr EA; 2577120Sgblack@eecs.umich.edu Fault fault = NoFault; 2587120Sgblack@eecs.umich.edu 2597120Sgblack@eecs.umich.edu %(op_decl)s; 2607120Sgblack@eecs.umich.edu %(op_rd)s; 2617120Sgblack@eecs.umich.edu %(ea_code)s; 2627120Sgblack@eecs.umich.edu 2637120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2647120Sgblack@eecs.umich.edu { 2657120Sgblack@eecs.umich.edu if (fault == NoFault) { 2667120Sgblack@eecs.umich.edu %(memacc_code)s; 2677120Sgblack@eecs.umich.edu } 2687120Sgblack@eecs.umich.edu 2697120Sgblack@eecs.umich.edu if (fault == NoFault) { 2707120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2717120Sgblack@eecs.umich.edu memAccessFlags, NULL); 2727120Sgblack@eecs.umich.edu } 2737120Sgblack@eecs.umich.edu 2747120Sgblack@eecs.umich.edu if (fault == NoFault) { 2757120Sgblack@eecs.umich.edu %(op_wb)s; 2767120Sgblack@eecs.umich.edu } 2777597Sminkyu.jeong@arm.com } else { 2787597Sminkyu.jeong@arm.com xc->setPredicate(false); 2797120Sgblack@eecs.umich.edu } 2807120Sgblack@eecs.umich.edu 2817646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 2827646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 2837408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2847408Sgblack@eecs.umich.edu } 2857408Sgblack@eecs.umich.edu 2867120Sgblack@eecs.umich.edu return fault; 2877120Sgblack@eecs.umich.edu } 2887120Sgblack@eecs.umich.edu}}; 2897120Sgblack@eecs.umich.edu 2907639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2917639Sgblack@eecs.umich.edu template <class Element> 2927639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2937639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 2947639Sgblack@eecs.umich.edu { 2957639Sgblack@eecs.umich.edu Addr EA; 2967639Sgblack@eecs.umich.edu Fault fault = NoFault; 2977639Sgblack@eecs.umich.edu 2987639Sgblack@eecs.umich.edu %(op_decl)s; 2997639Sgblack@eecs.umich.edu %(mem_decl)s; 3007639Sgblack@eecs.umich.edu %(op_rd)s; 3017639Sgblack@eecs.umich.edu %(ea_code)s; 3027639Sgblack@eecs.umich.edu 3037639Sgblack@eecs.umich.edu MemUnion memUnion; 3047639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 3057639Sgblack@eecs.umich.edu 3067639Sgblack@eecs.umich.edu if (%(predicate_test)s) 3077639Sgblack@eecs.umich.edu { 3087639Sgblack@eecs.umich.edu if (fault == NoFault) { 3097639Sgblack@eecs.umich.edu %(memacc_code)s; 3107639Sgblack@eecs.umich.edu } 3117639Sgblack@eecs.umich.edu 3127639Sgblack@eecs.umich.edu if (fault == NoFault) { 3137639Sgblack@eecs.umich.edu fault = xc->writeBytes(dataPtr, %(size)d, EA, 3147639Sgblack@eecs.umich.edu memAccessFlags, NULL); 3157639Sgblack@eecs.umich.edu } 3167639Sgblack@eecs.umich.edu 3177639Sgblack@eecs.umich.edu if (fault == NoFault) { 3187639Sgblack@eecs.umich.edu %(op_wb)s; 3197639Sgblack@eecs.umich.edu } 3207639Sgblack@eecs.umich.edu } 3217639Sgblack@eecs.umich.edu 3227646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3237646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3247639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3257639Sgblack@eecs.umich.edu } 3267639Sgblack@eecs.umich.edu 3277639Sgblack@eecs.umich.edu return fault; 3287639Sgblack@eecs.umich.edu } 3297639Sgblack@eecs.umich.edu}}; 3307639Sgblack@eecs.umich.edu 3317303Sgblack@eecs.umich.edudef template StoreExExecute {{ 3327303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3337303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3347303Sgblack@eecs.umich.edu { 3357303Sgblack@eecs.umich.edu Addr EA; 3367303Sgblack@eecs.umich.edu Fault fault = NoFault; 3377303Sgblack@eecs.umich.edu 3387303Sgblack@eecs.umich.edu %(op_decl)s; 3397303Sgblack@eecs.umich.edu %(op_rd)s; 3407303Sgblack@eecs.umich.edu %(ea_code)s; 3417303Sgblack@eecs.umich.edu 3427303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3437303Sgblack@eecs.umich.edu { 3447303Sgblack@eecs.umich.edu if (fault == NoFault) { 3457303Sgblack@eecs.umich.edu %(memacc_code)s; 3467303Sgblack@eecs.umich.edu } 3477303Sgblack@eecs.umich.edu 3487303Sgblack@eecs.umich.edu uint64_t writeResult; 3497303Sgblack@eecs.umich.edu 3507303Sgblack@eecs.umich.edu if (fault == NoFault) { 3517303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3527303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 3537303Sgblack@eecs.umich.edu } 3547303Sgblack@eecs.umich.edu 3557303Sgblack@eecs.umich.edu if (fault == NoFault) { 3567303Sgblack@eecs.umich.edu %(postacc_code)s; 3577303Sgblack@eecs.umich.edu } 3587303Sgblack@eecs.umich.edu 3597303Sgblack@eecs.umich.edu if (fault == NoFault) { 3607303Sgblack@eecs.umich.edu %(op_wb)s; 3617303Sgblack@eecs.umich.edu } 3627597Sminkyu.jeong@arm.com } else { 3637597Sminkyu.jeong@arm.com xc->setPredicate(false); 3647303Sgblack@eecs.umich.edu } 3657303Sgblack@eecs.umich.edu 3667646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 3677646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 3687408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3697408Sgblack@eecs.umich.edu } 3707408Sgblack@eecs.umich.edu 3717303Sgblack@eecs.umich.edu return fault; 3727303Sgblack@eecs.umich.edu } 3737303Sgblack@eecs.umich.edu}}; 3747303Sgblack@eecs.umich.edu 3757303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3767303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3777303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3787303Sgblack@eecs.umich.edu { 3797303Sgblack@eecs.umich.edu Addr EA; 3807303Sgblack@eecs.umich.edu Fault fault = NoFault; 3817303Sgblack@eecs.umich.edu 3827303Sgblack@eecs.umich.edu %(op_decl)s; 3837303Sgblack@eecs.umich.edu %(op_rd)s; 3847303Sgblack@eecs.umich.edu %(ea_code)s; 3857303Sgblack@eecs.umich.edu 3867303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3877303Sgblack@eecs.umich.edu { 3887303Sgblack@eecs.umich.edu if (fault == NoFault) { 3897303Sgblack@eecs.umich.edu %(memacc_code)s; 3907303Sgblack@eecs.umich.edu } 3917303Sgblack@eecs.umich.edu 3927303Sgblack@eecs.umich.edu if (fault == NoFault) { 3937303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3947303Sgblack@eecs.umich.edu memAccessFlags, NULL); 3957303Sgblack@eecs.umich.edu } 3967303Sgblack@eecs.umich.edu 3977303Sgblack@eecs.umich.edu // Need to write back any potential address register update 3987303Sgblack@eecs.umich.edu if (fault == NoFault) { 3997303Sgblack@eecs.umich.edu %(op_wb)s; 4007303Sgblack@eecs.umich.edu } 4017597Sminkyu.jeong@arm.com } else { 4027597Sminkyu.jeong@arm.com xc->setPredicate(false); 4037303Sgblack@eecs.umich.edu } 4047646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4057646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4067408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4077408Sgblack@eecs.umich.edu } 4087408Sgblack@eecs.umich.edu 4097303Sgblack@eecs.umich.edu return fault; 4107303Sgblack@eecs.umich.edu } 4117303Sgblack@eecs.umich.edu}}; 4127303Sgblack@eecs.umich.edu 4137120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 4147120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4157120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4167120Sgblack@eecs.umich.edu { 4177120Sgblack@eecs.umich.edu Addr EA; 4187120Sgblack@eecs.umich.edu Fault fault = NoFault; 4197120Sgblack@eecs.umich.edu 4207120Sgblack@eecs.umich.edu %(op_decl)s; 4217120Sgblack@eecs.umich.edu %(op_rd)s; 4227120Sgblack@eecs.umich.edu %(ea_code)s; 4237120Sgblack@eecs.umich.edu 4247120Sgblack@eecs.umich.edu if (%(predicate_test)s) 4257120Sgblack@eecs.umich.edu { 4267120Sgblack@eecs.umich.edu if (fault == NoFault) { 4277120Sgblack@eecs.umich.edu %(memacc_code)s; 4287120Sgblack@eecs.umich.edu } 4297120Sgblack@eecs.umich.edu 4307120Sgblack@eecs.umich.edu if (fault == NoFault) { 4317120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 4327120Sgblack@eecs.umich.edu memAccessFlags, NULL); 4337120Sgblack@eecs.umich.edu } 4347120Sgblack@eecs.umich.edu 4357120Sgblack@eecs.umich.edu // Need to write back any potential address register update 4367120Sgblack@eecs.umich.edu if (fault == NoFault) { 4377120Sgblack@eecs.umich.edu %(op_wb)s; 4387120Sgblack@eecs.umich.edu } 4397597Sminkyu.jeong@arm.com } else { 4407597Sminkyu.jeong@arm.com xc->setPredicate(false); 4417120Sgblack@eecs.umich.edu } 4427120Sgblack@eecs.umich.edu 4437646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4447646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4457408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4467408Sgblack@eecs.umich.edu } 4477408Sgblack@eecs.umich.edu 4487120Sgblack@eecs.umich.edu return fault; 4497120Sgblack@eecs.umich.edu } 4507120Sgblack@eecs.umich.edu}}; 4517120Sgblack@eecs.umich.edu 4527639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 4537639Sgblack@eecs.umich.edu template <class Element> 4547639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4557639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 4567639Sgblack@eecs.umich.edu { 4577639Sgblack@eecs.umich.edu Addr EA; 4587639Sgblack@eecs.umich.edu Fault fault = NoFault; 4597639Sgblack@eecs.umich.edu 4607639Sgblack@eecs.umich.edu %(op_decl)s; 4617639Sgblack@eecs.umich.edu %(mem_decl)s; 4627639Sgblack@eecs.umich.edu %(op_rd)s; 4637639Sgblack@eecs.umich.edu %(ea_code)s; 4647639Sgblack@eecs.umich.edu 4657639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4667639Sgblack@eecs.umich.edu { 4677639Sgblack@eecs.umich.edu MemUnion memUnion; 4687639Sgblack@eecs.umich.edu if (fault == NoFault) { 4697639Sgblack@eecs.umich.edu %(memacc_code)s; 4707639Sgblack@eecs.umich.edu } 4717639Sgblack@eecs.umich.edu 4727639Sgblack@eecs.umich.edu if (fault == NoFault) { 4737639Sgblack@eecs.umich.edu fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 4747639Sgblack@eecs.umich.edu memAccessFlags, NULL); 4757639Sgblack@eecs.umich.edu } 4767639Sgblack@eecs.umich.edu 4777639Sgblack@eecs.umich.edu // Need to write back any potential address register update 4787639Sgblack@eecs.umich.edu if (fault == NoFault) { 4797639Sgblack@eecs.umich.edu %(op_wb)s; 4807639Sgblack@eecs.umich.edu } 4817639Sgblack@eecs.umich.edu } 4827639Sgblack@eecs.umich.edu 4837646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 4847646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 4857639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4867639Sgblack@eecs.umich.edu } 4877639Sgblack@eecs.umich.edu 4887639Sgblack@eecs.umich.edu return fault; 4897639Sgblack@eecs.umich.edu } 4907639Sgblack@eecs.umich.edu}}; 4917639Sgblack@eecs.umich.edu 4927119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4937119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4947119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4957119Sgblack@eecs.umich.edu { 4967119Sgblack@eecs.umich.edu Addr EA; 4977119Sgblack@eecs.umich.edu Fault fault = NoFault; 4987119Sgblack@eecs.umich.edu 4997119Sgblack@eecs.umich.edu %(op_src_decl)s; 5007119Sgblack@eecs.umich.edu %(op_rd)s; 5017119Sgblack@eecs.umich.edu %(ea_code)s; 5027119Sgblack@eecs.umich.edu 5037119Sgblack@eecs.umich.edu if (%(predicate_test)s) 5047119Sgblack@eecs.umich.edu { 5057119Sgblack@eecs.umich.edu if (fault == NoFault) { 5067119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 5077119Sgblack@eecs.umich.edu } 5087597Sminkyu.jeong@arm.com } else { 5097597Sminkyu.jeong@arm.com xc->setPredicate(false); 5107646Sgene.wu@arm.com if (fault == NoFault && machInst.itstateMask != 0 && 5117646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 5127597Sminkyu.jeong@arm.com xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5137597Sminkyu.jeong@arm.com } 5147119Sgblack@eecs.umich.edu } 5157119Sgblack@eecs.umich.edu 5167119Sgblack@eecs.umich.edu return fault; 5177119Sgblack@eecs.umich.edu } 5187119Sgblack@eecs.umich.edu}}; 5197119Sgblack@eecs.umich.edu 5207639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 5217639Sgblack@eecs.umich.edu template <class Element> 5227639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 5237639Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 5247639Sgblack@eecs.umich.edu { 5257639Sgblack@eecs.umich.edu Addr EA; 5267639Sgblack@eecs.umich.edu Fault fault = NoFault; 5277639Sgblack@eecs.umich.edu 5287639Sgblack@eecs.umich.edu %(op_src_decl)s; 5297639Sgblack@eecs.umich.edu %(op_rd)s; 5307639Sgblack@eecs.umich.edu %(ea_code)s; 5317639Sgblack@eecs.umich.edu 5327639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5337639Sgblack@eecs.umich.edu { 5347639Sgblack@eecs.umich.edu if (fault == NoFault) { 5357639Sgblack@eecs.umich.edu fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 5367639Sgblack@eecs.umich.edu } 5377646Sgene.wu@arm.com } else if (fault == NoFault && machInst.itstateMask != 0 && 5387646Sgene.wu@arm.com (!isMicroop() || isLastMicroop())) { 5397639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5407639Sgblack@eecs.umich.edu } 5417639Sgblack@eecs.umich.edu 5427639Sgblack@eecs.umich.edu return fault; 5437639Sgblack@eecs.umich.edu } 5447639Sgblack@eecs.umich.edu}}; 5457639Sgblack@eecs.umich.edu 5467119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 5477119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5487119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 5497119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5507119Sgblack@eecs.umich.edu { 5517119Sgblack@eecs.umich.edu Fault fault = NoFault; 5527119Sgblack@eecs.umich.edu 5537119Sgblack@eecs.umich.edu %(op_decl)s; 5547119Sgblack@eecs.umich.edu %(op_rd)s; 5557119Sgblack@eecs.umich.edu 5567119Sgblack@eecs.umich.edu if (%(predicate_test)s) 5577119Sgblack@eecs.umich.edu { 5587119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5597119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 5607119Sgblack@eecs.umich.edu 5617119Sgblack@eecs.umich.edu if (fault == NoFault) { 5627119Sgblack@eecs.umich.edu %(memacc_code)s; 5637119Sgblack@eecs.umich.edu } 5647119Sgblack@eecs.umich.edu 5657119Sgblack@eecs.umich.edu if (fault == NoFault) { 5667119Sgblack@eecs.umich.edu %(op_wb)s; 5677119Sgblack@eecs.umich.edu } 5687119Sgblack@eecs.umich.edu } 5697119Sgblack@eecs.umich.edu 5707408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 5717408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 5727408Sgblack@eecs.umich.edu } 5737408Sgblack@eecs.umich.edu 5747119Sgblack@eecs.umich.edu return fault; 5757119Sgblack@eecs.umich.edu } 5767119Sgblack@eecs.umich.edu}}; 5777119Sgblack@eecs.umich.edu 5787639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5797639Sgblack@eecs.umich.edu template <class Element> 5807639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5817639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 5827639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5837639Sgblack@eecs.umich.edu { 5847639Sgblack@eecs.umich.edu Fault fault = NoFault; 5857639Sgblack@eecs.umich.edu 5867639Sgblack@eecs.umich.edu %(mem_decl)s; 5877639Sgblack@eecs.umich.edu %(op_decl)s; 5887639Sgblack@eecs.umich.edu %(op_rd)s; 5897639Sgblack@eecs.umich.edu 5907639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5917639Sgblack@eecs.umich.edu { 5927639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5937639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5947639Sgblack@eecs.umich.edu 5957639Sgblack@eecs.umich.edu if (fault == NoFault) { 5967639Sgblack@eecs.umich.edu %(memacc_code)s; 5977639Sgblack@eecs.umich.edu } 5987639Sgblack@eecs.umich.edu 5997639Sgblack@eecs.umich.edu if (fault == NoFault) { 6007639Sgblack@eecs.umich.edu %(op_wb)s; 6017639Sgblack@eecs.umich.edu } 6027639Sgblack@eecs.umich.edu } 6037639Sgblack@eecs.umich.edu 6047639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6057639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6067639Sgblack@eecs.umich.edu } 6077639Sgblack@eecs.umich.edu 6087639Sgblack@eecs.umich.edu return fault; 6097639Sgblack@eecs.umich.edu } 6107639Sgblack@eecs.umich.edu}}; 6117639Sgblack@eecs.umich.edu 6127120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 6137120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6147120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 6157120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6167120Sgblack@eecs.umich.edu { 6177120Sgblack@eecs.umich.edu Fault fault = NoFault; 6187120Sgblack@eecs.umich.edu 6197120Sgblack@eecs.umich.edu %(op_decl)s; 6207120Sgblack@eecs.umich.edu %(op_rd)s; 6217120Sgblack@eecs.umich.edu 6227120Sgblack@eecs.umich.edu if (%(predicate_test)s) 6237120Sgblack@eecs.umich.edu { 6247120Sgblack@eecs.umich.edu if (fault == NoFault) { 6257120Sgblack@eecs.umich.edu %(op_wb)s; 6267120Sgblack@eecs.umich.edu } 6277120Sgblack@eecs.umich.edu } 6287120Sgblack@eecs.umich.edu 6297408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6307408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6317408Sgblack@eecs.umich.edu } 6327408Sgblack@eecs.umich.edu 6337120Sgblack@eecs.umich.edu return fault; 6347120Sgblack@eecs.umich.edu } 6357120Sgblack@eecs.umich.edu}}; 6367120Sgblack@eecs.umich.edu 6377639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 6387639Sgblack@eecs.umich.edu template <class Element> 6397639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 6407639Sgblack@eecs.umich.edu PacketPtr pkt, %(CPU_exec_context)s *xc, 6417639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6427639Sgblack@eecs.umich.edu { 6437639Sgblack@eecs.umich.edu Fault fault = NoFault; 6447639Sgblack@eecs.umich.edu 6457639Sgblack@eecs.umich.edu %(op_decl)s; 6467639Sgblack@eecs.umich.edu %(op_rd)s; 6477639Sgblack@eecs.umich.edu 6487639Sgblack@eecs.umich.edu if (%(predicate_test)s) 6497639Sgblack@eecs.umich.edu { 6507639Sgblack@eecs.umich.edu if (fault == NoFault) { 6517639Sgblack@eecs.umich.edu %(op_wb)s; 6527639Sgblack@eecs.umich.edu } 6537639Sgblack@eecs.umich.edu } 6547639Sgblack@eecs.umich.edu 6557639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6567639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6577639Sgblack@eecs.umich.edu } 6587639Sgblack@eecs.umich.edu 6597639Sgblack@eecs.umich.edu return fault; 6607639Sgblack@eecs.umich.edu } 6617639Sgblack@eecs.umich.edu}}; 6627639Sgblack@eecs.umich.edu 6637303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 6647303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 6657303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 6667303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 6677303Sgblack@eecs.umich.edu { 6687303Sgblack@eecs.umich.edu Fault fault = NoFault; 6697303Sgblack@eecs.umich.edu 6707303Sgblack@eecs.umich.edu %(op_decl)s; 6717303Sgblack@eecs.umich.edu %(op_rd)s; 6727303Sgblack@eecs.umich.edu 6737303Sgblack@eecs.umich.edu if (%(predicate_test)s) 6747303Sgblack@eecs.umich.edu { 6757303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 6767303Sgblack@eecs.umich.edu %(postacc_code)s; 6777303Sgblack@eecs.umich.edu 6787303Sgblack@eecs.umich.edu if (fault == NoFault) { 6797303Sgblack@eecs.umich.edu %(op_wb)s; 6807303Sgblack@eecs.umich.edu } 6817303Sgblack@eecs.umich.edu } 6827303Sgblack@eecs.umich.edu 6837408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 6847408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 6857408Sgblack@eecs.umich.edu } 6867408Sgblack@eecs.umich.edu 6877303Sgblack@eecs.umich.edu return fault; 6887303Sgblack@eecs.umich.edu } 6897303Sgblack@eecs.umich.edu}}; 6907303Sgblack@eecs.umich.edu 6917291Sgblack@eecs.umich.edudef template RfeDeclare {{ 6927291Sgblack@eecs.umich.edu /** 6937291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6947291Sgblack@eecs.umich.edu */ 6957291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6967291Sgblack@eecs.umich.edu { 6977291Sgblack@eecs.umich.edu public: 6987291Sgblack@eecs.umich.edu 6997291Sgblack@eecs.umich.edu /// Constructor. 7007291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7017291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 7027291Sgblack@eecs.umich.edu 7037291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7047291Sgblack@eecs.umich.edu 7057291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7067291Sgblack@eecs.umich.edu 7077291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7087291Sgblack@eecs.umich.edu }; 7097291Sgblack@eecs.umich.edu}}; 7107291Sgblack@eecs.umich.edu 7117312Sgblack@eecs.umich.edudef template SrsDeclare {{ 7127312Sgblack@eecs.umich.edu /** 7137312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7147312Sgblack@eecs.umich.edu */ 7157312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7167312Sgblack@eecs.umich.edu { 7177312Sgblack@eecs.umich.edu public: 7187312Sgblack@eecs.umich.edu 7197312Sgblack@eecs.umich.edu /// Constructor. 7207312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7217312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 7227312Sgblack@eecs.umich.edu 7237312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7247312Sgblack@eecs.umich.edu 7257312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7267312Sgblack@eecs.umich.edu 7277312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7287312Sgblack@eecs.umich.edu }; 7297312Sgblack@eecs.umich.edu}}; 7307312Sgblack@eecs.umich.edu 7317205Sgblack@eecs.umich.edudef template SwapDeclare {{ 7327205Sgblack@eecs.umich.edu /** 7337205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7347205Sgblack@eecs.umich.edu */ 7357205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7367205Sgblack@eecs.umich.edu { 7377205Sgblack@eecs.umich.edu public: 7387205Sgblack@eecs.umich.edu 7397205Sgblack@eecs.umich.edu /// Constructor. 7407205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7417205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 7427205Sgblack@eecs.umich.edu 7437205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7447205Sgblack@eecs.umich.edu 7457205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7467205Sgblack@eecs.umich.edu 7477205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7487205Sgblack@eecs.umich.edu }; 7497205Sgblack@eecs.umich.edu}}; 7507205Sgblack@eecs.umich.edu 7517279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 7527279Sgblack@eecs.umich.edu /** 7537279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7547279Sgblack@eecs.umich.edu */ 7557279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7567279Sgblack@eecs.umich.edu { 7577279Sgblack@eecs.umich.edu public: 7587279Sgblack@eecs.umich.edu 7597279Sgblack@eecs.umich.edu /// Constructor. 7607279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7617279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7627279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7637279Sgblack@eecs.umich.edu 7647279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7657279Sgblack@eecs.umich.edu 7667279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7677279Sgblack@eecs.umich.edu 7687279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7697279Sgblack@eecs.umich.edu }; 7707279Sgblack@eecs.umich.edu}}; 7717279Sgblack@eecs.umich.edu 7727303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 7737303Sgblack@eecs.umich.edu /** 7747303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7757303Sgblack@eecs.umich.edu */ 7767303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7777303Sgblack@eecs.umich.edu { 7787303Sgblack@eecs.umich.edu public: 7797303Sgblack@eecs.umich.edu 7807303Sgblack@eecs.umich.edu /// Constructor. 7817303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7827303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 7837303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 7847303Sgblack@eecs.umich.edu 7857303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7867303Sgblack@eecs.umich.edu 7877303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7887303Sgblack@eecs.umich.edu 7897303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7907303Sgblack@eecs.umich.edu }; 7917303Sgblack@eecs.umich.edu}}; 7927303Sgblack@eecs.umich.edu 7937119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 7947119Sgblack@eecs.umich.edu /** 7957119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7967119Sgblack@eecs.umich.edu */ 7977119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7987119Sgblack@eecs.umich.edu { 7997119Sgblack@eecs.umich.edu public: 8007119Sgblack@eecs.umich.edu 8017119Sgblack@eecs.umich.edu /// Constructor. 8027119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8037119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8047119Sgblack@eecs.umich.edu 8057119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8067119Sgblack@eecs.umich.edu 8077119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8087119Sgblack@eecs.umich.edu 8097119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8107119Sgblack@eecs.umich.edu }; 8117119Sgblack@eecs.umich.edu}}; 8127119Sgblack@eecs.umich.edu 8137303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 8147303Sgblack@eecs.umich.edu /** 8157303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8167303Sgblack@eecs.umich.edu */ 8177303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8187303Sgblack@eecs.umich.edu { 8197303Sgblack@eecs.umich.edu public: 8207303Sgblack@eecs.umich.edu 8217303Sgblack@eecs.umich.edu /// Constructor. 8227303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8237303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 8247303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 8257303Sgblack@eecs.umich.edu 8267303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8277303Sgblack@eecs.umich.edu 8287303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8297303Sgblack@eecs.umich.edu 8307303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8317303Sgblack@eecs.umich.edu }; 8327303Sgblack@eecs.umich.edu}}; 8337303Sgblack@eecs.umich.edu 8347646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 8357279Sgblack@eecs.umich.edu /** 8367279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8377279Sgblack@eecs.umich.edu */ 8387279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8397279Sgblack@eecs.umich.edu { 8407279Sgblack@eecs.umich.edu public: 8417279Sgblack@eecs.umich.edu 8427279Sgblack@eecs.umich.edu /// Constructor. 8437279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8447279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 8457279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 8467279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8477279Sgblack@eecs.umich.edu uint32_t _index); 8487279Sgblack@eecs.umich.edu 8497279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8507279Sgblack@eecs.umich.edu 8517279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8527279Sgblack@eecs.umich.edu 8537279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8547279Sgblack@eecs.umich.edu }; 8557279Sgblack@eecs.umich.edu}}; 8567279Sgblack@eecs.umich.edu 8577646Sgene.wu@arm.comdef template StoreRegDeclare {{ 8587119Sgblack@eecs.umich.edu /** 8597119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8607119Sgblack@eecs.umich.edu */ 8617119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8627119Sgblack@eecs.umich.edu { 8637119Sgblack@eecs.umich.edu public: 8647119Sgblack@eecs.umich.edu 8657119Sgblack@eecs.umich.edu /// Constructor. 8667119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8677119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 8687119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8697119Sgblack@eecs.umich.edu uint32_t _index); 8707119Sgblack@eecs.umich.edu 8717119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8727119Sgblack@eecs.umich.edu 8737119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8747119Sgblack@eecs.umich.edu 8757119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8767119Sgblack@eecs.umich.edu }; 8777119Sgblack@eecs.umich.edu}}; 8787119Sgblack@eecs.umich.edu 8797646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 8807646Sgene.wu@arm.com /** 8817646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8827646Sgene.wu@arm.com */ 8837646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8847646Sgene.wu@arm.com { 8857646Sgene.wu@arm.com public: 8867646Sgene.wu@arm.com 8877646Sgene.wu@arm.com /// Constructor. 8887646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8897646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 8907646Sgene.wu@arm.com uint32_t _base, bool _add, 8917646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8927646Sgene.wu@arm.com uint32_t _index); 8937646Sgene.wu@arm.com 8947646Sgene.wu@arm.com %(BasicExecDeclare)s 8957646Sgene.wu@arm.com 8967646Sgene.wu@arm.com %(InitiateAccDeclare)s 8977646Sgene.wu@arm.com 8987646Sgene.wu@arm.com %(CompleteAccDeclare)s 8997646Sgene.wu@arm.com }; 9007646Sgene.wu@arm.com}}; 9017646Sgene.wu@arm.com 9027646Sgene.wu@arm.comdef template LoadRegDeclare {{ 9037646Sgene.wu@arm.com /** 9047646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 9057646Sgene.wu@arm.com */ 9067646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 9077646Sgene.wu@arm.com { 9087646Sgene.wu@arm.com public: 9097646Sgene.wu@arm.com 9107646Sgene.wu@arm.com /// Constructor. 9117646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 9127646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 9137646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 9147646Sgene.wu@arm.com uint32_t _index); 9157646Sgene.wu@arm.com 9167646Sgene.wu@arm.com %(BasicExecDeclare)s 9177646Sgene.wu@arm.com 9187646Sgene.wu@arm.com %(InitiateAccDeclare)s 9197646Sgene.wu@arm.com 9207646Sgene.wu@arm.com %(CompleteAccDeclare)s 9217646Sgene.wu@arm.com }; 9227646Sgene.wu@arm.com}}; 9237646Sgene.wu@arm.com 9247646Sgene.wu@arm.comdef template LoadImmDeclare {{ 9257646Sgene.wu@arm.com /** 9267646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 9277646Sgene.wu@arm.com */ 9287646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 9297646Sgene.wu@arm.com { 9307646Sgene.wu@arm.com public: 9317646Sgene.wu@arm.com 9327646Sgene.wu@arm.com /// Constructor. 9337646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 9347646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 9357646Sgene.wu@arm.com 9367646Sgene.wu@arm.com %(BasicExecDeclare)s 9377646Sgene.wu@arm.com 9387646Sgene.wu@arm.com %(InitiateAccDeclare)s 9397646Sgene.wu@arm.com 9407646Sgene.wu@arm.com %(CompleteAccDeclare)s 9417646Sgene.wu@arm.com }; 9427646Sgene.wu@arm.com}}; 9437646Sgene.wu@arm.com 9447119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 9457119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 9467119Sgblack@eecs.umich.edu}}; 9477119Sgblack@eecs.umich.edu 9487119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 9497119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 9507119Sgblack@eecs.umich.edu}}; 9517119Sgblack@eecs.umich.edu 9527291Sgblack@eecs.umich.edudef template RfeConstructor {{ 9537291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9547291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 9557291Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9567291Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 9577291Sgblack@eecs.umich.edu { 9587291Sgblack@eecs.umich.edu %(constructor)s; 9597646Sgene.wu@arm.com#if %(use_uops)d 9607646Sgene.wu@arm.com assert(numMicroops >= 2); 9617646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9627646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); 9637646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9647646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9657646Sgene.wu@arm.com#endif 9667291Sgblack@eecs.umich.edu } 9677291Sgblack@eecs.umich.edu}}; 9687291Sgblack@eecs.umich.edu 9697312Sgblack@eecs.umich.edudef template SrsConstructor {{ 9707312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9717312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 9727312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9737312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 9747312Sgblack@eecs.umich.edu { 9757312Sgblack@eecs.umich.edu %(constructor)s; 9767646Sgene.wu@arm.com#if %(use_uops)d 9777646Sgene.wu@arm.com assert(numMicroops >= 2); 9787646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9797646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9807646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9817646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9827646Sgene.wu@arm.com#endif 9837312Sgblack@eecs.umich.edu } 9847312Sgblack@eecs.umich.edu}}; 9857312Sgblack@eecs.umich.edu 9867205Sgblack@eecs.umich.edudef template SwapConstructor {{ 9877205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9887205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9897205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9907205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9917205Sgblack@eecs.umich.edu { 9927205Sgblack@eecs.umich.edu %(constructor)s; 9937205Sgblack@eecs.umich.edu } 9947205Sgblack@eecs.umich.edu}}; 9957205Sgblack@eecs.umich.edu 9967279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 9977279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 9987279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9997279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 10007279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10017279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10027279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10037279Sgblack@eecs.umich.edu { 10047279Sgblack@eecs.umich.edu %(constructor)s; 10057646Sgene.wu@arm.com#if %(use_uops)d 10067646Sgene.wu@arm.com assert(numMicroops >= 2); 10077646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10087646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 10097646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10107646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10117646Sgene.wu@arm.com#endif 10127279Sgblack@eecs.umich.edu } 10137279Sgblack@eecs.umich.edu}}; 10147279Sgblack@eecs.umich.edu 10157303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 10167303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10177303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 10187303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 10197303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10207303Sgblack@eecs.umich.edu (IntRegIndex)_result, 10217303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10227303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10237303Sgblack@eecs.umich.edu { 10247303Sgblack@eecs.umich.edu %(constructor)s; 10257646Sgene.wu@arm.com#if %(use_uops)d 10267646Sgene.wu@arm.com assert(numMicroops >= 2); 10277646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10287646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 10297646Sgene.wu@arm.com _base, _add, _imm); 10307646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10317646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10327646Sgene.wu@arm.com#endif 10337303Sgblack@eecs.umich.edu } 10347303Sgblack@eecs.umich.edu}}; 10357303Sgblack@eecs.umich.edu 10367119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 10377119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10387119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 10397119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10407119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 10417119Sgblack@eecs.umich.edu { 10427119Sgblack@eecs.umich.edu %(constructor)s; 10437646Sgene.wu@arm.com#if %(use_uops)d 10447646Sgene.wu@arm.com assert(numMicroops >= 2); 10457646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10467646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 10477646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10487646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10497646Sgene.wu@arm.com#endif 10507119Sgblack@eecs.umich.edu } 10517119Sgblack@eecs.umich.edu}}; 10527119Sgblack@eecs.umich.edu 10537303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 10547303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10557303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10567303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10577303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10587303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10597303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10607303Sgblack@eecs.umich.edu { 10617303Sgblack@eecs.umich.edu %(constructor)s; 10627646Sgene.wu@arm.com#if %(use_uops)d 10637646Sgene.wu@arm.com assert(numMicroops >= 2); 10647646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10657646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10667646Sgene.wu@arm.com _base, _add, _imm); 10677646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10687646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10697646Sgene.wu@arm.com#endif 10707303Sgblack@eecs.umich.edu } 10717303Sgblack@eecs.umich.edu}}; 10727303Sgblack@eecs.umich.edu 10737646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 10747279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10757279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10767279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10777279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10787279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10797279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10807279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10817279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10827279Sgblack@eecs.umich.edu { 10837279Sgblack@eecs.umich.edu %(constructor)s; 10847646Sgene.wu@arm.com#if %(use_uops)d 10857646Sgene.wu@arm.com assert(numMicroops >= 2); 10867646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10877646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10887646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10897646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10907646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10917646Sgene.wu@arm.com#endif 10927279Sgblack@eecs.umich.edu } 10937279Sgblack@eecs.umich.edu}}; 10947279Sgblack@eecs.umich.edu 10957646Sgene.wu@arm.comdef template StoreRegConstructor {{ 10967119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 10977119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10987119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10997119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11007119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11017119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 11027119Sgblack@eecs.umich.edu (IntRegIndex)_index) 11037119Sgblack@eecs.umich.edu { 11047119Sgblack@eecs.umich.edu %(constructor)s; 11057646Sgene.wu@arm.com#if %(use_uops)d 11067646Sgene.wu@arm.com assert(numMicroops >= 2); 11077646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11087646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11097646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11107646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11117646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11127646Sgene.wu@arm.com#endif 11137119Sgblack@eecs.umich.edu } 11147119Sgblack@eecs.umich.edu}}; 11157646Sgene.wu@arm.com 11167646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 11177646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11187646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 11197646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11207646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11217646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 11227646Sgene.wu@arm.com (IntRegIndex)_base, _add, 11237646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11247646Sgene.wu@arm.com (IntRegIndex)_index) 11257646Sgene.wu@arm.com { 11267646Sgene.wu@arm.com %(constructor)s; 11277646Sgene.wu@arm.com#if %(use_uops)d 11287646Sgene.wu@arm.com assert(numMicroops >= 2); 11297646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11307646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 11317646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11327646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11337646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11347646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11357646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11367646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11377646Sgene.wu@arm.com } else { 11387646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11397646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11407646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11417646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11427646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11437646Sgene.wu@arm.com } 11447646Sgene.wu@arm.com#endif 11457646Sgene.wu@arm.com } 11467646Sgene.wu@arm.com}}; 11477646Sgene.wu@arm.com 11487646Sgene.wu@arm.comdef template LoadRegConstructor {{ 11497646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11507646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11517646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11527646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11537646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11547646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11557646Sgene.wu@arm.com (IntRegIndex)_index) 11567646Sgene.wu@arm.com { 11577646Sgene.wu@arm.com %(constructor)s; 11587646Sgene.wu@arm.com#if %(use_uops)d 11597646Sgene.wu@arm.com assert(numMicroops >= 2); 11607646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11617646Sgene.wu@arm.com if (_dest == INTREG_PC) { 11627646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11637646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11647646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11657646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11667646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11677646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11687646Sgene.wu@arm.com } else if(_dest == _index) { 11697646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11707646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11717646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11727646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11737646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11747646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11757646Sgene.wu@arm.com } else { 11767646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11777646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11787646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11797646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11807646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11817646Sgene.wu@arm.com 11827646Sgene.wu@arm.com } 11837646Sgene.wu@arm.com#endif 11847646Sgene.wu@arm.com } 11857646Sgene.wu@arm.com}}; 11867646Sgene.wu@arm.com 11877646Sgene.wu@arm.comdef template LoadImmConstructor {{ 11887646Sgene.wu@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 11897646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 11907646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11917646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 11927646Sgene.wu@arm.com { 11937646Sgene.wu@arm.com %(constructor)s; 11947646Sgene.wu@arm.com#if %(use_uops)d 11957646Sgene.wu@arm.com assert(numMicroops >= 2); 11967646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11977646Sgene.wu@arm.com if (_dest == INTREG_PC) { 11987646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11997646Sgene.wu@arm.com _imm); 12007646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12017646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12027646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12037646Sgene.wu@arm.com } else { 12047646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12057646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12067646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12077646Sgene.wu@arm.com } 12087646Sgene.wu@arm.com#endif 12097646Sgene.wu@arm.com } 12107646Sgene.wu@arm.com}}; 12117646Sgene.wu@arm.com 1212