mem.isa revision 7408
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37120Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.edudef template SwapExecute {{ 457205Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 467205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 477205Sgblack@eecs.umich.edu { 487205Sgblack@eecs.umich.edu Addr EA; 497205Sgblack@eecs.umich.edu Fault fault = NoFault; 507205Sgblack@eecs.umich.edu 517205Sgblack@eecs.umich.edu %(op_decl)s; 527205Sgblack@eecs.umich.edu uint64_t memData = 0; 537205Sgblack@eecs.umich.edu %(op_rd)s; 547205Sgblack@eecs.umich.edu %(ea_code)s; 557205Sgblack@eecs.umich.edu 567205Sgblack@eecs.umich.edu if (%(predicate_test)s) 577205Sgblack@eecs.umich.edu { 587205Sgblack@eecs.umich.edu %(preacc_code)s; 597205Sgblack@eecs.umich.edu 607205Sgblack@eecs.umich.edu if (fault == NoFault) { 617205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 627205Sgblack@eecs.umich.edu EA, memAccessFlags, &memData); 637205Sgblack@eecs.umich.edu } 647205Sgblack@eecs.umich.edu 657205Sgblack@eecs.umich.edu if (fault == NoFault) { 667205Sgblack@eecs.umich.edu %(postacc_code)s; 677205Sgblack@eecs.umich.edu } 687205Sgblack@eecs.umich.edu 697205Sgblack@eecs.umich.edu if (fault == NoFault) { 707205Sgblack@eecs.umich.edu %(op_wb)s; 717205Sgblack@eecs.umich.edu } 727205Sgblack@eecs.umich.edu } 737205Sgblack@eecs.umich.edu 747408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 757408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 767408Sgblack@eecs.umich.edu } 777408Sgblack@eecs.umich.edu 787205Sgblack@eecs.umich.edu return fault; 797205Sgblack@eecs.umich.edu } 807205Sgblack@eecs.umich.edu}}; 817205Sgblack@eecs.umich.edu 827205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 837205Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 847205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 857205Sgblack@eecs.umich.edu { 867205Sgblack@eecs.umich.edu Addr EA; 877205Sgblack@eecs.umich.edu Fault fault = NoFault; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu %(op_decl)s; 907205Sgblack@eecs.umich.edu uint64_t memData = 0; 917205Sgblack@eecs.umich.edu %(op_rd)s; 927205Sgblack@eecs.umich.edu %(ea_code)s; 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (%(predicate_test)s) 957205Sgblack@eecs.umich.edu { 967205Sgblack@eecs.umich.edu %(preacc_code)s; 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1007205Sgblack@eecs.umich.edu memAccessFlags, &memData); 1017205Sgblack@eecs.umich.edu } 1027205Sgblack@eecs.umich.edu 1037205Sgblack@eecs.umich.edu if (fault == NoFault) { 1047205Sgblack@eecs.umich.edu %(op_wb)s; 1057205Sgblack@eecs.umich.edu } 1067205Sgblack@eecs.umich.edu } 1077205Sgblack@eecs.umich.edu 1087408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1097408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1107408Sgblack@eecs.umich.edu } 1117408Sgblack@eecs.umich.edu 1127205Sgblack@eecs.umich.edu return fault; 1137205Sgblack@eecs.umich.edu } 1147205Sgblack@eecs.umich.edu}}; 1157205Sgblack@eecs.umich.edu 1167205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1177205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1187205Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1197205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1207205Sgblack@eecs.umich.edu { 1217205Sgblack@eecs.umich.edu Fault fault = NoFault; 1227205Sgblack@eecs.umich.edu 1237205Sgblack@eecs.umich.edu %(op_decl)s; 1247205Sgblack@eecs.umich.edu %(op_rd)s; 1257205Sgblack@eecs.umich.edu 1267205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1277205Sgblack@eecs.umich.edu { 1287205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1297205Sgblack@eecs.umich.edu uint64_t memData = pkt->get<typeof(Mem)>(); 1307205Sgblack@eecs.umich.edu 1317205Sgblack@eecs.umich.edu %(postacc_code)s; 1327205Sgblack@eecs.umich.edu 1337205Sgblack@eecs.umich.edu if (fault == NoFault) { 1347205Sgblack@eecs.umich.edu %(op_wb)s; 1357205Sgblack@eecs.umich.edu } 1367205Sgblack@eecs.umich.edu } 1377205Sgblack@eecs.umich.edu 1387408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1397408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1407408Sgblack@eecs.umich.edu } 1417408Sgblack@eecs.umich.edu 1427205Sgblack@eecs.umich.edu return fault; 1437205Sgblack@eecs.umich.edu } 1447205Sgblack@eecs.umich.edu}}; 1457205Sgblack@eecs.umich.edu 1467119Sgblack@eecs.umich.edudef template LoadExecute {{ 1477119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1487119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1497119Sgblack@eecs.umich.edu { 1507119Sgblack@eecs.umich.edu Addr EA; 1517119Sgblack@eecs.umich.edu Fault fault = NoFault; 1527119Sgblack@eecs.umich.edu 1537119Sgblack@eecs.umich.edu %(op_decl)s; 1547119Sgblack@eecs.umich.edu %(op_rd)s; 1557119Sgblack@eecs.umich.edu %(ea_code)s; 1567119Sgblack@eecs.umich.edu 1577119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1587119Sgblack@eecs.umich.edu { 1597119Sgblack@eecs.umich.edu if (fault == NoFault) { 1607119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 1617119Sgblack@eecs.umich.edu %(memacc_code)s; 1627119Sgblack@eecs.umich.edu } 1637119Sgblack@eecs.umich.edu 1647119Sgblack@eecs.umich.edu if (fault == NoFault) { 1657119Sgblack@eecs.umich.edu %(op_wb)s; 1667119Sgblack@eecs.umich.edu } 1677119Sgblack@eecs.umich.edu } 1687119Sgblack@eecs.umich.edu 1697408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1707408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1717408Sgblack@eecs.umich.edu } 1727408Sgblack@eecs.umich.edu 1737119Sgblack@eecs.umich.edu return fault; 1747119Sgblack@eecs.umich.edu } 1757119Sgblack@eecs.umich.edu}}; 1767119Sgblack@eecs.umich.edu 1777120Sgblack@eecs.umich.edudef template StoreExecute {{ 1787120Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1797120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1807120Sgblack@eecs.umich.edu { 1817120Sgblack@eecs.umich.edu Addr EA; 1827120Sgblack@eecs.umich.edu Fault fault = NoFault; 1837120Sgblack@eecs.umich.edu 1847120Sgblack@eecs.umich.edu %(op_decl)s; 1857120Sgblack@eecs.umich.edu %(op_rd)s; 1867120Sgblack@eecs.umich.edu %(ea_code)s; 1877120Sgblack@eecs.umich.edu 1887120Sgblack@eecs.umich.edu if (%(predicate_test)s) 1897120Sgblack@eecs.umich.edu { 1907120Sgblack@eecs.umich.edu if (fault == NoFault) { 1917120Sgblack@eecs.umich.edu %(memacc_code)s; 1927120Sgblack@eecs.umich.edu } 1937120Sgblack@eecs.umich.edu 1947120Sgblack@eecs.umich.edu if (fault == NoFault) { 1957120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 1967120Sgblack@eecs.umich.edu memAccessFlags, NULL); 1977120Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 1987120Sgblack@eecs.umich.edu } 1997120Sgblack@eecs.umich.edu 2007120Sgblack@eecs.umich.edu if (fault == NoFault) { 2017120Sgblack@eecs.umich.edu %(op_wb)s; 2027120Sgblack@eecs.umich.edu } 2037120Sgblack@eecs.umich.edu } 2047120Sgblack@eecs.umich.edu 2057408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2067408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2077408Sgblack@eecs.umich.edu } 2087408Sgblack@eecs.umich.edu 2097120Sgblack@eecs.umich.edu return fault; 2107120Sgblack@eecs.umich.edu } 2117120Sgblack@eecs.umich.edu}}; 2127120Sgblack@eecs.umich.edu 2137303Sgblack@eecs.umich.edudef template StoreExExecute {{ 2147303Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2157303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2167303Sgblack@eecs.umich.edu { 2177303Sgblack@eecs.umich.edu Addr EA; 2187303Sgblack@eecs.umich.edu Fault fault = NoFault; 2197303Sgblack@eecs.umich.edu 2207303Sgblack@eecs.umich.edu %(op_decl)s; 2217303Sgblack@eecs.umich.edu %(op_rd)s; 2227303Sgblack@eecs.umich.edu %(ea_code)s; 2237303Sgblack@eecs.umich.edu 2247303Sgblack@eecs.umich.edu if (%(predicate_test)s) 2257303Sgblack@eecs.umich.edu { 2267303Sgblack@eecs.umich.edu if (fault == NoFault) { 2277303Sgblack@eecs.umich.edu %(memacc_code)s; 2287303Sgblack@eecs.umich.edu } 2297303Sgblack@eecs.umich.edu 2307303Sgblack@eecs.umich.edu uint64_t writeResult; 2317303Sgblack@eecs.umich.edu 2327303Sgblack@eecs.umich.edu if (fault == NoFault) { 2337303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2347303Sgblack@eecs.umich.edu memAccessFlags, &writeResult); 2357303Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2367303Sgblack@eecs.umich.edu } 2377303Sgblack@eecs.umich.edu 2387303Sgblack@eecs.umich.edu if (fault == NoFault) { 2397303Sgblack@eecs.umich.edu %(postacc_code)s; 2407303Sgblack@eecs.umich.edu } 2417303Sgblack@eecs.umich.edu 2427303Sgblack@eecs.umich.edu if (fault == NoFault) { 2437303Sgblack@eecs.umich.edu %(op_wb)s; 2447303Sgblack@eecs.umich.edu } 2457303Sgblack@eecs.umich.edu } 2467303Sgblack@eecs.umich.edu 2477408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2487408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2497408Sgblack@eecs.umich.edu } 2507408Sgblack@eecs.umich.edu 2517303Sgblack@eecs.umich.edu return fault; 2527303Sgblack@eecs.umich.edu } 2537303Sgblack@eecs.umich.edu}}; 2547303Sgblack@eecs.umich.edu 2557303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 2567303Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2577303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2587303Sgblack@eecs.umich.edu { 2597303Sgblack@eecs.umich.edu Addr EA; 2607303Sgblack@eecs.umich.edu Fault fault = NoFault; 2617303Sgblack@eecs.umich.edu 2627303Sgblack@eecs.umich.edu %(op_decl)s; 2637303Sgblack@eecs.umich.edu %(op_rd)s; 2647303Sgblack@eecs.umich.edu %(ea_code)s; 2657303Sgblack@eecs.umich.edu 2667303Sgblack@eecs.umich.edu if (%(predicate_test)s) 2677303Sgblack@eecs.umich.edu { 2687303Sgblack@eecs.umich.edu if (fault == NoFault) { 2697303Sgblack@eecs.umich.edu %(memacc_code)s; 2707303Sgblack@eecs.umich.edu } 2717303Sgblack@eecs.umich.edu 2727303Sgblack@eecs.umich.edu if (fault == NoFault) { 2737303Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2747303Sgblack@eecs.umich.edu memAccessFlags, NULL); 2757303Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2767303Sgblack@eecs.umich.edu } 2777303Sgblack@eecs.umich.edu 2787303Sgblack@eecs.umich.edu // Need to write back any potential address register update 2797303Sgblack@eecs.umich.edu if (fault == NoFault) { 2807303Sgblack@eecs.umich.edu %(op_wb)s; 2817303Sgblack@eecs.umich.edu } 2827303Sgblack@eecs.umich.edu } 2837303Sgblack@eecs.umich.edu 2847408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2857408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2867408Sgblack@eecs.umich.edu } 2877408Sgblack@eecs.umich.edu 2887303Sgblack@eecs.umich.edu return fault; 2897303Sgblack@eecs.umich.edu } 2907303Sgblack@eecs.umich.edu}}; 2917303Sgblack@eecs.umich.edu 2927120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 2937120Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2947120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2957120Sgblack@eecs.umich.edu { 2967120Sgblack@eecs.umich.edu Addr EA; 2977120Sgblack@eecs.umich.edu Fault fault = NoFault; 2987120Sgblack@eecs.umich.edu 2997120Sgblack@eecs.umich.edu %(op_decl)s; 3007120Sgblack@eecs.umich.edu %(op_rd)s; 3017120Sgblack@eecs.umich.edu %(ea_code)s; 3027120Sgblack@eecs.umich.edu 3037120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3047120Sgblack@eecs.umich.edu { 3057120Sgblack@eecs.umich.edu if (fault == NoFault) { 3067120Sgblack@eecs.umich.edu %(memacc_code)s; 3077120Sgblack@eecs.umich.edu } 3087120Sgblack@eecs.umich.edu 3097120Sgblack@eecs.umich.edu if (fault == NoFault) { 3107120Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3117120Sgblack@eecs.umich.edu memAccessFlags, NULL); 3127120Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 3137120Sgblack@eecs.umich.edu } 3147120Sgblack@eecs.umich.edu 3157120Sgblack@eecs.umich.edu // Need to write back any potential address register update 3167120Sgblack@eecs.umich.edu if (fault == NoFault) { 3177120Sgblack@eecs.umich.edu %(op_wb)s; 3187120Sgblack@eecs.umich.edu } 3197120Sgblack@eecs.umich.edu } 3207120Sgblack@eecs.umich.edu 3217408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 3227408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3237408Sgblack@eecs.umich.edu } 3247408Sgblack@eecs.umich.edu 3257120Sgblack@eecs.umich.edu return fault; 3267120Sgblack@eecs.umich.edu } 3277120Sgblack@eecs.umich.edu}}; 3287120Sgblack@eecs.umich.edu 3297119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 3307119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3317119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3327119Sgblack@eecs.umich.edu { 3337119Sgblack@eecs.umich.edu Addr EA; 3347119Sgblack@eecs.umich.edu Fault fault = NoFault; 3357119Sgblack@eecs.umich.edu 3367119Sgblack@eecs.umich.edu %(op_src_decl)s; 3377119Sgblack@eecs.umich.edu %(op_rd)s; 3387119Sgblack@eecs.umich.edu %(ea_code)s; 3397119Sgblack@eecs.umich.edu 3407119Sgblack@eecs.umich.edu if (%(predicate_test)s) 3417119Sgblack@eecs.umich.edu { 3427119Sgblack@eecs.umich.edu if (fault == NoFault) { 3437119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 3447119Sgblack@eecs.umich.edu } 3457119Sgblack@eecs.umich.edu } 3467119Sgblack@eecs.umich.edu 3477119Sgblack@eecs.umich.edu return fault; 3487119Sgblack@eecs.umich.edu } 3497119Sgblack@eecs.umich.edu}}; 3507119Sgblack@eecs.umich.edu 3517119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 3527119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3537119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 3547119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3557119Sgblack@eecs.umich.edu { 3567119Sgblack@eecs.umich.edu Fault fault = NoFault; 3577119Sgblack@eecs.umich.edu 3587119Sgblack@eecs.umich.edu %(op_decl)s; 3597119Sgblack@eecs.umich.edu %(op_rd)s; 3607119Sgblack@eecs.umich.edu 3617119Sgblack@eecs.umich.edu if (%(predicate_test)s) 3627119Sgblack@eecs.umich.edu { 3637119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 3647119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 3657119Sgblack@eecs.umich.edu 3667119Sgblack@eecs.umich.edu if (fault == NoFault) { 3677119Sgblack@eecs.umich.edu %(memacc_code)s; 3687119Sgblack@eecs.umich.edu } 3697119Sgblack@eecs.umich.edu 3707119Sgblack@eecs.umich.edu if (fault == NoFault) { 3717119Sgblack@eecs.umich.edu %(op_wb)s; 3727119Sgblack@eecs.umich.edu } 3737119Sgblack@eecs.umich.edu } 3747119Sgblack@eecs.umich.edu 3757408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 3767408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 3777408Sgblack@eecs.umich.edu } 3787408Sgblack@eecs.umich.edu 3797119Sgblack@eecs.umich.edu return fault; 3807119Sgblack@eecs.umich.edu } 3817119Sgblack@eecs.umich.edu}}; 3827119Sgblack@eecs.umich.edu 3837120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 3847120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3857120Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 3867120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3877120Sgblack@eecs.umich.edu { 3887120Sgblack@eecs.umich.edu Fault fault = NoFault; 3897120Sgblack@eecs.umich.edu 3907120Sgblack@eecs.umich.edu %(op_decl)s; 3917120Sgblack@eecs.umich.edu %(op_rd)s; 3927120Sgblack@eecs.umich.edu 3937120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3947120Sgblack@eecs.umich.edu { 3957120Sgblack@eecs.umich.edu if (fault == NoFault) { 3967120Sgblack@eecs.umich.edu %(op_wb)s; 3977120Sgblack@eecs.umich.edu } 3987120Sgblack@eecs.umich.edu } 3997120Sgblack@eecs.umich.edu 4007408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 4017408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4027408Sgblack@eecs.umich.edu } 4037408Sgblack@eecs.umich.edu 4047120Sgblack@eecs.umich.edu return fault; 4057120Sgblack@eecs.umich.edu } 4067120Sgblack@eecs.umich.edu}}; 4077120Sgblack@eecs.umich.edu 4087303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 4097303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4107303Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4117303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4127303Sgblack@eecs.umich.edu { 4137303Sgblack@eecs.umich.edu Fault fault = NoFault; 4147303Sgblack@eecs.umich.edu 4157303Sgblack@eecs.umich.edu %(op_decl)s; 4167303Sgblack@eecs.umich.edu %(op_rd)s; 4177303Sgblack@eecs.umich.edu 4187303Sgblack@eecs.umich.edu if (%(predicate_test)s) 4197303Sgblack@eecs.umich.edu { 4207303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 4217303Sgblack@eecs.umich.edu %(postacc_code)s; 4227303Sgblack@eecs.umich.edu 4237303Sgblack@eecs.umich.edu if (fault == NoFault) { 4247303Sgblack@eecs.umich.edu %(op_wb)s; 4257303Sgblack@eecs.umich.edu } 4267303Sgblack@eecs.umich.edu } 4277303Sgblack@eecs.umich.edu 4287408Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 4297408Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 4307408Sgblack@eecs.umich.edu } 4317408Sgblack@eecs.umich.edu 4327303Sgblack@eecs.umich.edu return fault; 4337303Sgblack@eecs.umich.edu } 4347303Sgblack@eecs.umich.edu}}; 4357303Sgblack@eecs.umich.edu 4367291Sgblack@eecs.umich.edudef template RfeDeclare {{ 4377291Sgblack@eecs.umich.edu /** 4387291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4397291Sgblack@eecs.umich.edu */ 4407291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 4417291Sgblack@eecs.umich.edu { 4427291Sgblack@eecs.umich.edu public: 4437291Sgblack@eecs.umich.edu 4447291Sgblack@eecs.umich.edu /// Constructor. 4457291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 4467291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 4477291Sgblack@eecs.umich.edu 4487291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4497291Sgblack@eecs.umich.edu 4507291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 4517291Sgblack@eecs.umich.edu 4527291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4537291Sgblack@eecs.umich.edu }; 4547291Sgblack@eecs.umich.edu}}; 4557291Sgblack@eecs.umich.edu 4567312Sgblack@eecs.umich.edudef template SrsDeclare {{ 4577312Sgblack@eecs.umich.edu /** 4587312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4597312Sgblack@eecs.umich.edu */ 4607312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 4617312Sgblack@eecs.umich.edu { 4627312Sgblack@eecs.umich.edu public: 4637312Sgblack@eecs.umich.edu 4647312Sgblack@eecs.umich.edu /// Constructor. 4657312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 4667312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 4677312Sgblack@eecs.umich.edu 4687312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4697312Sgblack@eecs.umich.edu 4707312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 4717312Sgblack@eecs.umich.edu 4727312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4737312Sgblack@eecs.umich.edu }; 4747312Sgblack@eecs.umich.edu}}; 4757312Sgblack@eecs.umich.edu 4767205Sgblack@eecs.umich.edudef template SwapDeclare {{ 4777205Sgblack@eecs.umich.edu /** 4787205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4797205Sgblack@eecs.umich.edu */ 4807205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 4817205Sgblack@eecs.umich.edu { 4827205Sgblack@eecs.umich.edu public: 4837205Sgblack@eecs.umich.edu 4847205Sgblack@eecs.umich.edu /// Constructor. 4857205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 4867205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 4877205Sgblack@eecs.umich.edu 4887205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 4897205Sgblack@eecs.umich.edu 4907205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 4917205Sgblack@eecs.umich.edu 4927205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 4937205Sgblack@eecs.umich.edu }; 4947205Sgblack@eecs.umich.edu}}; 4957205Sgblack@eecs.umich.edu 4967279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 4977279Sgblack@eecs.umich.edu /** 4987279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 4997279Sgblack@eecs.umich.edu */ 5007279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5017279Sgblack@eecs.umich.edu { 5027279Sgblack@eecs.umich.edu public: 5037279Sgblack@eecs.umich.edu 5047279Sgblack@eecs.umich.edu /// Constructor. 5057279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5067279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 5077279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 5087279Sgblack@eecs.umich.edu 5097279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5107279Sgblack@eecs.umich.edu 5117279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5127279Sgblack@eecs.umich.edu 5137279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5147279Sgblack@eecs.umich.edu }; 5157279Sgblack@eecs.umich.edu}}; 5167279Sgblack@eecs.umich.edu 5177303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 5187303Sgblack@eecs.umich.edu /** 5197303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5207303Sgblack@eecs.umich.edu */ 5217303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5227303Sgblack@eecs.umich.edu { 5237303Sgblack@eecs.umich.edu public: 5247303Sgblack@eecs.umich.edu 5257303Sgblack@eecs.umich.edu /// Constructor. 5267303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5277303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 5287303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 5297303Sgblack@eecs.umich.edu 5307303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5317303Sgblack@eecs.umich.edu 5327303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5337303Sgblack@eecs.umich.edu 5347303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5357303Sgblack@eecs.umich.edu }; 5367303Sgblack@eecs.umich.edu}}; 5377303Sgblack@eecs.umich.edu 5387119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 5397119Sgblack@eecs.umich.edu /** 5407119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5417119Sgblack@eecs.umich.edu */ 5427119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5437119Sgblack@eecs.umich.edu { 5447119Sgblack@eecs.umich.edu public: 5457119Sgblack@eecs.umich.edu 5467119Sgblack@eecs.umich.edu /// Constructor. 5477119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5487119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 5497119Sgblack@eecs.umich.edu 5507119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5517119Sgblack@eecs.umich.edu 5527119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5537119Sgblack@eecs.umich.edu 5547119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5557119Sgblack@eecs.umich.edu }; 5567119Sgblack@eecs.umich.edu}}; 5577119Sgblack@eecs.umich.edu 5587303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 5597303Sgblack@eecs.umich.edu /** 5607303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5617303Sgblack@eecs.umich.edu */ 5627303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5637303Sgblack@eecs.umich.edu { 5647303Sgblack@eecs.umich.edu public: 5657303Sgblack@eecs.umich.edu 5667303Sgblack@eecs.umich.edu /// Constructor. 5677303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5687303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 5697303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 5707303Sgblack@eecs.umich.edu 5717303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5727303Sgblack@eecs.umich.edu 5737303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5747303Sgblack@eecs.umich.edu 5757303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5767303Sgblack@eecs.umich.edu }; 5777303Sgblack@eecs.umich.edu}}; 5787303Sgblack@eecs.umich.edu 5797279Sgblack@eecs.umich.edudef template LoadStoreDRegDeclare {{ 5807279Sgblack@eecs.umich.edu /** 5817279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5827279Sgblack@eecs.umich.edu */ 5837279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5847279Sgblack@eecs.umich.edu { 5857279Sgblack@eecs.umich.edu public: 5867279Sgblack@eecs.umich.edu 5877279Sgblack@eecs.umich.edu /// Constructor. 5887279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5897279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 5907279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 5917279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 5927279Sgblack@eecs.umich.edu uint32_t _index); 5937279Sgblack@eecs.umich.edu 5947279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5957279Sgblack@eecs.umich.edu 5967279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5977279Sgblack@eecs.umich.edu 5987279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5997279Sgblack@eecs.umich.edu }; 6007279Sgblack@eecs.umich.edu}}; 6017279Sgblack@eecs.umich.edu 6027119Sgblack@eecs.umich.edudef template LoadStoreRegDeclare {{ 6037119Sgblack@eecs.umich.edu /** 6047119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6057119Sgblack@eecs.umich.edu */ 6067119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6077119Sgblack@eecs.umich.edu { 6087119Sgblack@eecs.umich.edu public: 6097119Sgblack@eecs.umich.edu 6107119Sgblack@eecs.umich.edu /// Constructor. 6117119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6127119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 6137119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 6147119Sgblack@eecs.umich.edu uint32_t _index); 6157119Sgblack@eecs.umich.edu 6167119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6177119Sgblack@eecs.umich.edu 6187119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6197119Sgblack@eecs.umich.edu 6207119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6217119Sgblack@eecs.umich.edu }; 6227119Sgblack@eecs.umich.edu}}; 6237119Sgblack@eecs.umich.edu 6247119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 6257119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 6267119Sgblack@eecs.umich.edu}}; 6277119Sgblack@eecs.umich.edu 6287119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 6297119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 6307119Sgblack@eecs.umich.edu}}; 6317119Sgblack@eecs.umich.edu 6327291Sgblack@eecs.umich.edudef template RfeConstructor {{ 6337291Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6347291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 6357291Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6367291Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 6377291Sgblack@eecs.umich.edu { 6387291Sgblack@eecs.umich.edu %(constructor)s; 6397291Sgblack@eecs.umich.edu } 6407291Sgblack@eecs.umich.edu}}; 6417291Sgblack@eecs.umich.edu 6427312Sgblack@eecs.umich.edudef template SrsConstructor {{ 6437312Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6447312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 6457312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6467312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 6477312Sgblack@eecs.umich.edu { 6487312Sgblack@eecs.umich.edu %(constructor)s; 6497312Sgblack@eecs.umich.edu } 6507312Sgblack@eecs.umich.edu}}; 6517312Sgblack@eecs.umich.edu 6527205Sgblack@eecs.umich.edudef template SwapConstructor {{ 6537205Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6547205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 6557205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6567205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 6577205Sgblack@eecs.umich.edu { 6587205Sgblack@eecs.umich.edu %(constructor)s; 6597205Sgblack@eecs.umich.edu } 6607205Sgblack@eecs.umich.edu}}; 6617205Sgblack@eecs.umich.edu 6627279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 6637279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6647279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6657279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 6667279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6677279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 6687279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 6697279Sgblack@eecs.umich.edu { 6707279Sgblack@eecs.umich.edu %(constructor)s; 6717279Sgblack@eecs.umich.edu } 6727279Sgblack@eecs.umich.edu}}; 6737279Sgblack@eecs.umich.edu 6747303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 6757303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6767303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6777303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 6787303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6797303Sgblack@eecs.umich.edu (IntRegIndex)_result, 6807303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 6817303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 6827303Sgblack@eecs.umich.edu { 6837303Sgblack@eecs.umich.edu %(constructor)s; 6847303Sgblack@eecs.umich.edu } 6857303Sgblack@eecs.umich.edu}}; 6867303Sgblack@eecs.umich.edu 6877119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 6887119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6897119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 6907119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6917119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 6927119Sgblack@eecs.umich.edu { 6937119Sgblack@eecs.umich.edu %(constructor)s; 6947119Sgblack@eecs.umich.edu } 6957119Sgblack@eecs.umich.edu}}; 6967119Sgblack@eecs.umich.edu 6977303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 6987303Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 6997303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7007303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 7017303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7027303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 7037303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 7047303Sgblack@eecs.umich.edu { 7057303Sgblack@eecs.umich.edu %(constructor)s; 7067303Sgblack@eecs.umich.edu } 7077303Sgblack@eecs.umich.edu}}; 7087303Sgblack@eecs.umich.edu 7097279Sgblack@eecs.umich.edudef template LoadStoreDRegConstructor {{ 7107279Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 7117279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 7127279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 7137279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7147279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 7157279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 7167279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 7177279Sgblack@eecs.umich.edu (IntRegIndex)_index) 7187279Sgblack@eecs.umich.edu { 7197279Sgblack@eecs.umich.edu %(constructor)s; 7207279Sgblack@eecs.umich.edu } 7217279Sgblack@eecs.umich.edu}}; 7227279Sgblack@eecs.umich.edu 7237119Sgblack@eecs.umich.edudef template LoadStoreRegConstructor {{ 7247119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 7257119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7267119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 7277119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 7287119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 7297119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 7307119Sgblack@eecs.umich.edu (IntRegIndex)_index) 7317119Sgblack@eecs.umich.edu { 7327119Sgblack@eecs.umich.edu %(constructor)s; 7337119Sgblack@eecs.umich.edu } 7347119Sgblack@eecs.umich.edu}}; 735