mem.isa revision 7279
111598Sandreas.sandberg@arm.com// -*- mode:c++ -*- 27586SAli.Saidi@arm.com 37586SAli.Saidi@arm.com// Copyright (c) 2010 ARM Limited 47586SAli.Saidi@arm.com// All rights reserved 57586SAli.Saidi@arm.com// 67586SAli.Saidi@arm.com// The license below extends only to copyright in the software and shall 77586SAli.Saidi@arm.com// not be construed as granting a license to any other intellectual 87586SAli.Saidi@arm.com// property including but not limited to intellectual property relating 97586SAli.Saidi@arm.com// to a hardware implementation of the functionality of the software 107586SAli.Saidi@arm.com// licensed hereunder. You may use the software subject to the license 117586SAli.Saidi@arm.com// terms below provided that you ensure that this notice is replicated 127586SAli.Saidi@arm.com// unmodified and in its entirety in all distributions of the software, 1310118Snilay@cs.wisc.edu// modified or unmodified, in source code or in binary form. 1410118Snilay@cs.wisc.edu// 153970Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 163005Sstever@eecs.umich.edu// All rights reserved. 173005Sstever@eecs.umich.edu// 183005Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 193005Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 203005Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 213005Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 223005Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 233005Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 243005Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 253005Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 263005Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 273005Sstever@eecs.umich.edu// this software without specific prior written permission. 283005Sstever@eecs.umich.edu// 293005Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303005Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313005Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323005Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333005Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343005Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353005Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363005Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373005Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383005Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393005Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403005Sstever@eecs.umich.edu// 413005Sstever@eecs.umich.edu// Authors: Stephen Hines 4210118Snilay@cs.wisc.edu 433005Sstever@eecs.umich.edu 446654Snate@binkert.orgdef template SwapExecute {{ 456654Snate@binkert.org Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 462889SN/A Trace::InstRecord *traceData) const 472710SN/A { 486654Snate@binkert.org Addr EA; 496654Snate@binkert.org Fault fault = NoFault; 506654Snate@binkert.org 515457Ssaidi@eecs.umich.edu %(op_decl)s; 526654Snate@binkert.org uint64_t memData = 0; 5310118Snilay@cs.wisc.edu %(op_rd)s; 5410118Snilay@cs.wisc.edu %(ea_code)s; 5510118Snilay@cs.wisc.edu 566654Snate@binkert.org if (%(predicate_test)s) 572934SN/A { 582549SN/A %(preacc_code)s; 592995SN/A 603395Shsul@eecs.umich.edu if (fault == NoFault) { 616981SLisa.Hsu@amd.com fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 629836Sandreas.hansson@arm.com EA, memAccessFlags, &memData); 633448Shsul@eecs.umich.edu } 648920Snilay@cs.wisc.edu 653444Sktlim@umich.edu if (fault == NoFault) { 663304Sstever@eecs.umich.edu %(postacc_code)s; 679653SAndreas.Sandberg@ARM.com } 689653SAndreas.Sandberg@ARM.com 699653SAndreas.Sandberg@ARM.com if (fault == NoFault) { 709653SAndreas.Sandberg@ARM.com %(op_wb)s; 719653SAndreas.Sandberg@ARM.com } 729653SAndreas.Sandberg@ARM.com } 739653SAndreas.Sandberg@ARM.com 7410594Sgabeblack@google.com return fault; 7510594Sgabeblack@google.com } 7610594Sgabeblack@google.com}}; 7710594Sgabeblack@google.com 7810594Sgabeblack@google.comdef template SwapInitiateAcc {{ 7910594Sgabeblack@google.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 8010594Sgabeblack@google.com Trace::InstRecord *traceData) const 8110594Sgabeblack@google.com { 8210594Sgabeblack@google.com Addr EA; 8310594Sgabeblack@google.com Fault fault = NoFault; 8410594Sgabeblack@google.com 8510119Snilay@cs.wisc.edu %(op_decl)s; 8610594Sgabeblack@google.com uint64_t memData = 0; 8710119Snilay@cs.wisc.edu %(op_rd)s; 8810594Sgabeblack@google.com %(ea_code)s; 8910594Sgabeblack@google.com 9010119Snilay@cs.wisc.edu if (%(predicate_test)s) 9110594Sgabeblack@google.com { 9210119Snilay@cs.wisc.edu %(preacc_code)s; 9310594Sgabeblack@google.com 9410119Snilay@cs.wisc.edu if (fault == NoFault) { 9510119Snilay@cs.wisc.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 9610594Sgabeblack@google.com memAccessFlags, &memData); 9710119Snilay@cs.wisc.edu } 9810512SAli.Saidi@ARM.com 9910512SAli.Saidi@ARM.com if (fault == NoFault) { 10010594Sgabeblack@google.com %(op_wb)s; 10110780SCurtis.Dunham@arm.com } 10211598Sandreas.sandberg@arm.com } 10311598Sandreas.sandberg@arm.com 10410119Snilay@cs.wisc.edu return fault; 10510119Snilay@cs.wisc.edu } 10610119Snilay@cs.wisc.edu}}; 10710119Snilay@cs.wisc.edu 1082566SN/Adef template SwapCompleteAcc {{ 10910119Snilay@cs.wisc.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 11010119Snilay@cs.wisc.edu %(CPU_exec_context)s *xc, 1119665Sandreas.hansson@arm.com Trace::InstRecord *traceData) const 11210119Snilay@cs.wisc.edu { 11310119Snilay@cs.wisc.edu Fault fault = NoFault; 11410119Snilay@cs.wisc.edu 11510119Snilay@cs.wisc.edu %(op_decl)s; 11610119Snilay@cs.wisc.edu %(op_rd)s; 11710119Snilay@cs.wisc.edu 11810119Snilay@cs.wisc.edu if (%(predicate_test)s) 11910119Snilay@cs.wisc.edu { 12010119Snilay@cs.wisc.edu // ARM instructions will not have a pkt if the predicate is false 12110119Snilay@cs.wisc.edu uint64_t memData = pkt->get<typeof(Mem)>(); 12210119Snilay@cs.wisc.edu 12310119Snilay@cs.wisc.edu %(postacc_code)s; 12410119Snilay@cs.wisc.edu 12510119Snilay@cs.wisc.edu if (fault == NoFault) { 12610119Snilay@cs.wisc.edu %(op_wb)s; 12710119Snilay@cs.wisc.edu } 12810119Snilay@cs.wisc.edu } 12910119Snilay@cs.wisc.edu 13010119Snilay@cs.wisc.edu return fault; 13110119Snilay@cs.wisc.edu } 13210119Snilay@cs.wisc.edu}}; 13310119Snilay@cs.wisc.edu 13410119Snilay@cs.wisc.edudef template LoadExecute {{ 13510119Snilay@cs.wisc.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 13610119Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 13710119Snilay@cs.wisc.edu { 13810119Snilay@cs.wisc.edu Addr EA; 13910119Snilay@cs.wisc.edu Fault fault = NoFault; 14010119Snilay@cs.wisc.edu 14110119Snilay@cs.wisc.edu %(op_decl)s; 14210119Snilay@cs.wisc.edu %(op_rd)s; 14310119Snilay@cs.wisc.edu %(ea_code)s; 14410119Snilay@cs.wisc.edu 14510119Snilay@cs.wisc.edu if (%(predicate_test)s) 14610119Snilay@cs.wisc.edu { 14710119Snilay@cs.wisc.edu if (fault == NoFault) { 14810119Snilay@cs.wisc.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 14910119Snilay@cs.wisc.edu %(memacc_code)s; 15010119Snilay@cs.wisc.edu } 15110119Snilay@cs.wisc.edu 15210119Snilay@cs.wisc.edu if (fault == NoFault) { 15310119Snilay@cs.wisc.edu %(op_wb)s; 15410519Snilay@cs.wisc.edu } 15510519Snilay@cs.wisc.edu } 15610119Snilay@cs.wisc.edu 15710119Snilay@cs.wisc.edu return fault; 15810119Snilay@cs.wisc.edu } 15910119Snilay@cs.wisc.edu}}; 16010119Snilay@cs.wisc.edu 16110547Snilay@cs.wisc.edudef template StoreExecute {{ 16210547Snilay@cs.wisc.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 16310547Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 16410547Snilay@cs.wisc.edu { 16510119Snilay@cs.wisc.edu Addr EA; 16610119Snilay@cs.wisc.edu Fault fault = NoFault; 16710119Snilay@cs.wisc.edu 16810119Snilay@cs.wisc.edu %(op_decl)s; 16910119Snilay@cs.wisc.edu %(op_rd)s; 17010119Snilay@cs.wisc.edu %(ea_code)s; 17110119Snilay@cs.wisc.edu 17210119Snilay@cs.wisc.edu if (%(predicate_test)s) 17310120Snilay@cs.wisc.edu { 17410120Snilay@cs.wisc.edu if (fault == NoFault) { 17510119Snilay@cs.wisc.edu %(memacc_code)s; 17611598Sandreas.sandberg@arm.com } 17710120Snilay@cs.wisc.edu 17810120Snilay@cs.wisc.edu if (fault == NoFault) { 17910119Snilay@cs.wisc.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 18011598Sandreas.sandberg@arm.com memAccessFlags, NULL); 18111150Smitch.hayenga@arm.com if (traceData) { traceData->setData(Mem); } 18211150Smitch.hayenga@arm.com } 18311150Smitch.hayenga@arm.com 18410119Snilay@cs.wisc.edu if (fault == NoFault) { 1852995SN/A %(op_wb)s; 18610119Snilay@cs.wisc.edu } 18710119Snilay@cs.wisc.edu } 18810119Snilay@cs.wisc.edu 18910119Snilay@cs.wisc.edu return fault; 19010119Snilay@cs.wisc.edu } 19110780SCurtis.Dunham@arm.com}}; 19210119Snilay@cs.wisc.edu 19310119Snilay@cs.wisc.edudef template StoreInitiateAcc {{ 19410119Snilay@cs.wisc.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1953304Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 19610119Snilay@cs.wisc.edu { 19710119Snilay@cs.wisc.edu Addr EA; 19810119Snilay@cs.wisc.edu Fault fault = NoFault; 19910119Snilay@cs.wisc.edu 20010119Snilay@cs.wisc.edu %(op_decl)s; 20110119Snilay@cs.wisc.edu %(op_rd)s; 2026135Sgblack@eecs.umich.edu %(ea_code)s; 20310608Sdam.sunwoo@arm.com 20410608Sdam.sunwoo@arm.com if (%(predicate_test)s) 20510608Sdam.sunwoo@arm.com { 20610608Sdam.sunwoo@arm.com if (fault == NoFault) { 20710608Sdam.sunwoo@arm.com %(memacc_code)s; 20810608Sdam.sunwoo@arm.com } 20910608Sdam.sunwoo@arm.com 21010119Snilay@cs.wisc.edu if (fault == NoFault) { 21110119Snilay@cs.wisc.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 21210119Snilay@cs.wisc.edu memAccessFlags, NULL); 21310608Sdam.sunwoo@arm.com if (traceData) { traceData->setData(Mem); } 21410608Sdam.sunwoo@arm.com } 21510119Snilay@cs.wisc.edu 21610119Snilay@cs.wisc.edu // Need to write back any potential address register update 21710119Snilay@cs.wisc.edu if (fault == NoFault) { 2183819Shsul@eecs.umich.edu %(op_wb)s; 21911251Sradhika.jagtap@ARM.com } 22011251Sradhika.jagtap@ARM.com } 22111251Sradhika.jagtap@ARM.com 22211251Sradhika.jagtap@ARM.com return fault; 22311251Sradhika.jagtap@ARM.com } 22411251Sradhika.jagtap@ARM.com}}; 22511251Sradhika.jagtap@ARM.com 22611251Sradhika.jagtap@ARM.comdef template LoadInitiateAcc {{ 22711251Sradhika.jagtap@ARM.com Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 22811251Sradhika.jagtap@ARM.com Trace::InstRecord *traceData) const 22911251Sradhika.jagtap@ARM.com { 23010119Snilay@cs.wisc.edu Addr EA; 23111183Serfan.azarkhish@unibo.it Fault fault = NoFault; 23210119Snilay@cs.wisc.edu 23310118Snilay@cs.wisc.edu %(op_src_decl)s; 23410119Snilay@cs.wisc.edu %(op_rd)s; 2359827Sakash.bagdia@arm.com %(ea_code)s; 23610119Snilay@cs.wisc.edu 23710119Snilay@cs.wisc.edu if (%(predicate_test)s) 23810119Snilay@cs.wisc.edu { 23910119Snilay@cs.wisc.edu if (fault == NoFault) { 24010119Snilay@cs.wisc.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 24110119Snilay@cs.wisc.edu } 2429827Sakash.bagdia@arm.com } 24310594Sgabeblack@google.com 2446654Snate@binkert.org return fault; 24510594Sgabeblack@google.com } 2466654Snate@binkert.org}}; 24710594Sgabeblack@google.com 2486654Snate@binkert.orgdef template LoadCompleteAcc {{ 24910594Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 2506654Snate@binkert.org %(CPU_exec_context)s *xc, 25110594Sgabeblack@google.com Trace::InstRecord *traceData) const 25210594Sgabeblack@google.com { 2537586SAli.Saidi@arm.com Fault fault = NoFault; 25410635Satgutier@umich.edu 25510635Satgutier@umich.edu %(op_decl)s; 2568661SAli.Saidi@ARM.com %(op_rd)s; 2579827Sakash.bagdia@arm.com 2589827Sakash.bagdia@arm.com if (%(predicate_test)s) 2599827Sakash.bagdia@arm.com { 2609793Sakash.bagdia@arm.com // ARM instructions will not have a pkt if the predicate is false 26110119Snilay@cs.wisc.edu Mem = pkt->get<typeof(Mem)>(); 26210119Snilay@cs.wisc.edu 2639790Sakash.bagdia@arm.com if (fault == NoFault) { 2649827Sakash.bagdia@arm.com %(memacc_code)s; 2659827Sakash.bagdia@arm.com } 2669827Sakash.bagdia@arm.com 2679793Sakash.bagdia@arm.com if (fault == NoFault) { 2689827Sakash.bagdia@arm.com %(op_wb)s; 2699827Sakash.bagdia@arm.com } 2709827Sakash.bagdia@arm.com } 2719793Sakash.bagdia@arm.com 2729793Sakash.bagdia@arm.com return fault; 2739793Sakash.bagdia@arm.com } 2749384SAndreas.Sandberg@arm.com}}; 2758863Snilay@cs.wisc.edu 2767876Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 2774968Sacolyte@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2788926Sandreas.hansson@arm.com %(CPU_exec_context)s *xc, 2794837Ssaidi@eecs.umich.edu Trace::InstRecord *traceData) const 2804837Ssaidi@eecs.umich.edu { 2819408Sandreas.hansson@arm.com Fault fault = NoFault; 2829653SAndreas.Sandberg@ARM.com 2839653SAndreas.Sandberg@ARM.com %(op_decl)s; 2849653SAndreas.Sandberg@ARM.com %(op_rd)s; 2859164Sandreas.hansson@arm.com 2869408Sandreas.hansson@arm.com if (%(predicate_test)s) 2878845Sandreas.hansson@arm.com { 2888845Sandreas.hansson@arm.com if (fault == NoFault) { 2894837Ssaidi@eecs.umich.edu %(op_wb)s; 2909826Sandreas.hansson@arm.com } 2919826Sandreas.hansson@arm.com } 2929835Sandreas.hansson@arm.com 2939826Sandreas.hansson@arm.com return fault; 2949826Sandreas.hansson@arm.com } 2959826Sandreas.hansson@arm.com}}; 2969826Sandreas.hansson@arm.com 2978659SAli.Saidi@ARM.comdef template SwapDeclare {{ 29810119Snilay@cs.wisc.edu /** 29910119Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 30010119Snilay@cs.wisc.edu */ 30110119Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 30210119Snilay@cs.wisc.edu { 30310119Snilay@cs.wisc.edu public: 30410119Snilay@cs.wisc.edu 30510119Snilay@cs.wisc.edu /// Constructor. 30610119Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 30710119Snilay@cs.wisc.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 30810119Snilay@cs.wisc.edu 30910119Snilay@cs.wisc.edu %(BasicExecDeclare)s 31010119Snilay@cs.wisc.edu 31110119Snilay@cs.wisc.edu %(InitiateAccDeclare)s 31210119Snilay@cs.wisc.edu 31310119Snilay@cs.wisc.edu %(CompleteAccDeclare)s 31410119Snilay@cs.wisc.edu }; 31510119Snilay@cs.wisc.edu}}; 31610119Snilay@cs.wisc.edu 31710119Snilay@cs.wisc.edudef template LoadStoreDImmDeclare {{ 31810119Snilay@cs.wisc.edu /** 31910119Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 32010119Snilay@cs.wisc.edu */ 32110119Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 32210119Snilay@cs.wisc.edu { 32310119Snilay@cs.wisc.edu public: 32410119Snilay@cs.wisc.edu 32510119Snilay@cs.wisc.edu /// Constructor. 32610119Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 32710119Snilay@cs.wisc.edu uint32_t _dest, uint32_t _dest2, 32810119Snilay@cs.wisc.edu uint32_t _base, bool _add, int32_t _imm); 32910119Snilay@cs.wisc.edu 33010119Snilay@cs.wisc.edu %(BasicExecDeclare)s 33110697SCurtis.Dunham@arm.com 33210747SChris.Emmons@arm.com %(InitiateAccDeclare)s 33310697SCurtis.Dunham@arm.com 33410747SChris.Emmons@arm.com %(CompleteAccDeclare)s 33510119Snilay@cs.wisc.edu }; 33610697SCurtis.Dunham@arm.com}}; 33710747SChris.Emmons@arm.com 33810119Snilay@cs.wisc.edudef template LoadStoreImmDeclare {{ 33910119Snilay@cs.wisc.edu /** 34010119Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 34110119Snilay@cs.wisc.edu */ 34210119Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 34310119Snilay@cs.wisc.edu { 3448801Sgblack@eecs.umich.edu public: 34511291Sgabor.dozsa@arm.com 34611291Sgabor.dozsa@arm.com /// Constructor. 34711291Sgabor.dozsa@arm.com %(class_name)s(ExtMachInst machInst, 34811291Sgabor.dozsa@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 34911291Sgabor.dozsa@arm.com 35011291Sgabor.dozsa@arm.com %(BasicExecDeclare)s 35111291Sgabor.dozsa@arm.com 35211291Sgabor.dozsa@arm.com %(InitiateAccDeclare)s 35311291Sgabor.dozsa@arm.com 35411291Sgabor.dozsa@arm.com %(CompleteAccDeclare)s 35511291Sgabor.dozsa@arm.com }; 35611291Sgabor.dozsa@arm.com}}; 3573005Sstever@eecs.umich.edu 3588801Sgblack@eecs.umich.edudef template LoadStoreDRegDeclare {{ 3593005Sstever@eecs.umich.edu /** 3603005Sstever@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 3613005Sstever@eecs.umich.edu */ 3622566SN/A class %(class_name)s : public %(base_class)s 3637861Sgblack@eecs.umich.edu { 3647861Sgblack@eecs.umich.edu public: 3657861Sgblack@eecs.umich.edu 3668635Schris.emmons@arm.com /// Constructor. 3678635Schris.emmons@arm.com %(class_name)s(ExtMachInst machInst, 3688635Schris.emmons@arm.com uint32_t _dest, uint32_t _dest2, 3699061Snilay@cs.wisc.edu uint32_t _base, bool _add, 3703481Shsul@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 371 uint32_t _index); 372 373 %(BasicExecDeclare)s 374 375 %(InitiateAccDeclare)s 376 377 %(CompleteAccDeclare)s 378 }; 379}}; 380 381def template LoadStoreRegDeclare {{ 382 /** 383 * Static instruction class for "%(mnemonic)s". 384 */ 385 class %(class_name)s : public %(base_class)s 386 { 387 public: 388 389 /// Constructor. 390 %(class_name)s(ExtMachInst machInst, 391 uint32_t _dest, uint32_t _base, bool _add, 392 int32_t _shiftAmt, uint32_t _shiftType, 393 uint32_t _index); 394 395 %(BasicExecDeclare)s 396 397 %(InitiateAccDeclare)s 398 399 %(CompleteAccDeclare)s 400 }; 401}}; 402 403def template InitiateAccDeclare {{ 404 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 405}}; 406 407def template CompleteAccDeclare {{ 408 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 409}}; 410 411def template SwapConstructor {{ 412 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 413 uint32_t _dest, uint32_t _op1, uint32_t _base) 414 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 415 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 416 { 417 %(constructor)s; 418 } 419}}; 420 421def template LoadStoreDImmConstructor {{ 422 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 423 uint32_t _dest, uint32_t _dest2, 424 uint32_t _base, bool _add, int32_t _imm) 425 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 426 (IntRegIndex)_dest, (IntRegIndex)_dest2, 427 (IntRegIndex)_base, _add, _imm) 428 { 429 %(constructor)s; 430 } 431}}; 432 433def template LoadStoreImmConstructor {{ 434 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 435 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 436 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 437 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 438 { 439 %(constructor)s; 440 } 441}}; 442 443def template LoadStoreDRegConstructor {{ 444 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 445 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 446 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 447 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 448 (IntRegIndex)_dest, (IntRegIndex)_dest2, 449 (IntRegIndex)_base, _add, 450 _shiftAmt, (ArmShiftType)_shiftType, 451 (IntRegIndex)_index) 452 { 453 %(constructor)s; 454 } 455}}; 456 457def template LoadStoreRegConstructor {{ 458 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 459 uint32_t _dest, uint32_t _base, bool _add, 460 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 461 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 462 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 463 _shiftAmt, (ArmShiftType)_shiftType, 464 (IntRegIndex)_index) 465 { 466 %(constructor)s; 467 } 468}}; 469