mem.isa revision 7119
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 47119Sgblack@eecs.umich.edu// All rights reserved. 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 77119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 87119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 97119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 107119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 117119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 127119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 137119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 147119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 157119Sgblack@eecs.umich.edu// this software without specific prior written permission. 167119Sgblack@eecs.umich.edu// 177119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// Authors: Stephen Hines 307119Sgblack@eecs.umich.edu 317119Sgblack@eecs.umich.edu 327119Sgblack@eecs.umich.edudef template LoadExecute {{ 337119Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 347119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 357119Sgblack@eecs.umich.edu { 367119Sgblack@eecs.umich.edu Addr EA; 377119Sgblack@eecs.umich.edu Fault fault = NoFault; 387119Sgblack@eecs.umich.edu 397119Sgblack@eecs.umich.edu %(op_decl)s; 407119Sgblack@eecs.umich.edu %(op_rd)s; 417119Sgblack@eecs.umich.edu %(ea_code)s; 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu if (%(predicate_test)s) 447119Sgblack@eecs.umich.edu { 457119Sgblack@eecs.umich.edu if (fault == NoFault) { 467119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 477119Sgblack@eecs.umich.edu %(memacc_code)s; 487119Sgblack@eecs.umich.edu } 497119Sgblack@eecs.umich.edu 507119Sgblack@eecs.umich.edu if (fault == NoFault) { 517119Sgblack@eecs.umich.edu %(op_wb)s; 527119Sgblack@eecs.umich.edu } 537119Sgblack@eecs.umich.edu } 547119Sgblack@eecs.umich.edu 557119Sgblack@eecs.umich.edu return fault; 567119Sgblack@eecs.umich.edu } 577119Sgblack@eecs.umich.edu}}; 587119Sgblack@eecs.umich.edu 597119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 607119Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 617119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 627119Sgblack@eecs.umich.edu { 637119Sgblack@eecs.umich.edu Addr EA; 647119Sgblack@eecs.umich.edu Fault fault = NoFault; 657119Sgblack@eecs.umich.edu 667119Sgblack@eecs.umich.edu %(op_src_decl)s; 677119Sgblack@eecs.umich.edu %(op_rd)s; 687119Sgblack@eecs.umich.edu %(ea_code)s; 697119Sgblack@eecs.umich.edu 707119Sgblack@eecs.umich.edu if (%(predicate_test)s) 717119Sgblack@eecs.umich.edu { 727119Sgblack@eecs.umich.edu if (fault == NoFault) { 737119Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 747119Sgblack@eecs.umich.edu } 757119Sgblack@eecs.umich.edu } 767119Sgblack@eecs.umich.edu 777119Sgblack@eecs.umich.edu return fault; 787119Sgblack@eecs.umich.edu } 797119Sgblack@eecs.umich.edu}}; 807119Sgblack@eecs.umich.edu 817119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 827119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 837119Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 847119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 857119Sgblack@eecs.umich.edu { 867119Sgblack@eecs.umich.edu Fault fault = NoFault; 877119Sgblack@eecs.umich.edu 887119Sgblack@eecs.umich.edu %(op_decl)s; 897119Sgblack@eecs.umich.edu %(op_rd)s; 907119Sgblack@eecs.umich.edu 917119Sgblack@eecs.umich.edu if (%(predicate_test)s) 927119Sgblack@eecs.umich.edu { 937119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 947119Sgblack@eecs.umich.edu Mem = pkt->get<typeof(Mem)>(); 957119Sgblack@eecs.umich.edu 967119Sgblack@eecs.umich.edu if (fault == NoFault) { 977119Sgblack@eecs.umich.edu %(memacc_code)s; 987119Sgblack@eecs.umich.edu } 997119Sgblack@eecs.umich.edu 1007119Sgblack@eecs.umich.edu if (fault == NoFault) { 1017119Sgblack@eecs.umich.edu %(op_wb)s; 1027119Sgblack@eecs.umich.edu } 1037119Sgblack@eecs.umich.edu } 1047119Sgblack@eecs.umich.edu 1057119Sgblack@eecs.umich.edu return fault; 1067119Sgblack@eecs.umich.edu } 1077119Sgblack@eecs.umich.edu}}; 1087119Sgblack@eecs.umich.edu 1097119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 1107119Sgblack@eecs.umich.edu /** 1117119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 1127119Sgblack@eecs.umich.edu */ 1137119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1147119Sgblack@eecs.umich.edu { 1157119Sgblack@eecs.umich.edu public: 1167119Sgblack@eecs.umich.edu 1177119Sgblack@eecs.umich.edu /// Constructor. 1187119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1197119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 1207119Sgblack@eecs.umich.edu 1217119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1227119Sgblack@eecs.umich.edu 1237119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1247119Sgblack@eecs.umich.edu 1257119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1267119Sgblack@eecs.umich.edu }; 1277119Sgblack@eecs.umich.edu}}; 1287119Sgblack@eecs.umich.edu 1297119Sgblack@eecs.umich.edudef template LoadStoreRegDeclare {{ 1307119Sgblack@eecs.umich.edu /** 1317119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 1327119Sgblack@eecs.umich.edu */ 1337119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1347119Sgblack@eecs.umich.edu { 1357119Sgblack@eecs.umich.edu public: 1367119Sgblack@eecs.umich.edu 1377119Sgblack@eecs.umich.edu /// Constructor. 1387119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1397119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 1407119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 1417119Sgblack@eecs.umich.edu uint32_t _index); 1427119Sgblack@eecs.umich.edu 1437119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1447119Sgblack@eecs.umich.edu 1457119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1467119Sgblack@eecs.umich.edu 1477119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1487119Sgblack@eecs.umich.edu }; 1497119Sgblack@eecs.umich.edu}}; 1507119Sgblack@eecs.umich.edu 1517119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 1527119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1537119Sgblack@eecs.umich.edu}}; 1547119Sgblack@eecs.umich.edu 1557119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 1567119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1577119Sgblack@eecs.umich.edu}}; 1587119Sgblack@eecs.umich.edu 1597119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 1607119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1617119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1627119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1637119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1647119Sgblack@eecs.umich.edu { 1657119Sgblack@eecs.umich.edu %(constructor)s; 1667119Sgblack@eecs.umich.edu } 1677119Sgblack@eecs.umich.edu}}; 1687119Sgblack@eecs.umich.edu 1697119Sgblack@eecs.umich.edudef template LoadStoreRegConstructor {{ 1707119Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1717119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 1727119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1737119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1747119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 1757119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 1767119Sgblack@eecs.umich.edu (IntRegIndex)_index) 1777119Sgblack@eecs.umich.edu { 1787119Sgblack@eecs.umich.edu %(constructor)s; 1797119Sgblack@eecs.umich.edu } 1807119Sgblack@eecs.umich.edu}}; 181