mem.isa revision 12234
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 312110SRekai.GonzalezAlberquilla@arm.com// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 4512234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 5412234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 6312234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 647646Sgene.wu@arm.com Trace::InstRecord *traceData) const 657646Sgene.wu@arm.com { 667646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 677646Sgene.wu@arm.com return NoFault; 687646Sgene.wu@arm.com } 697646Sgene.wu@arm.com}}; 707646Sgene.wu@arm.com 717646Sgene.wu@arm.com 727205Sgblack@eecs.umich.edudef template SwapExecute {{ 7312234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 747205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 757205Sgblack@eecs.umich.edu { 767205Sgblack@eecs.umich.edu Addr EA; 777205Sgblack@eecs.umich.edu Fault fault = NoFault; 787205Sgblack@eecs.umich.edu 797205Sgblack@eecs.umich.edu %(op_decl)s; 807205Sgblack@eecs.umich.edu uint64_t memData = 0; 817205Sgblack@eecs.umich.edu %(op_rd)s; 827205Sgblack@eecs.umich.edu %(ea_code)s; 837205Sgblack@eecs.umich.edu 847205Sgblack@eecs.umich.edu if (%(predicate_test)s) 857205Sgblack@eecs.umich.edu { 867205Sgblack@eecs.umich.edu %(preacc_code)s; 877205Sgblack@eecs.umich.edu 887205Sgblack@eecs.umich.edu if (fault == NoFault) { 898442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 908442Sgblack@eecs.umich.edu &memData); 917205Sgblack@eecs.umich.edu } 927205Sgblack@eecs.umich.edu 937205Sgblack@eecs.umich.edu if (fault == NoFault) { 947205Sgblack@eecs.umich.edu %(postacc_code)s; 957205Sgblack@eecs.umich.edu } 967205Sgblack@eecs.umich.edu 977205Sgblack@eecs.umich.edu if (fault == NoFault) { 987205Sgblack@eecs.umich.edu %(op_wb)s; 997205Sgblack@eecs.umich.edu } 1007597Sminkyu.jeong@arm.com } else { 1017597Sminkyu.jeong@arm.com xc->setPredicate(false); 1027205Sgblack@eecs.umich.edu } 1037205Sgblack@eecs.umich.edu 1047205Sgblack@eecs.umich.edu return fault; 1057205Sgblack@eecs.umich.edu } 1067205Sgblack@eecs.umich.edu}}; 1077205Sgblack@eecs.umich.edu 1087205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 10912234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 1107205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1117205Sgblack@eecs.umich.edu { 1127205Sgblack@eecs.umich.edu Addr EA; 1137205Sgblack@eecs.umich.edu Fault fault = NoFault; 1147205Sgblack@eecs.umich.edu 1157205Sgblack@eecs.umich.edu %(op_decl)s; 1167205Sgblack@eecs.umich.edu uint64_t memData = 0; 1177205Sgblack@eecs.umich.edu %(op_rd)s; 1187205Sgblack@eecs.umich.edu %(ea_code)s; 1197205Sgblack@eecs.umich.edu 1207205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1217205Sgblack@eecs.umich.edu { 1227205Sgblack@eecs.umich.edu %(preacc_code)s; 1237205Sgblack@eecs.umich.edu 1247205Sgblack@eecs.umich.edu if (fault == NoFault) { 1258442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1268442Sgblack@eecs.umich.edu &memData); 1277205Sgblack@eecs.umich.edu } 1287597Sminkyu.jeong@arm.com } else { 1297597Sminkyu.jeong@arm.com xc->setPredicate(false); 1307205Sgblack@eecs.umich.edu } 1317205Sgblack@eecs.umich.edu 1327205Sgblack@eecs.umich.edu return fault; 1337205Sgblack@eecs.umich.edu } 1347205Sgblack@eecs.umich.edu}}; 1357205Sgblack@eecs.umich.edu 1367205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 13712234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 1387205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1397205Sgblack@eecs.umich.edu { 1407205Sgblack@eecs.umich.edu Fault fault = NoFault; 1417205Sgblack@eecs.umich.edu 1427205Sgblack@eecs.umich.edu %(op_decl)s; 1437205Sgblack@eecs.umich.edu %(op_rd)s; 1447205Sgblack@eecs.umich.edu 1457205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1467205Sgblack@eecs.umich.edu { 1477205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1488442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1498442Sgblack@eecs.umich.edu uint64_t memData = Mem; 1507205Sgblack@eecs.umich.edu 1517205Sgblack@eecs.umich.edu %(postacc_code)s; 1527205Sgblack@eecs.umich.edu 1537205Sgblack@eecs.umich.edu if (fault == NoFault) { 1547205Sgblack@eecs.umich.edu %(op_wb)s; 1557205Sgblack@eecs.umich.edu } 1567205Sgblack@eecs.umich.edu } 1577205Sgblack@eecs.umich.edu 1587205Sgblack@eecs.umich.edu return fault; 1597205Sgblack@eecs.umich.edu } 1607205Sgblack@eecs.umich.edu}}; 1617205Sgblack@eecs.umich.edu 1627119Sgblack@eecs.umich.edudef template LoadExecute {{ 16312234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 1647119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1657119Sgblack@eecs.umich.edu { 1667119Sgblack@eecs.umich.edu Addr EA; 1677119Sgblack@eecs.umich.edu Fault fault = NoFault; 1687119Sgblack@eecs.umich.edu 1697119Sgblack@eecs.umich.edu %(op_decl)s; 1707119Sgblack@eecs.umich.edu %(op_rd)s; 1717119Sgblack@eecs.umich.edu %(ea_code)s; 1727119Sgblack@eecs.umich.edu 1737119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1747119Sgblack@eecs.umich.edu { 1757119Sgblack@eecs.umich.edu if (fault == NoFault) { 1768442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1777119Sgblack@eecs.umich.edu %(memacc_code)s; 1787119Sgblack@eecs.umich.edu } 1797119Sgblack@eecs.umich.edu 1807119Sgblack@eecs.umich.edu if (fault == NoFault) { 1817119Sgblack@eecs.umich.edu %(op_wb)s; 1827119Sgblack@eecs.umich.edu } 1837597Sminkyu.jeong@arm.com } else { 1847597Sminkyu.jeong@arm.com xc->setPredicate(false); 1857119Sgblack@eecs.umich.edu } 1867119Sgblack@eecs.umich.edu 1877119Sgblack@eecs.umich.edu return fault; 1887119Sgblack@eecs.umich.edu } 1897119Sgblack@eecs.umich.edu}}; 1907119Sgblack@eecs.umich.edu 1917639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1927639Sgblack@eecs.umich.edu template <class Element> 1937639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 19412234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 1957639Sgblack@eecs.umich.edu { 1967639Sgblack@eecs.umich.edu Addr EA; 1977639Sgblack@eecs.umich.edu Fault fault = NoFault; 1987639Sgblack@eecs.umich.edu 1997639Sgblack@eecs.umich.edu %(op_decl)s; 2007639Sgblack@eecs.umich.edu %(mem_decl)s; 2017639Sgblack@eecs.umich.edu %(op_rd)s; 2027639Sgblack@eecs.umich.edu %(ea_code)s; 2037639Sgblack@eecs.umich.edu 2047639Sgblack@eecs.umich.edu MemUnion memUnion; 2057639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2067639Sgblack@eecs.umich.edu 2077639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2087639Sgblack@eecs.umich.edu { 2097639Sgblack@eecs.umich.edu if (fault == NoFault) { 2108444Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 2117639Sgblack@eecs.umich.edu %(memacc_code)s; 2127639Sgblack@eecs.umich.edu } 2137639Sgblack@eecs.umich.edu 2147639Sgblack@eecs.umich.edu if (fault == NoFault) { 2157639Sgblack@eecs.umich.edu %(op_wb)s; 2167639Sgblack@eecs.umich.edu } 2178072SGiacomo.Gabrielli@arm.com } else { 2188072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2197639Sgblack@eecs.umich.edu } 2207639Sgblack@eecs.umich.edu 2217639Sgblack@eecs.umich.edu return fault; 2227639Sgblack@eecs.umich.edu } 2237639Sgblack@eecs.umich.edu}}; 2247639Sgblack@eecs.umich.edu 2257120Sgblack@eecs.umich.edudef template StoreExecute {{ 22612234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2277120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2287120Sgblack@eecs.umich.edu { 2297120Sgblack@eecs.umich.edu Addr EA; 2307120Sgblack@eecs.umich.edu Fault fault = NoFault; 2317120Sgblack@eecs.umich.edu 2327120Sgblack@eecs.umich.edu %(op_decl)s; 2337120Sgblack@eecs.umich.edu %(op_rd)s; 2347120Sgblack@eecs.umich.edu %(ea_code)s; 2357120Sgblack@eecs.umich.edu 2367120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2377120Sgblack@eecs.umich.edu { 2387120Sgblack@eecs.umich.edu if (fault == NoFault) { 2397120Sgblack@eecs.umich.edu %(memacc_code)s; 2407120Sgblack@eecs.umich.edu } 2417120Sgblack@eecs.umich.edu 2427120Sgblack@eecs.umich.edu if (fault == NoFault) { 2438442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2448442Sgblack@eecs.umich.edu memAccessFlags, NULL); 2457120Sgblack@eecs.umich.edu } 2467120Sgblack@eecs.umich.edu 2477120Sgblack@eecs.umich.edu if (fault == NoFault) { 2487120Sgblack@eecs.umich.edu %(op_wb)s; 2497120Sgblack@eecs.umich.edu } 2507597Sminkyu.jeong@arm.com } else { 2517597Sminkyu.jeong@arm.com xc->setPredicate(false); 2527120Sgblack@eecs.umich.edu } 2537120Sgblack@eecs.umich.edu 2547120Sgblack@eecs.umich.edu return fault; 2557120Sgblack@eecs.umich.edu } 2567120Sgblack@eecs.umich.edu}}; 2577120Sgblack@eecs.umich.edu 2587639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2597639Sgblack@eecs.umich.edu template <class Element> 2607639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 26112234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 2627639Sgblack@eecs.umich.edu { 2637639Sgblack@eecs.umich.edu Addr EA; 2647639Sgblack@eecs.umich.edu Fault fault = NoFault; 2657639Sgblack@eecs.umich.edu 2667639Sgblack@eecs.umich.edu %(op_decl)s; 2677639Sgblack@eecs.umich.edu %(mem_decl)s; 2687639Sgblack@eecs.umich.edu %(op_rd)s; 2697639Sgblack@eecs.umich.edu %(ea_code)s; 2707639Sgblack@eecs.umich.edu 2717639Sgblack@eecs.umich.edu MemUnion memUnion; 2727639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2737639Sgblack@eecs.umich.edu 2747639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2757639Sgblack@eecs.umich.edu { 2767639Sgblack@eecs.umich.edu if (fault == NoFault) { 2777639Sgblack@eecs.umich.edu %(memacc_code)s; 2787639Sgblack@eecs.umich.edu } 2797639Sgblack@eecs.umich.edu 2807639Sgblack@eecs.umich.edu if (fault == NoFault) { 2818444Sgblack@eecs.umich.edu fault = xc->writeMem(dataPtr, %(size)d, EA, 2828444Sgblack@eecs.umich.edu memAccessFlags, NULL); 2837639Sgblack@eecs.umich.edu } 2847639Sgblack@eecs.umich.edu 2857639Sgblack@eecs.umich.edu if (fault == NoFault) { 2867639Sgblack@eecs.umich.edu %(op_wb)s; 2877639Sgblack@eecs.umich.edu } 2888072SGiacomo.Gabrielli@arm.com } else { 2898072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2907639Sgblack@eecs.umich.edu } 2917639Sgblack@eecs.umich.edu 2927639Sgblack@eecs.umich.edu return fault; 2937639Sgblack@eecs.umich.edu } 2947639Sgblack@eecs.umich.edu}}; 2957639Sgblack@eecs.umich.edu 2967303Sgblack@eecs.umich.edudef template StoreExExecute {{ 29712234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2987303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2997303Sgblack@eecs.umich.edu { 3007303Sgblack@eecs.umich.edu Addr EA; 3017303Sgblack@eecs.umich.edu Fault fault = NoFault; 3027303Sgblack@eecs.umich.edu 3037303Sgblack@eecs.umich.edu %(op_decl)s; 3047303Sgblack@eecs.umich.edu %(op_rd)s; 3057303Sgblack@eecs.umich.edu %(ea_code)s; 3067303Sgblack@eecs.umich.edu 3077303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3087303Sgblack@eecs.umich.edu { 3097303Sgblack@eecs.umich.edu if (fault == NoFault) { 3107303Sgblack@eecs.umich.edu %(memacc_code)s; 3117303Sgblack@eecs.umich.edu } 3127303Sgblack@eecs.umich.edu 3137303Sgblack@eecs.umich.edu uint64_t writeResult; 3147303Sgblack@eecs.umich.edu 3157303Sgblack@eecs.umich.edu if (fault == NoFault) { 3168442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3178442Sgblack@eecs.umich.edu &writeResult); 3187303Sgblack@eecs.umich.edu } 3197303Sgblack@eecs.umich.edu 3207303Sgblack@eecs.umich.edu if (fault == NoFault) { 3217303Sgblack@eecs.umich.edu %(postacc_code)s; 3227303Sgblack@eecs.umich.edu } 3237303Sgblack@eecs.umich.edu 3247303Sgblack@eecs.umich.edu if (fault == NoFault) { 3257303Sgblack@eecs.umich.edu %(op_wb)s; 3267303Sgblack@eecs.umich.edu } 3277597Sminkyu.jeong@arm.com } else { 3287597Sminkyu.jeong@arm.com xc->setPredicate(false); 3297303Sgblack@eecs.umich.edu } 3307303Sgblack@eecs.umich.edu 3317303Sgblack@eecs.umich.edu return fault; 3327303Sgblack@eecs.umich.edu } 3337303Sgblack@eecs.umich.edu}}; 3347303Sgblack@eecs.umich.edu 3357303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 33612234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3377303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3387303Sgblack@eecs.umich.edu { 3397303Sgblack@eecs.umich.edu Addr EA; 3407303Sgblack@eecs.umich.edu Fault fault = NoFault; 3417303Sgblack@eecs.umich.edu 3427303Sgblack@eecs.umich.edu %(op_decl)s; 3437303Sgblack@eecs.umich.edu %(op_rd)s; 3447303Sgblack@eecs.umich.edu %(ea_code)s; 3457303Sgblack@eecs.umich.edu 3467303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3477303Sgblack@eecs.umich.edu { 3487303Sgblack@eecs.umich.edu if (fault == NoFault) { 3497303Sgblack@eecs.umich.edu %(memacc_code)s; 3507303Sgblack@eecs.umich.edu } 3517303Sgblack@eecs.umich.edu 3527303Sgblack@eecs.umich.edu if (fault == NoFault) { 3538442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3548442Sgblack@eecs.umich.edu NULL); 3557303Sgblack@eecs.umich.edu } 3567597Sminkyu.jeong@arm.com } else { 3577597Sminkyu.jeong@arm.com xc->setPredicate(false); 3587303Sgblack@eecs.umich.edu } 3597408Sgblack@eecs.umich.edu 3607303Sgblack@eecs.umich.edu return fault; 3617303Sgblack@eecs.umich.edu } 3627303Sgblack@eecs.umich.edu}}; 3637303Sgblack@eecs.umich.edu 3647120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 36512234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3667120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3677120Sgblack@eecs.umich.edu { 3687120Sgblack@eecs.umich.edu Addr EA; 3697120Sgblack@eecs.umich.edu Fault fault = NoFault; 3707120Sgblack@eecs.umich.edu 3717120Sgblack@eecs.umich.edu %(op_decl)s; 3727120Sgblack@eecs.umich.edu %(op_rd)s; 3737120Sgblack@eecs.umich.edu %(ea_code)s; 3747120Sgblack@eecs.umich.edu 3757120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3767120Sgblack@eecs.umich.edu { 3777120Sgblack@eecs.umich.edu if (fault == NoFault) { 3787120Sgblack@eecs.umich.edu %(memacc_code)s; 3797120Sgblack@eecs.umich.edu } 3807120Sgblack@eecs.umich.edu 3817120Sgblack@eecs.umich.edu if (fault == NoFault) { 3828442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3838442Sgblack@eecs.umich.edu NULL); 3847120Sgblack@eecs.umich.edu } 3857597Sminkyu.jeong@arm.com } else { 3867597Sminkyu.jeong@arm.com xc->setPredicate(false); 3877120Sgblack@eecs.umich.edu } 3887120Sgblack@eecs.umich.edu 3897120Sgblack@eecs.umich.edu return fault; 3907120Sgblack@eecs.umich.edu } 3917120Sgblack@eecs.umich.edu}}; 3927120Sgblack@eecs.umich.edu 3937639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3947639Sgblack@eecs.umich.edu template <class Element> 3957639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 39612234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 3977639Sgblack@eecs.umich.edu { 3987639Sgblack@eecs.umich.edu Addr EA; 3997639Sgblack@eecs.umich.edu Fault fault = NoFault; 4007639Sgblack@eecs.umich.edu 4017639Sgblack@eecs.umich.edu %(op_decl)s; 4027639Sgblack@eecs.umich.edu %(mem_decl)s; 4037639Sgblack@eecs.umich.edu %(op_rd)s; 4047639Sgblack@eecs.umich.edu %(ea_code)s; 4057639Sgblack@eecs.umich.edu 4067639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4077639Sgblack@eecs.umich.edu { 4087639Sgblack@eecs.umich.edu MemUnion memUnion; 4097639Sgblack@eecs.umich.edu if (fault == NoFault) { 4107639Sgblack@eecs.umich.edu %(memacc_code)s; 4117639Sgblack@eecs.umich.edu } 4127639Sgblack@eecs.umich.edu 4137639Sgblack@eecs.umich.edu if (fault == NoFault) { 4148444Sgblack@eecs.umich.edu fault = xc->writeMem(memUnion.bytes, %(size)d, EA, 4158444Sgblack@eecs.umich.edu memAccessFlags, NULL); 4167639Sgblack@eecs.umich.edu } 4178072SGiacomo.Gabrielli@arm.com } else { 4188072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4197639Sgblack@eecs.umich.edu } 4207639Sgblack@eecs.umich.edu 4217639Sgblack@eecs.umich.edu return fault; 4227639Sgblack@eecs.umich.edu } 4237639Sgblack@eecs.umich.edu}}; 4247639Sgblack@eecs.umich.edu 4257119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 42612234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 4277119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4287119Sgblack@eecs.umich.edu { 4297119Sgblack@eecs.umich.edu Addr EA; 4307119Sgblack@eecs.umich.edu Fault fault = NoFault; 4317119Sgblack@eecs.umich.edu 4327119Sgblack@eecs.umich.edu %(op_src_decl)s; 4337119Sgblack@eecs.umich.edu %(op_rd)s; 4347119Sgblack@eecs.umich.edu %(ea_code)s; 4357119Sgblack@eecs.umich.edu 4367119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4377119Sgblack@eecs.umich.edu { 4387119Sgblack@eecs.umich.edu if (fault == NoFault) { 43911303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, 44011303Ssteve.reinhardt@amd.com memAccessFlags); 4417119Sgblack@eecs.umich.edu } 4427597Sminkyu.jeong@arm.com } else { 4437597Sminkyu.jeong@arm.com xc->setPredicate(false); 4447119Sgblack@eecs.umich.edu } 4457119Sgblack@eecs.umich.edu 4467119Sgblack@eecs.umich.edu return fault; 4477119Sgblack@eecs.umich.edu } 4487119Sgblack@eecs.umich.edu}}; 4497119Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4517639Sgblack@eecs.umich.edu template <class Element> 4527639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 45312234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 4547639Sgblack@eecs.umich.edu { 4557639Sgblack@eecs.umich.edu Addr EA; 4567639Sgblack@eecs.umich.edu Fault fault = NoFault; 4577639Sgblack@eecs.umich.edu 4588207SAli.Saidi@ARM.com %(op_decl)s; 4598207SAli.Saidi@ARM.com %(mem_decl)s; 4607639Sgblack@eecs.umich.edu %(op_rd)s; 4617639Sgblack@eecs.umich.edu %(ea_code)s; 4627639Sgblack@eecs.umich.edu 4637639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4647639Sgblack@eecs.umich.edu { 4657639Sgblack@eecs.umich.edu if (fault == NoFault) { 46611303Ssteve.reinhardt@amd.com fault = xc->initiateMemRead(EA, %(size)d, memAccessFlags); 4677639Sgblack@eecs.umich.edu } 4688072SGiacomo.Gabrielli@arm.com } else { 4698072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4707639Sgblack@eecs.umich.edu } 4717639Sgblack@eecs.umich.edu 4727639Sgblack@eecs.umich.edu return fault; 4737639Sgblack@eecs.umich.edu } 4747639Sgblack@eecs.umich.edu}}; 4757639Sgblack@eecs.umich.edu 4767119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 47712234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 4787119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4797119Sgblack@eecs.umich.edu { 4807119Sgblack@eecs.umich.edu Fault fault = NoFault; 4817119Sgblack@eecs.umich.edu 4827119Sgblack@eecs.umich.edu %(op_decl)s; 4837119Sgblack@eecs.umich.edu %(op_rd)s; 4847119Sgblack@eecs.umich.edu 4857119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4867119Sgblack@eecs.umich.edu { 4877119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4888442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 4897119Sgblack@eecs.umich.edu 4907119Sgblack@eecs.umich.edu if (fault == NoFault) { 4917119Sgblack@eecs.umich.edu %(memacc_code)s; 4927119Sgblack@eecs.umich.edu } 4937119Sgblack@eecs.umich.edu 4947119Sgblack@eecs.umich.edu if (fault == NoFault) { 4957119Sgblack@eecs.umich.edu %(op_wb)s; 4967119Sgblack@eecs.umich.edu } 4977119Sgblack@eecs.umich.edu } 4987119Sgblack@eecs.umich.edu 4997119Sgblack@eecs.umich.edu return fault; 5007119Sgblack@eecs.umich.edu } 5017119Sgblack@eecs.umich.edu}}; 5027119Sgblack@eecs.umich.edu 5037639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5047639Sgblack@eecs.umich.edu template <class Element> 5057639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 50612234Sgabeblack@google.com PacketPtr pkt, ExecContext *xc, 5077639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5087639Sgblack@eecs.umich.edu { 5097639Sgblack@eecs.umich.edu Fault fault = NoFault; 5107639Sgblack@eecs.umich.edu 5117639Sgblack@eecs.umich.edu %(mem_decl)s; 5127639Sgblack@eecs.umich.edu %(op_decl)s; 5137639Sgblack@eecs.umich.edu %(op_rd)s; 5147639Sgblack@eecs.umich.edu 5157639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5167639Sgblack@eecs.umich.edu { 5177639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5187639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5197639Sgblack@eecs.umich.edu 5207639Sgblack@eecs.umich.edu if (fault == NoFault) { 5217639Sgblack@eecs.umich.edu %(memacc_code)s; 5227639Sgblack@eecs.umich.edu } 5237639Sgblack@eecs.umich.edu 5247639Sgblack@eecs.umich.edu if (fault == NoFault) { 5257639Sgblack@eecs.umich.edu %(op_wb)s; 5267639Sgblack@eecs.umich.edu } 5277639Sgblack@eecs.umich.edu } 5287639Sgblack@eecs.umich.edu 5297639Sgblack@eecs.umich.edu return fault; 5307639Sgblack@eecs.umich.edu } 5317639Sgblack@eecs.umich.edu}}; 5327639Sgblack@eecs.umich.edu 5337120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 53412234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 5357120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5367120Sgblack@eecs.umich.edu { 5377712Sgblack@eecs.umich.edu return NoFault; 5387120Sgblack@eecs.umich.edu } 5397120Sgblack@eecs.umich.edu}}; 5407120Sgblack@eecs.umich.edu 5417639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5427639Sgblack@eecs.umich.edu template <class Element> 5437639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 54412234Sgabeblack@google.com PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const 5457639Sgblack@eecs.umich.edu { 5467712Sgblack@eecs.umich.edu return NoFault; 5477639Sgblack@eecs.umich.edu } 5487639Sgblack@eecs.umich.edu}}; 5497639Sgblack@eecs.umich.edu 5507303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 55112234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 5527303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5537303Sgblack@eecs.umich.edu { 5547303Sgblack@eecs.umich.edu Fault fault = NoFault; 5557303Sgblack@eecs.umich.edu 5567303Sgblack@eecs.umich.edu %(op_decl)s; 5577303Sgblack@eecs.umich.edu %(op_rd)s; 5587303Sgblack@eecs.umich.edu 5597303Sgblack@eecs.umich.edu if (%(predicate_test)s) 5607303Sgblack@eecs.umich.edu { 5617303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5627303Sgblack@eecs.umich.edu %(postacc_code)s; 5637303Sgblack@eecs.umich.edu 5647303Sgblack@eecs.umich.edu if (fault == NoFault) { 5657303Sgblack@eecs.umich.edu %(op_wb)s; 5667303Sgblack@eecs.umich.edu } 5677303Sgblack@eecs.umich.edu } 5687303Sgblack@eecs.umich.edu 5697303Sgblack@eecs.umich.edu return fault; 5707303Sgblack@eecs.umich.edu } 5717303Sgblack@eecs.umich.edu}}; 5727303Sgblack@eecs.umich.edu 5737291Sgblack@eecs.umich.edudef template RfeDeclare {{ 5747291Sgblack@eecs.umich.edu /** 5757291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5767291Sgblack@eecs.umich.edu */ 5777291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5787291Sgblack@eecs.umich.edu { 5797291Sgblack@eecs.umich.edu public: 5807291Sgblack@eecs.umich.edu 5817291Sgblack@eecs.umich.edu /// Constructor. 5827291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5837291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5847291Sgblack@eecs.umich.edu 5857291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5867291Sgblack@eecs.umich.edu 5877291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5887291Sgblack@eecs.umich.edu 5897291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5907291Sgblack@eecs.umich.edu }; 5917291Sgblack@eecs.umich.edu}}; 5927291Sgblack@eecs.umich.edu 5937312Sgblack@eecs.umich.edudef template SrsDeclare {{ 5947312Sgblack@eecs.umich.edu /** 5957312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5967312Sgblack@eecs.umich.edu */ 5977312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5987312Sgblack@eecs.umich.edu { 5997312Sgblack@eecs.umich.edu public: 6007312Sgblack@eecs.umich.edu 6017312Sgblack@eecs.umich.edu /// Constructor. 6027312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6037312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6047312Sgblack@eecs.umich.edu 6057312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6067312Sgblack@eecs.umich.edu 6077312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6087312Sgblack@eecs.umich.edu 6097312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6107312Sgblack@eecs.umich.edu }; 6117312Sgblack@eecs.umich.edu}}; 6127312Sgblack@eecs.umich.edu 6137205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6147205Sgblack@eecs.umich.edu /** 6157205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6167205Sgblack@eecs.umich.edu */ 6177205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6187205Sgblack@eecs.umich.edu { 6197205Sgblack@eecs.umich.edu public: 6207205Sgblack@eecs.umich.edu 6217205Sgblack@eecs.umich.edu /// Constructor. 6227205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6237205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6247205Sgblack@eecs.umich.edu 6257205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6267205Sgblack@eecs.umich.edu 6277205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6287205Sgblack@eecs.umich.edu 6297205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6307205Sgblack@eecs.umich.edu }; 6317205Sgblack@eecs.umich.edu}}; 6327205Sgblack@eecs.umich.edu 6337279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6347279Sgblack@eecs.umich.edu /** 6357279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6367279Sgblack@eecs.umich.edu */ 6377279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6387279Sgblack@eecs.umich.edu { 6397279Sgblack@eecs.umich.edu public: 6407279Sgblack@eecs.umich.edu 6417279Sgblack@eecs.umich.edu /// Constructor. 6427279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6437279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6447279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6457279Sgblack@eecs.umich.edu 6467279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6477279Sgblack@eecs.umich.edu 6487279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6497279Sgblack@eecs.umich.edu 6507279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6517279Sgblack@eecs.umich.edu }; 6527279Sgblack@eecs.umich.edu}}; 6537279Sgblack@eecs.umich.edu 6547303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6557303Sgblack@eecs.umich.edu /** 6567303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6577303Sgblack@eecs.umich.edu */ 6587303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6597303Sgblack@eecs.umich.edu { 6607303Sgblack@eecs.umich.edu public: 6617303Sgblack@eecs.umich.edu 6627303Sgblack@eecs.umich.edu /// Constructor. 6637303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6647303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6657303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6667303Sgblack@eecs.umich.edu 6677303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6687303Sgblack@eecs.umich.edu 6697303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6707303Sgblack@eecs.umich.edu 6717303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6727303Sgblack@eecs.umich.edu }; 6737303Sgblack@eecs.umich.edu}}; 6747303Sgblack@eecs.umich.edu 6757119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6767119Sgblack@eecs.umich.edu /** 6777119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6787119Sgblack@eecs.umich.edu */ 6797119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6807119Sgblack@eecs.umich.edu { 6817119Sgblack@eecs.umich.edu public: 6827119Sgblack@eecs.umich.edu 6837119Sgblack@eecs.umich.edu /// Constructor. 6847119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6857119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6867119Sgblack@eecs.umich.edu 6877119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6887119Sgblack@eecs.umich.edu 6897119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6907119Sgblack@eecs.umich.edu 6917119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 69210037SARM gem5 Developers 69310037SARM gem5 Developers virtual void 69410037SARM gem5 Developers annotateFault(ArmFault *fault) { 69510037SARM gem5 Developers %(fa_code)s 69610037SARM gem5 Developers } 6977119Sgblack@eecs.umich.edu }; 6987119Sgblack@eecs.umich.edu}}; 6997119Sgblack@eecs.umich.edu 7007303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7017303Sgblack@eecs.umich.edu /** 7027303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7037303Sgblack@eecs.umich.edu */ 7047303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7057303Sgblack@eecs.umich.edu { 7067303Sgblack@eecs.umich.edu public: 7077303Sgblack@eecs.umich.edu 7087303Sgblack@eecs.umich.edu /// Constructor. 7097303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7107303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7117303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7127303Sgblack@eecs.umich.edu 7137303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7147303Sgblack@eecs.umich.edu 7157303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7167303Sgblack@eecs.umich.edu 7177303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7187303Sgblack@eecs.umich.edu }; 7197303Sgblack@eecs.umich.edu}}; 7207303Sgblack@eecs.umich.edu 7217646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 7227279Sgblack@eecs.umich.edu /** 7237279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7247279Sgblack@eecs.umich.edu */ 7257279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7267279Sgblack@eecs.umich.edu { 7277279Sgblack@eecs.umich.edu public: 7287279Sgblack@eecs.umich.edu 7297279Sgblack@eecs.umich.edu /// Constructor. 7307279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7317279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7327279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7337279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7347279Sgblack@eecs.umich.edu uint32_t _index); 7357279Sgblack@eecs.umich.edu 7367279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7377279Sgblack@eecs.umich.edu 7387279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7397279Sgblack@eecs.umich.edu 7407279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7417279Sgblack@eecs.umich.edu }; 7427279Sgblack@eecs.umich.edu}}; 7437279Sgblack@eecs.umich.edu 7447646Sgene.wu@arm.comdef template StoreRegDeclare {{ 7457119Sgblack@eecs.umich.edu /** 7467119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7477119Sgblack@eecs.umich.edu */ 7487119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7497119Sgblack@eecs.umich.edu { 7507119Sgblack@eecs.umich.edu public: 7517119Sgblack@eecs.umich.edu 7527119Sgblack@eecs.umich.edu /// Constructor. 7537119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7547119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7557119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7567119Sgblack@eecs.umich.edu uint32_t _index); 7577119Sgblack@eecs.umich.edu 7587119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7597119Sgblack@eecs.umich.edu 7607119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7617119Sgblack@eecs.umich.edu 7627119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 76310037SARM gem5 Developers 76410037SARM gem5 Developers virtual void 76510037SARM gem5 Developers annotateFault(ArmFault *fault) { 76610037SARM gem5 Developers %(fa_code)s 76710037SARM gem5 Developers } 7687119Sgblack@eecs.umich.edu }; 7697119Sgblack@eecs.umich.edu}}; 7707119Sgblack@eecs.umich.edu 7717646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 7727646Sgene.wu@arm.com /** 7737646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7747646Sgene.wu@arm.com */ 7757646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7767646Sgene.wu@arm.com { 7777646Sgene.wu@arm.com public: 7787646Sgene.wu@arm.com 7797646Sgene.wu@arm.com /// Constructor. 7807646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 7817646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 7827646Sgene.wu@arm.com uint32_t _base, bool _add, 7837646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 7847646Sgene.wu@arm.com uint32_t _index); 7857646Sgene.wu@arm.com 7867646Sgene.wu@arm.com %(BasicExecDeclare)s 7877646Sgene.wu@arm.com 7887646Sgene.wu@arm.com %(InitiateAccDeclare)s 7897646Sgene.wu@arm.com 7907646Sgene.wu@arm.com %(CompleteAccDeclare)s 7917646Sgene.wu@arm.com }; 7927646Sgene.wu@arm.com}}; 7937646Sgene.wu@arm.com 7947646Sgene.wu@arm.comdef template LoadRegDeclare {{ 7957646Sgene.wu@arm.com /** 7967646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7977646Sgene.wu@arm.com */ 7987646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7997646Sgene.wu@arm.com { 8007646Sgene.wu@arm.com public: 8017646Sgene.wu@arm.com 8027646Sgene.wu@arm.com /// Constructor. 8037646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8047646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 8057646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8067646Sgene.wu@arm.com uint32_t _index); 8077646Sgene.wu@arm.com 8087646Sgene.wu@arm.com %(BasicExecDeclare)s 8097646Sgene.wu@arm.com 8107646Sgene.wu@arm.com %(InitiateAccDeclare)s 8117646Sgene.wu@arm.com 8127646Sgene.wu@arm.com %(CompleteAccDeclare)s 81310037SARM gem5 Developers 81410037SARM gem5 Developers virtual void 81510037SARM gem5 Developers annotateFault(ArmFault *fault) { 81610037SARM gem5 Developers %(fa_code)s 81710037SARM gem5 Developers } 8187646Sgene.wu@arm.com }; 8197646Sgene.wu@arm.com}}; 8207646Sgene.wu@arm.com 8217646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8227646Sgene.wu@arm.com /** 8237646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8247646Sgene.wu@arm.com */ 8257646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8267646Sgene.wu@arm.com { 8277646Sgene.wu@arm.com public: 8287646Sgene.wu@arm.com 8297646Sgene.wu@arm.com /// Constructor. 8307646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8317646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8327646Sgene.wu@arm.com 8337646Sgene.wu@arm.com %(BasicExecDeclare)s 8347646Sgene.wu@arm.com 8357646Sgene.wu@arm.com %(InitiateAccDeclare)s 8367646Sgene.wu@arm.com 8377646Sgene.wu@arm.com %(CompleteAccDeclare)s 83810037SARM gem5 Developers 83910037SARM gem5 Developers virtual void 84010037SARM gem5 Developers annotateFault(ArmFault *fault) { 84110037SARM gem5 Developers %(fa_code)s 84210037SARM gem5 Developers } 8437646Sgene.wu@arm.com }; 8447646Sgene.wu@arm.com}}; 8457646Sgene.wu@arm.com 8467119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 84712234Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 8487119Sgblack@eecs.umich.edu}}; 8497119Sgblack@eecs.umich.edu 8507119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 85112234Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 8527119Sgblack@eecs.umich.edu}}; 8537119Sgblack@eecs.umich.edu 8547291Sgblack@eecs.umich.edudef template RfeConstructor {{ 85510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8568140SMatt.Horsnell@arm.com uint32_t _base, int _mode, bool _wb) 8578140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8588140SMatt.Horsnell@arm.com (IntRegIndex)_base, (AddrMode)_mode, _wb) 8597291Sgblack@eecs.umich.edu { 8607291Sgblack@eecs.umich.edu %(constructor)s; 8617848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8627848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8637848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8647848SAli.Saidi@ARM.com } 8657848SAli.Saidi@ARM.com } 8667646Sgene.wu@arm.com#if %(use_uops)d 8678140SMatt.Horsnell@arm.com uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8688140SMatt.Horsnell@arm.com int uopIdx = 0; 8698140SMatt.Horsnell@arm.com uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8708140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8718140SMatt.Horsnell@arm.com#if %(use_wb)d 8728140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(wb_decl)s; 8738140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8748140SMatt.Horsnell@arm.com#endif 8758140SMatt.Horsnell@arm.com#if %(use_pc)d 8768140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(pc_decl)s; 8778140SMatt.Horsnell@arm.com#endif 87810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 8798140SMatt.Horsnell@arm.com uops[uopIdx]->setLastMicroop(); 8807646Sgene.wu@arm.com#endif 8817291Sgblack@eecs.umich.edu } 8827291Sgblack@eecs.umich.edu}}; 8837291Sgblack@eecs.umich.edu 8847312Sgblack@eecs.umich.edudef template SrsConstructor {{ 88510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8867312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8877312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8887312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8897312Sgblack@eecs.umich.edu { 8907312Sgblack@eecs.umich.edu %(constructor)s; 8917848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8927848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8937848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8947848SAli.Saidi@ARM.com } 8957848SAli.Saidi@ARM.com } 8967646Sgene.wu@arm.com#if %(use_uops)d 8977646Sgene.wu@arm.com assert(numMicroops >= 2); 8987646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 8997646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9007724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 90110666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9027646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9037646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9047646Sgene.wu@arm.com#endif 9057312Sgblack@eecs.umich.edu } 9067312Sgblack@eecs.umich.edu}}; 9077312Sgblack@eecs.umich.edu 9087205Sgblack@eecs.umich.edudef template SwapConstructor {{ 90910184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9107205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9117205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9127205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9137205Sgblack@eecs.umich.edu { 9147205Sgblack@eecs.umich.edu %(constructor)s; 9157848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9167848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9177848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9187848SAli.Saidi@ARM.com } 9197848SAli.Saidi@ARM.com } 9207205Sgblack@eecs.umich.edu } 9217205Sgblack@eecs.umich.edu}}; 9227205Sgblack@eecs.umich.edu 9237279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 92410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9257279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9267279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9277279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9287279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9297279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9307279Sgblack@eecs.umich.edu { 9317279Sgblack@eecs.umich.edu %(constructor)s; 9327848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9337848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9347848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9357848SAli.Saidi@ARM.com } 9367848SAli.Saidi@ARM.com } 9377646Sgene.wu@arm.com#if %(use_uops)d 9387646Sgene.wu@arm.com assert(numMicroops >= 2); 9397646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9407646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 94110666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9427724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9437646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9447646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9457646Sgene.wu@arm.com#endif 9467279Sgblack@eecs.umich.edu } 9477279Sgblack@eecs.umich.edu}}; 9487279Sgblack@eecs.umich.edu 9497303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 95010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9517303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9527303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9537303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9547303Sgblack@eecs.umich.edu (IntRegIndex)_result, 9557303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9567303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9577303Sgblack@eecs.umich.edu { 9587303Sgblack@eecs.umich.edu %(constructor)s; 9597848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9607848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9617848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9627848SAli.Saidi@ARM.com } 9637848SAli.Saidi@ARM.com } 9647646Sgene.wu@arm.com#if %(use_uops)d 9657646Sgene.wu@arm.com assert(numMicroops >= 2); 9667646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9677646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9687646Sgene.wu@arm.com _base, _add, _imm); 9697724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 97010666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9717646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9727646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9737646Sgene.wu@arm.com#endif 9747303Sgblack@eecs.umich.edu } 9757303Sgblack@eecs.umich.edu}}; 9767303Sgblack@eecs.umich.edu 9777119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 97810184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9797119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9807119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9817119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9827119Sgblack@eecs.umich.edu { 9837119Sgblack@eecs.umich.edu %(constructor)s; 9847848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9857848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9867848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9877848SAli.Saidi@ARM.com } 9887848SAli.Saidi@ARM.com } 9897646Sgene.wu@arm.com#if %(use_uops)d 9907646Sgene.wu@arm.com assert(numMicroops >= 2); 9917646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9927646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9937724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 99410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9957646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9967646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9977646Sgene.wu@arm.com#endif 9987119Sgblack@eecs.umich.edu } 9997119Sgblack@eecs.umich.edu}}; 10007119Sgblack@eecs.umich.edu 10017303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 100210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10037303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10047303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10057303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10067303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10077303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10087303Sgblack@eecs.umich.edu { 10097303Sgblack@eecs.umich.edu %(constructor)s; 10107848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10117848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10127848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10137848SAli.Saidi@ARM.com } 10147848SAli.Saidi@ARM.com } 10157646Sgene.wu@arm.com#if %(use_uops)d 10167646Sgene.wu@arm.com assert(numMicroops >= 2); 10177646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10187646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10197646Sgene.wu@arm.com _base, _add, _imm); 10207724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 102110666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10227646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10237646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10247646Sgene.wu@arm.com#endif 10257303Sgblack@eecs.umich.edu } 10267303Sgblack@eecs.umich.edu}}; 10277303Sgblack@eecs.umich.edu 10287646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 102910184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10307279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10317279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10327279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10337279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10347279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10357279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10367279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10377279Sgblack@eecs.umich.edu { 10387279Sgblack@eecs.umich.edu %(constructor)s; 10397848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10407848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10417848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10427848SAli.Saidi@ARM.com } 10437848SAli.Saidi@ARM.com } 10447646Sgene.wu@arm.com#if %(use_uops)d 10457646Sgene.wu@arm.com assert(numMicroops >= 2); 10467646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10477646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10487646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10497724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 105010666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10517646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10527646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10537646Sgene.wu@arm.com#endif 10547279Sgblack@eecs.umich.edu } 10557279Sgblack@eecs.umich.edu}}; 10567279Sgblack@eecs.umich.edu 10577646Sgene.wu@arm.comdef template StoreRegConstructor {{ 105810184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10597119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10607119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10617119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10627119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10637119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10647119Sgblack@eecs.umich.edu (IntRegIndex)_index) 10657119Sgblack@eecs.umich.edu { 10667119Sgblack@eecs.umich.edu %(constructor)s; 10677848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10687848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10697848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10707848SAli.Saidi@ARM.com } 10717848SAli.Saidi@ARM.com } 10727646Sgene.wu@arm.com#if %(use_uops)d 10737646Sgene.wu@arm.com assert(numMicroops >= 2); 10747646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10757646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10767646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10777724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 107810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10797646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10807646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10817646Sgene.wu@arm.com#endif 10827119Sgblack@eecs.umich.edu } 10837119Sgblack@eecs.umich.edu}}; 10847646Sgene.wu@arm.com 10857646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 108610184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10877646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10887646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10897646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10907646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 10917646Sgene.wu@arm.com (IntRegIndex)_base, _add, 10927646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 10937646Sgene.wu@arm.com (IntRegIndex)_index) 10947646Sgene.wu@arm.com { 10957646Sgene.wu@arm.com %(constructor)s; 10967848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10977848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10987848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10997848SAli.Saidi@ARM.com } 11007848SAli.Saidi@ARM.com } 11017646Sgene.wu@arm.com#if %(use_uops)d 11027646Sgene.wu@arm.com assert(numMicroops >= 2); 11037646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11047646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 11057646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11067646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11077724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 110810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11097646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11107646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11117724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11127646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11137646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11147646Sgene.wu@arm.com } else { 11157646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11167646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11177646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11187724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 111910666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11207646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11217646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11227646Sgene.wu@arm.com } 11237646Sgene.wu@arm.com#endif 11247646Sgene.wu@arm.com } 11257646Sgene.wu@arm.com}}; 11267646Sgene.wu@arm.com 11277646Sgene.wu@arm.comdef template LoadRegConstructor {{ 112810184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 11297646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11307646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11317646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11327646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11337646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11347646Sgene.wu@arm.com (IntRegIndex)_index) 11357646Sgene.wu@arm.com { 11367646Sgene.wu@arm.com %(constructor)s; 11378607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11387848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11398203SAli.Saidi@ARM.com conditional = true; 11407848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11417848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11427848SAli.Saidi@ARM.com } 11437848SAli.Saidi@ARM.com } 11447646Sgene.wu@arm.com#if %(use_uops)d 11457646Sgene.wu@arm.com assert(numMicroops >= 2); 11467646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 114712110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11487646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11497646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11507646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11517724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 115210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11537646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11547724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11557646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11568203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 11578203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11588203SAli.Saidi@ARM.com if (conditional) 11598203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 11608203SAli.Saidi@ARM.com else 11618203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 11627646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11637646Sgene.wu@arm.com } else if(_dest == _index) { 11647646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11657646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11667724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 116710666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11687646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11697646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11707724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11717646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11727646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11737646Sgene.wu@arm.com } else { 11747646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11757646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11767646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11777724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 117810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11797646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11807646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11817646Sgene.wu@arm.com 11827646Sgene.wu@arm.com } 11839250SAli.Saidi@ARM.com#else 118412110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11859250SAli.Saidi@ARM.com flags[IsControl] = true; 11869250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 11879250SAli.Saidi@ARM.com if (conditional) 11889250SAli.Saidi@ARM.com flags[IsCondControl] = true; 11899250SAli.Saidi@ARM.com else 11909250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 11919250SAli.Saidi@ARM.com } 11927646Sgene.wu@arm.com#endif 11937646Sgene.wu@arm.com } 11947646Sgene.wu@arm.com}}; 11957646Sgene.wu@arm.com 11967646Sgene.wu@arm.comdef template LoadImmConstructor {{ 119710184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 11987646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 11997646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 12007646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 12017646Sgene.wu@arm.com { 12027646Sgene.wu@arm.com %(constructor)s; 12038607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 12047848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 12058203SAli.Saidi@ARM.com conditional = true; 12067848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 12077848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12087848SAli.Saidi@ARM.com } 12097848SAli.Saidi@ARM.com } 12107646Sgene.wu@arm.com#if %(use_uops)d 12117646Sgene.wu@arm.com assert(numMicroops >= 2); 12127646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 121312110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 12147646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 12157646Sgene.wu@arm.com _imm); 12167724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 121710666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12187646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12197724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12207646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12218203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 12228203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 122310199SAndrew.Bardsley@arm.com /* Also set flags on the macroop so that pre-microop decomposition 122410199SAndrew.Bardsley@arm.com branch prediction can work */ 122510199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsControl); 122610199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsIndirectControl); 122710199SAndrew.Bardsley@arm.com if (conditional) { 12288203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 122910199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsCondControl); 123010199SAndrew.Bardsley@arm.com } else { 12318203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 123210199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsUncondControl); 123310199SAndrew.Bardsley@arm.com } 123410199SAndrew.Bardsley@arm.com if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) { 12358203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsReturn); 123610199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsReturn); 123710199SAndrew.Bardsley@arm.com } 12387646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12397646Sgene.wu@arm.com } else { 12407646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12417724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 124210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12437646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12447646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12457646Sgene.wu@arm.com } 12469250SAli.Saidi@ARM.com#else 124712110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 12489250SAli.Saidi@ARM.com flags[IsControl] = true; 12499250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 12509250SAli.Saidi@ARM.com if (conditional) 12519250SAli.Saidi@ARM.com flags[IsCondControl] = true; 12529250SAli.Saidi@ARM.com else 12539250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 12549250SAli.Saidi@ARM.com } 12557646Sgene.wu@arm.com#endif 12567646Sgene.wu@arm.com } 12577646Sgene.wu@arm.com}}; 12587646Sgene.wu@arm.com 1259