mem.isa revision 12110
17322Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27322Sgblack@eecs.umich.edu 37322Sgblack@eecs.umich.edu// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited 47322Sgblack@eecs.umich.edu// All rights reserved 57322Sgblack@eecs.umich.edu// 67322Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77322Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87322Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97322Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107322Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117322Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127322Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137322Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147322Sgblack@eecs.umich.edu// 157322Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167322Sgblack@eecs.umich.edu// All rights reserved. 177322Sgblack@eecs.umich.edu// 187322Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197322Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207322Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227322Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237322Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247322Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257322Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267322Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277322Sgblack@eecs.umich.edu// this software without specific prior written permission. 287322Sgblack@eecs.umich.edu// 297322Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307322Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317322Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327322Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337322Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347322Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357322Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367322Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377322Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387322Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397322Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407376Sgblack@eecs.umich.edu// 417376Sgblack@eecs.umich.edu// Authors: Stephen Hines 427376Sgblack@eecs.umich.edu 437376Sgblack@eecs.umich.edu 447376Sgblack@eecs.umich.edudef template PanicExecute {{ 457376Sgblack@eecs.umich.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 467376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 477376Sgblack@eecs.umich.edu { 487376Sgblack@eecs.umich.edu panic("Execute function executed when it shouldn't be!\n"); 497376Sgblack@eecs.umich.edu return NoFault; 507376Sgblack@eecs.umich.edu } 517376Sgblack@eecs.umich.edu}}; 527376Sgblack@eecs.umich.edu 537376Sgblack@eecs.umich.edudef template PanicInitiateAcc {{ 547376Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 557376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 567376Sgblack@eecs.umich.edu { 577376Sgblack@eecs.umich.edu panic("InitiateAcc function executed when it shouldn't be!\n"); 587376Sgblack@eecs.umich.edu return NoFault; 597376Sgblack@eecs.umich.edu } 607376Sgblack@eecs.umich.edu}}; 617376Sgblack@eecs.umich.edu 627376Sgblack@eecs.umich.edudef template PanicCompleteAcc {{ 637376Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 647376Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, 657376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 667376Sgblack@eecs.umich.edu { 677376Sgblack@eecs.umich.edu panic("CompleteAcc function executed when it shouldn't be!\n"); 687376Sgblack@eecs.umich.edu return NoFault; 697376Sgblack@eecs.umich.edu } 707376Sgblack@eecs.umich.edu}}; 717376Sgblack@eecs.umich.edu 727376Sgblack@eecs.umich.edu 737376Sgblack@eecs.umich.edudef template SwapExecute {{ 747376Sgblack@eecs.umich.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 757376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767376Sgblack@eecs.umich.edu { 777376Sgblack@eecs.umich.edu Addr EA; 787376Sgblack@eecs.umich.edu Fault fault = NoFault; 797376Sgblack@eecs.umich.edu 807376Sgblack@eecs.umich.edu %(op_decl)s; 817376Sgblack@eecs.umich.edu uint64_t memData = 0; 827376Sgblack@eecs.umich.edu %(op_rd)s; 837376Sgblack@eecs.umich.edu %(ea_code)s; 847376Sgblack@eecs.umich.edu 857376Sgblack@eecs.umich.edu if (%(predicate_test)s) 867376Sgblack@eecs.umich.edu { 877376Sgblack@eecs.umich.edu %(preacc_code)s; 887376Sgblack@eecs.umich.edu 897376Sgblack@eecs.umich.edu if (fault == NoFault) { 907376Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 917376Sgblack@eecs.umich.edu &memData); 927376Sgblack@eecs.umich.edu } 937376Sgblack@eecs.umich.edu 947376Sgblack@eecs.umich.edu if (fault == NoFault) { 957376Sgblack@eecs.umich.edu %(postacc_code)s; 967376Sgblack@eecs.umich.edu } 977376Sgblack@eecs.umich.edu 987376Sgblack@eecs.umich.edu if (fault == NoFault) { 997376Sgblack@eecs.umich.edu %(op_wb)s; 1007376Sgblack@eecs.umich.edu } 1017376Sgblack@eecs.umich.edu } else { 1027376Sgblack@eecs.umich.edu xc->setPredicate(false); 1037376Sgblack@eecs.umich.edu } 1047376Sgblack@eecs.umich.edu 1057376Sgblack@eecs.umich.edu return fault; 1067376Sgblack@eecs.umich.edu } 1077376Sgblack@eecs.umich.edu}}; 1087376Sgblack@eecs.umich.edu 1097376Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 1107376Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 1117376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1127376Sgblack@eecs.umich.edu { 1137376Sgblack@eecs.umich.edu Addr EA; 1147376Sgblack@eecs.umich.edu Fault fault = NoFault; 1157376Sgblack@eecs.umich.edu 1167376Sgblack@eecs.umich.edu %(op_decl)s; 1177376Sgblack@eecs.umich.edu uint64_t memData = 0; 1187376Sgblack@eecs.umich.edu %(op_rd)s; 1197376Sgblack@eecs.umich.edu %(ea_code)s; 1207376Sgblack@eecs.umich.edu 1217376Sgblack@eecs.umich.edu if (%(predicate_test)s) 1227376Sgblack@eecs.umich.edu { 1237376Sgblack@eecs.umich.edu %(preacc_code)s; 1247376Sgblack@eecs.umich.edu 1257376Sgblack@eecs.umich.edu if (fault == NoFault) { 1267376Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1277376Sgblack@eecs.umich.edu &memData); 1287376Sgblack@eecs.umich.edu } 1297376Sgblack@eecs.umich.edu } else { 1307376Sgblack@eecs.umich.edu xc->setPredicate(false); 1317376Sgblack@eecs.umich.edu } 1327376Sgblack@eecs.umich.edu 1337376Sgblack@eecs.umich.edu return fault; 1347376Sgblack@eecs.umich.edu } 1357376Sgblack@eecs.umich.edu}}; 1367376Sgblack@eecs.umich.edu 1377376Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1387376Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1397376Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, 1407376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1417376Sgblack@eecs.umich.edu { 1427376Sgblack@eecs.umich.edu Fault fault = NoFault; 1437376Sgblack@eecs.umich.edu 1447376Sgblack@eecs.umich.edu %(op_decl)s; 1457376Sgblack@eecs.umich.edu %(op_rd)s; 1467376Sgblack@eecs.umich.edu 1477376Sgblack@eecs.umich.edu if (%(predicate_test)s) 1487376Sgblack@eecs.umich.edu { 1497376Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1507376Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1517376Sgblack@eecs.umich.edu uint64_t memData = Mem; 1527376Sgblack@eecs.umich.edu 1537376Sgblack@eecs.umich.edu %(postacc_code)s; 1547376Sgblack@eecs.umich.edu 1557376Sgblack@eecs.umich.edu if (fault == NoFault) { 1567376Sgblack@eecs.umich.edu %(op_wb)s; 1577376Sgblack@eecs.umich.edu } 1587376Sgblack@eecs.umich.edu } 1597376Sgblack@eecs.umich.edu 1607376Sgblack@eecs.umich.edu return fault; 1617376Sgblack@eecs.umich.edu } 1627376Sgblack@eecs.umich.edu}}; 1637376Sgblack@eecs.umich.edu 1647376Sgblack@eecs.umich.edudef template LoadExecute {{ 1657376Sgblack@eecs.umich.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 1667376Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1677376Sgblack@eecs.umich.edu { 1687376Sgblack@eecs.umich.edu Addr EA; 1697376Sgblack@eecs.umich.edu Fault fault = NoFault; 1707376Sgblack@eecs.umich.edu 1717376Sgblack@eecs.umich.edu %(op_decl)s; 1727376Sgblack@eecs.umich.edu %(op_rd)s; 1737376Sgblack@eecs.umich.edu %(ea_code)s; 1747376Sgblack@eecs.umich.edu 1757376Sgblack@eecs.umich.edu if (%(predicate_test)s) 1767376Sgblack@eecs.umich.edu { 1777376Sgblack@eecs.umich.edu if (fault == NoFault) { 1787376Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1797376Sgblack@eecs.umich.edu %(memacc_code)s; 1807376Sgblack@eecs.umich.edu } 1817376Sgblack@eecs.umich.edu 1827376Sgblack@eecs.umich.edu if (fault == NoFault) { 1837376Sgblack@eecs.umich.edu %(op_wb)s; 1847376Sgblack@eecs.umich.edu } 1857376Sgblack@eecs.umich.edu } else { 1867376Sgblack@eecs.umich.edu xc->setPredicate(false); 1877376Sgblack@eecs.umich.edu } 1887322Sgblack@eecs.umich.edu 1897322Sgblack@eecs.umich.edu return fault; 1907322Sgblack@eecs.umich.edu } 1917322Sgblack@eecs.umich.edu}}; 1927322Sgblack@eecs.umich.edu 1937322Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1947396Sgblack@eecs.umich.edu template <class Element> 1957322Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 1967322Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1977396Sgblack@eecs.umich.edu { 1987396Sgblack@eecs.umich.edu Addr EA; 1997322Sgblack@eecs.umich.edu Fault fault = NoFault; 2007324Sgblack@eecs.umich.edu 2017396Sgblack@eecs.umich.edu %(op_decl)s; 2027324Sgblack@eecs.umich.edu %(mem_decl)s; 2037324Sgblack@eecs.umich.edu %(op_rd)s; 2047396Sgblack@eecs.umich.edu %(ea_code)s; 2057396Sgblack@eecs.umich.edu 2067324Sgblack@eecs.umich.edu MemUnion memUnion; 2077333Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2087392Sgblack@eecs.umich.edu 2097396Sgblack@eecs.umich.edu if (%(predicate_test)s) 2107392Sgblack@eecs.umich.edu { 2117392Sgblack@eecs.umich.edu if (fault == NoFault) { 2127396Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 2137396Sgblack@eecs.umich.edu %(memacc_code)s; 2147392Sgblack@eecs.umich.edu } 2157392Sgblack@eecs.umich.edu 2167333Sgblack@eecs.umich.edu if (fault == NoFault) { 2177333Sgblack@eecs.umich.edu %(op_wb)s; 2187333Sgblack@eecs.umich.edu } 2197396Sgblack@eecs.umich.edu } else { 2207333Sgblack@eecs.umich.edu xc->setPredicate(false); 2217333Sgblack@eecs.umich.edu } 2227396Sgblack@eecs.umich.edu 2237396Sgblack@eecs.umich.edu return fault; 2247333Sgblack@eecs.umich.edu } 2257333Sgblack@eecs.umich.edu}}; 2267333Sgblack@eecs.umich.edu 2277333Sgblack@eecs.umich.edudef template StoreExecute {{ 2287333Sgblack@eecs.umich.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 2297333Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2307396Sgblack@eecs.umich.edu { 2317333Sgblack@eecs.umich.edu Addr EA; 2327333Sgblack@eecs.umich.edu Fault fault = NoFault; 2337396Sgblack@eecs.umich.edu 2347396Sgblack@eecs.umich.edu %(op_decl)s; 2357333Sgblack@eecs.umich.edu %(op_rd)s; 2367333Sgblack@eecs.umich.edu %(ea_code)s; 2377333Sgblack@eecs.umich.edu 2387333Sgblack@eecs.umich.edu if (%(predicate_test)s) 2397333Sgblack@eecs.umich.edu { 2407333Sgblack@eecs.umich.edu if (fault == NoFault) { 2417333Sgblack@eecs.umich.edu %(memacc_code)s; 2427333Sgblack@eecs.umich.edu } 2437396Sgblack@eecs.umich.edu 2447333Sgblack@eecs.umich.edu if (fault == NoFault) { 2457333Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2467396Sgblack@eecs.umich.edu memAccessFlags, NULL); 2477396Sgblack@eecs.umich.edu } 2487333Sgblack@eecs.umich.edu 2497333Sgblack@eecs.umich.edu if (fault == NoFault) { 2507333Sgblack@eecs.umich.edu %(op_wb)s; 2517333Sgblack@eecs.umich.edu } 2527333Sgblack@eecs.umich.edu } else { 2537396Sgblack@eecs.umich.edu xc->setPredicate(false); 2547333Sgblack@eecs.umich.edu } 2557333Sgblack@eecs.umich.edu 2567396Sgblack@eecs.umich.edu return fault; 2577396Sgblack@eecs.umich.edu } 2587333Sgblack@eecs.umich.edu}}; 2597333Sgblack@eecs.umich.edu 2607333Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2617333Sgblack@eecs.umich.edu template <class Element> 2627333Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 2637333Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 2647396Sgblack@eecs.umich.edu { 2657333Sgblack@eecs.umich.edu Addr EA; 2667333Sgblack@eecs.umich.edu Fault fault = NoFault; 2677396Sgblack@eecs.umich.edu 2687396Sgblack@eecs.umich.edu %(op_decl)s; 2697333Sgblack@eecs.umich.edu %(mem_decl)s; 2707333Sgblack@eecs.umich.edu %(op_rd)s; 2717333Sgblack@eecs.umich.edu %(ea_code)s; 2727333Sgblack@eecs.umich.edu 2737333Sgblack@eecs.umich.edu MemUnion memUnion; 2747333Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2757333Sgblack@eecs.umich.edu 2767333Sgblack@eecs.umich.edu if (%(predicate_test)s) 2777396Sgblack@eecs.umich.edu { 2787333Sgblack@eecs.umich.edu if (fault == NoFault) { 2797333Sgblack@eecs.umich.edu %(memacc_code)s; 2807396Sgblack@eecs.umich.edu } 2817396Sgblack@eecs.umich.edu 2827333Sgblack@eecs.umich.edu if (fault == NoFault) { 2837333Sgblack@eecs.umich.edu fault = xc->writeMem(dataPtr, %(size)d, EA, 2847333Sgblack@eecs.umich.edu memAccessFlags, NULL); 2857639Sgblack@eecs.umich.edu } 2867333Sgblack@eecs.umich.edu 2877396Sgblack@eecs.umich.edu if (fault == NoFault) { 2887333Sgblack@eecs.umich.edu %(op_wb)s; 2897333Sgblack@eecs.umich.edu } 2907396Sgblack@eecs.umich.edu } else { 2917396Sgblack@eecs.umich.edu xc->setPredicate(false); 2927333Sgblack@eecs.umich.edu } 2937333Sgblack@eecs.umich.edu 2947333Sgblack@eecs.umich.edu return fault; 2957639Sgblack@eecs.umich.edu } 2967333Sgblack@eecs.umich.edu}}; 2977396Sgblack@eecs.umich.edu 2987333Sgblack@eecs.umich.edudef template StoreExExecute {{ 2997333Sgblack@eecs.umich.edu Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 3007396Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3017396Sgblack@eecs.umich.edu { 3027333Sgblack@eecs.umich.edu Addr EA; 3037333Sgblack@eecs.umich.edu Fault fault = NoFault; 3047333Sgblack@eecs.umich.edu 3057333Sgblack@eecs.umich.edu %(op_decl)s; 3067333Sgblack@eecs.umich.edu %(op_rd)s; 3077396Sgblack@eecs.umich.edu %(ea_code)s; 3087333Sgblack@eecs.umich.edu 3097333Sgblack@eecs.umich.edu if (%(predicate_test)s) 3107396Sgblack@eecs.umich.edu { 3117396Sgblack@eecs.umich.edu if (fault == NoFault) { 3127333Sgblack@eecs.umich.edu %(memacc_code)s; 3137333Sgblack@eecs.umich.edu } 3147333Sgblack@eecs.umich.edu 3157639Sgblack@eecs.umich.edu uint64_t writeResult; 3167639Sgblack@eecs.umich.edu 3177333Sgblack@eecs.umich.edu if (fault == NoFault) { 3187396Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3197333Sgblack@eecs.umich.edu &writeResult); 3207333Sgblack@eecs.umich.edu } 3217396Sgblack@eecs.umich.edu 3227396Sgblack@eecs.umich.edu if (fault == NoFault) { 3237333Sgblack@eecs.umich.edu %(postacc_code)s; 3247333Sgblack@eecs.umich.edu } 3257333Sgblack@eecs.umich.edu 3267639Sgblack@eecs.umich.edu if (fault == NoFault) { 3277639Sgblack@eecs.umich.edu %(op_wb)s; 3287333Sgblack@eecs.umich.edu } 3297396Sgblack@eecs.umich.edu } else { 3307333Sgblack@eecs.umich.edu xc->setPredicate(false); 3317333Sgblack@eecs.umich.edu } 3327396Sgblack@eecs.umich.edu 3337396Sgblack@eecs.umich.edu return fault; 3347333Sgblack@eecs.umich.edu } 3357333Sgblack@eecs.umich.edu}}; 3367333Sgblack@eecs.umich.edu 3377639Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 3387639Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 3397333Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3407396Sgblack@eecs.umich.edu { 3417333Sgblack@eecs.umich.edu Addr EA; 3427333Sgblack@eecs.umich.edu Fault fault = NoFault; 3437396Sgblack@eecs.umich.edu 3447396Sgblack@eecs.umich.edu %(op_decl)s; 3457333Sgblack@eecs.umich.edu %(op_rd)s; 3467333Sgblack@eecs.umich.edu %(ea_code)s; 3477333Sgblack@eecs.umich.edu 3487639Sgblack@eecs.umich.edu if (%(predicate_test)s) 3497639Sgblack@eecs.umich.edu { 3507333Sgblack@eecs.umich.edu if (fault == NoFault) { 3517396Sgblack@eecs.umich.edu %(memacc_code)s; 3527333Sgblack@eecs.umich.edu } 3537333Sgblack@eecs.umich.edu 3547396Sgblack@eecs.umich.edu if (fault == NoFault) { 3557396Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3567333Sgblack@eecs.umich.edu NULL); 3577333Sgblack@eecs.umich.edu } 3587333Sgblack@eecs.umich.edu } else { 3597333Sgblack@eecs.umich.edu xc->setPredicate(false); 3607333Sgblack@eecs.umich.edu } 3617396Sgblack@eecs.umich.edu 3627333Sgblack@eecs.umich.edu return fault; 3637333Sgblack@eecs.umich.edu } 3647396Sgblack@eecs.umich.edu}}; 3657396Sgblack@eecs.umich.edu 3667333Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3677333Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 3687333Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3697333Sgblack@eecs.umich.edu { 3707333Sgblack@eecs.umich.edu Addr EA; 3717333Sgblack@eecs.umich.edu Fault fault = NoFault; 3727396Sgblack@eecs.umich.edu 3737333Sgblack@eecs.umich.edu %(op_decl)s; 3747333Sgblack@eecs.umich.edu %(op_rd)s; 3757396Sgblack@eecs.umich.edu %(ea_code)s; 3767396Sgblack@eecs.umich.edu 3777333Sgblack@eecs.umich.edu if (%(predicate_test)s) 3787333Sgblack@eecs.umich.edu { 3797333Sgblack@eecs.umich.edu if (fault == NoFault) { 3807333Sgblack@eecs.umich.edu %(memacc_code)s; 3817333Sgblack@eecs.umich.edu } 3827333Sgblack@eecs.umich.edu 3837396Sgblack@eecs.umich.edu if (fault == NoFault) { 3847333Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3857333Sgblack@eecs.umich.edu NULL); 3867396Sgblack@eecs.umich.edu } 3877396Sgblack@eecs.umich.edu } else { 3887333Sgblack@eecs.umich.edu xc->setPredicate(false); 3897381Sgblack@eecs.umich.edu } 3907381Sgblack@eecs.umich.edu 3917381Sgblack@eecs.umich.edu return fault; 3927381Sgblack@eecs.umich.edu } 3937381Sgblack@eecs.umich.edu}}; 3947381Sgblack@eecs.umich.edu 3957381Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3967364Sgblack@eecs.umich.edu template <class Element> 3977396Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 3987396Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 3997396Sgblack@eecs.umich.edu { 4007396Sgblack@eecs.umich.edu Addr EA; 4017364Sgblack@eecs.umich.edu Fault fault = NoFault; 4027396Sgblack@eecs.umich.edu 4037639Sgblack@eecs.umich.edu %(op_decl)s; 4047396Sgblack@eecs.umich.edu %(mem_decl)s; 4057396Sgblack@eecs.umich.edu %(op_rd)s; 4067396Sgblack@eecs.umich.edu %(ea_code)s; 4077396Sgblack@eecs.umich.edu 4087396Sgblack@eecs.umich.edu if (%(predicate_test)s) 4097396Sgblack@eecs.umich.edu { 4107396Sgblack@eecs.umich.edu MemUnion memUnion; 4117396Sgblack@eecs.umich.edu if (fault == NoFault) { 4127396Sgblack@eecs.umich.edu %(memacc_code)s; 4137396Sgblack@eecs.umich.edu } 4147396Sgblack@eecs.umich.edu 4157639Sgblack@eecs.umich.edu if (fault == NoFault) { 4167396Sgblack@eecs.umich.edu fault = xc->writeMem(memUnion.bytes, %(size)d, EA, 4177396Sgblack@eecs.umich.edu memAccessFlags, NULL); 4187396Sgblack@eecs.umich.edu } 4197396Sgblack@eecs.umich.edu } else { 4207396Sgblack@eecs.umich.edu xc->setPredicate(false); 4217364Sgblack@eecs.umich.edu } 4227396Sgblack@eecs.umich.edu 4237396Sgblack@eecs.umich.edu return fault; 4247365Sgblack@eecs.umich.edu } 4257396Sgblack@eecs.umich.edu}}; 4267396Sgblack@eecs.umich.edu 4277396Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 4287396Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 4297396Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4307396Sgblack@eecs.umich.edu { 4317396Sgblack@eecs.umich.edu Addr EA; 4327396Sgblack@eecs.umich.edu Fault fault = NoFault; 4337365Sgblack@eecs.umich.edu 4347396Sgblack@eecs.umich.edu %(op_src_decl)s; 4357396Sgblack@eecs.umich.edu %(op_rd)s; 4367366Sgblack@eecs.umich.edu %(ea_code)s; 4377396Sgblack@eecs.umich.edu 4387396Sgblack@eecs.umich.edu if (%(predicate_test)s) 4397396Sgblack@eecs.umich.edu { 4407396Sgblack@eecs.umich.edu if (fault == NoFault) { 4417366Sgblack@eecs.umich.edu fault = initiateMemRead(xc, traceData, EA, Mem, 4427396Sgblack@eecs.umich.edu memAccessFlags); 4437396Sgblack@eecs.umich.edu } 4447396Sgblack@eecs.umich.edu } else { 4457396Sgblack@eecs.umich.edu xc->setPredicate(false); 4467367Sgblack@eecs.umich.edu } 4477396Sgblack@eecs.umich.edu 4487396Sgblack@eecs.umich.edu return fault; 4497396Sgblack@eecs.umich.edu } 4507396Sgblack@eecs.umich.edu}}; 4517367Sgblack@eecs.umich.edu 4527396Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4537396Sgblack@eecs.umich.edu template <class Element> 4547396Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 4557396Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 4567396Sgblack@eecs.umich.edu { 4577396Sgblack@eecs.umich.edu Addr EA; 4587396Sgblack@eecs.umich.edu Fault fault = NoFault; 4597396Sgblack@eecs.umich.edu 4607368Sgblack@eecs.umich.edu %(op_decl)s; 4617396Sgblack@eecs.umich.edu %(mem_decl)s; 4627396Sgblack@eecs.umich.edu %(op_rd)s; 4637368Sgblack@eecs.umich.edu %(ea_code)s; 4647396Sgblack@eecs.umich.edu 4657396Sgblack@eecs.umich.edu if (%(predicate_test)s) 4667396Sgblack@eecs.umich.edu { 4677396Sgblack@eecs.umich.edu if (fault == NoFault) { 4687369Sgblack@eecs.umich.edu fault = xc->initiateMemRead(EA, %(size)d, memAccessFlags); 4697396Sgblack@eecs.umich.edu } 4707369Sgblack@eecs.umich.edu } else { 4717396Sgblack@eecs.umich.edu xc->setPredicate(false); 4727396Sgblack@eecs.umich.edu } 4737396Sgblack@eecs.umich.edu 4747396Sgblack@eecs.umich.edu return fault; 4757369Sgblack@eecs.umich.edu } 4767396Sgblack@eecs.umich.edu}}; 4777396Sgblack@eecs.umich.edu 4787396Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 4797396Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4807396Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, 4817396Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4827369Sgblack@eecs.umich.edu { 4837396Sgblack@eecs.umich.edu Fault fault = NoFault; 4847396Sgblack@eecs.umich.edu 4857396Sgblack@eecs.umich.edu %(op_decl)s; 4867396Sgblack@eecs.umich.edu %(op_rd)s; 4877396Sgblack@eecs.umich.edu 4887396Sgblack@eecs.umich.edu if (%(predicate_test)s) 4897396Sgblack@eecs.umich.edu { 4907396Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4917396Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 4927396Sgblack@eecs.umich.edu 4937396Sgblack@eecs.umich.edu if (fault == NoFault) { 4947396Sgblack@eecs.umich.edu %(memacc_code)s; 4957381Sgblack@eecs.umich.edu } 4967381Sgblack@eecs.umich.edu 4977381Sgblack@eecs.umich.edu if (fault == NoFault) { 4987381Sgblack@eecs.umich.edu %(op_wb)s; 4997381Sgblack@eecs.umich.edu } 5007381Sgblack@eecs.umich.edu } 5017381Sgblack@eecs.umich.edu 5027370Sgblack@eecs.umich.edu return fault; 5037370Sgblack@eecs.umich.edu } 5047396Sgblack@eecs.umich.edu}}; 5057396Sgblack@eecs.umich.edu 5067639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5077639Sgblack@eecs.umich.edu template <class Element> 5087639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5097396Sgblack@eecs.umich.edu PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 5107370Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5117396Sgblack@eecs.umich.edu { 5127370Sgblack@eecs.umich.edu Fault fault = NoFault; 5137370Sgblack@eecs.umich.edu 5147396Sgblack@eecs.umich.edu %(mem_decl)s; 5157396Sgblack@eecs.umich.edu %(op_decl)s; 5167370Sgblack@eecs.umich.edu %(op_rd)s; 5177370Sgblack@eecs.umich.edu 5187370Sgblack@eecs.umich.edu if (%(predicate_test)s) 5197396Sgblack@eecs.umich.edu { 5207396Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5217396Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5227639Sgblack@eecs.umich.edu 5237396Sgblack@eecs.umich.edu if (fault == NoFault) { 5247639Sgblack@eecs.umich.edu %(memacc_code)s; 5257639Sgblack@eecs.umich.edu } 5267396Sgblack@eecs.umich.edu 5277396Sgblack@eecs.umich.edu if (fault == NoFault) { 5287396Sgblack@eecs.umich.edu %(op_wb)s; 5297370Sgblack@eecs.umich.edu } 5307396Sgblack@eecs.umich.edu } 5317370Sgblack@eecs.umich.edu 5327370Sgblack@eecs.umich.edu return fault; 5337396Sgblack@eecs.umich.edu } 5347396Sgblack@eecs.umich.edu}}; 5357370Sgblack@eecs.umich.edu 5367370Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5377370Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5387396Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, 5397396Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5407639Sgblack@eecs.umich.edu { 5417639Sgblack@eecs.umich.edu return NoFault; 5427639Sgblack@eecs.umich.edu } 5437396Sgblack@eecs.umich.edu}}; 5447370Sgblack@eecs.umich.edu 5457396Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5467370Sgblack@eecs.umich.edu template <class Element> 5477370Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 5487396Sgblack@eecs.umich.edu PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 5497396Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5507370Sgblack@eecs.umich.edu { 5517370Sgblack@eecs.umich.edu return NoFault; 5527370Sgblack@eecs.umich.edu } 5537396Sgblack@eecs.umich.edu}}; 5547396Sgblack@eecs.umich.edu 5557396Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 5567639Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 5577396Sgblack@eecs.umich.edu CPU_EXEC_CONTEXT *xc, 5587639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5597639Sgblack@eecs.umich.edu { 5607396Sgblack@eecs.umich.edu Fault fault = NoFault; 5617396Sgblack@eecs.umich.edu 5627396Sgblack@eecs.umich.edu %(op_decl)s; 5637370Sgblack@eecs.umich.edu %(op_rd)s; 5647396Sgblack@eecs.umich.edu 5657370Sgblack@eecs.umich.edu if (%(predicate_test)s) 5667370Sgblack@eecs.umich.edu { 5677396Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5687396Sgblack@eecs.umich.edu %(postacc_code)s; 5697370Sgblack@eecs.umich.edu 5707371Sgblack@eecs.umich.edu if (fault == NoFault) { 5717371Sgblack@eecs.umich.edu %(op_wb)s; 5727396Sgblack@eecs.umich.edu } 5737396Sgblack@eecs.umich.edu } 5747639Sgblack@eecs.umich.edu 5757639Sgblack@eecs.umich.edu return fault; 5767639Sgblack@eecs.umich.edu } 5777396Sgblack@eecs.umich.edu}}; 5787371Sgblack@eecs.umich.edu 5797396Sgblack@eecs.umich.edudef template RfeDeclare {{ 5807371Sgblack@eecs.umich.edu /** 5817371Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5827396Sgblack@eecs.umich.edu */ 5837396Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5847371Sgblack@eecs.umich.edu { 5857371Sgblack@eecs.umich.edu public: 5867371Sgblack@eecs.umich.edu 5877396Sgblack@eecs.umich.edu /// Constructor. 5887396Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5897396Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5907639Sgblack@eecs.umich.edu 5917396Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5927639Sgblack@eecs.umich.edu 5937639Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5947396Sgblack@eecs.umich.edu 5957396Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5967396Sgblack@eecs.umich.edu }; 5977371Sgblack@eecs.umich.edu}}; 5987396Sgblack@eecs.umich.edu 5997371Sgblack@eecs.umich.edudef template SrsDeclare {{ 6007371Sgblack@eecs.umich.edu /** 6017396Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6027396Sgblack@eecs.umich.edu */ 6037371Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6047371Sgblack@eecs.umich.edu { 6057371Sgblack@eecs.umich.edu public: 6067396Sgblack@eecs.umich.edu 6077396Sgblack@eecs.umich.edu /// Constructor. 6087639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6097639Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6107639Sgblack@eecs.umich.edu 6117396Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6127371Sgblack@eecs.umich.edu 6137396Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6147371Sgblack@eecs.umich.edu 6157371Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6167396Sgblack@eecs.umich.edu }; 6177396Sgblack@eecs.umich.edu}}; 6187371Sgblack@eecs.umich.edu 6197371Sgblack@eecs.umich.edudef template SwapDeclare {{ 6207371Sgblack@eecs.umich.edu /** 6217396Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6227396Sgblack@eecs.umich.edu */ 6237396Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6247639Sgblack@eecs.umich.edu { 6257396Sgblack@eecs.umich.edu public: 6267639Sgblack@eecs.umich.edu 6277639Sgblack@eecs.umich.edu /// Constructor. 6287396Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6297396Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6307396Sgblack@eecs.umich.edu 6317371Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6327396Sgblack@eecs.umich.edu 6337371Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6347371Sgblack@eecs.umich.edu 6357396Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6367396Sgblack@eecs.umich.edu }; 6377371Sgblack@eecs.umich.edu}}; 6387371Sgblack@eecs.umich.edu 6397371Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6407396Sgblack@eecs.umich.edu /** 6417639Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6427639Sgblack@eecs.umich.edu */ 6437396Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6447371Sgblack@eecs.umich.edu { 6457396Sgblack@eecs.umich.edu public: 6467371Sgblack@eecs.umich.edu 6477371Sgblack@eecs.umich.edu /// Constructor. 6487396Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6497396Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6507371Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6517371Sgblack@eecs.umich.edu 6527371Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6537396Sgblack@eecs.umich.edu 6547396Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6557396Sgblack@eecs.umich.edu 6567639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6577639Sgblack@eecs.umich.edu }; 6587396Sgblack@eecs.umich.edu}}; 6597396Sgblack@eecs.umich.edu 6607396Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6617371Sgblack@eecs.umich.edu /** 6627396Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6637371Sgblack@eecs.umich.edu */ 6647371Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6657396Sgblack@eecs.umich.edu { 6667396Sgblack@eecs.umich.edu public: 6677371Sgblack@eecs.umich.edu 6687381Sgblack@eecs.umich.edu /// Constructor. 6697381Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6707381Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6717381Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6727381Sgblack@eecs.umich.edu 6737381Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6747381Sgblack@eecs.umich.edu 6757373Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6767373Sgblack@eecs.umich.edu 6777397Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6787397Sgblack@eecs.umich.edu }; 6797381Sgblack@eecs.umich.edu}}; 6807373Sgblack@eecs.umich.edu 6817381Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6827639Sgblack@eecs.umich.edu /** 6837397Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6847373Sgblack@eecs.umich.edu */ 6857396Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6867373Sgblack@eecs.umich.edu { 6877373Sgblack@eecs.umich.edu public: 6887396Sgblack@eecs.umich.edu 6897396Sgblack@eecs.umich.edu /// Constructor. 6907373Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6917373Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6927373Sgblack@eecs.umich.edu 6937397Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6947397Sgblack@eecs.umich.edu 6957381Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6967397Sgblack@eecs.umich.edu 6977397Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6987639Sgblack@eecs.umich.edu 6997397Sgblack@eecs.umich.edu virtual void 7007397Sgblack@eecs.umich.edu annotateFault(ArmFault *fault) { 7017397Sgblack@eecs.umich.edu %(fa_code)s 7027373Sgblack@eecs.umich.edu } 7037396Sgblack@eecs.umich.edu }; 7047373Sgblack@eecs.umich.edu}}; 7057373Sgblack@eecs.umich.edu 7067396Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7077396Sgblack@eecs.umich.edu /** 7087373Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7097373Sgblack@eecs.umich.edu */ 7107373Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7117397Sgblack@eecs.umich.edu { 7127397Sgblack@eecs.umich.edu public: 7137381Sgblack@eecs.umich.edu 7147373Sgblack@eecs.umich.edu /// Constructor. 7157381Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7167639Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7177397Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7187373Sgblack@eecs.umich.edu 7197396Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7207373Sgblack@eecs.umich.edu 7217373Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7227396Sgblack@eecs.umich.edu 7237396Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7247373Sgblack@eecs.umich.edu }; 7257373Sgblack@eecs.umich.edu}}; 7267373Sgblack@eecs.umich.edu 7277397Sgblack@eecs.umich.edudef template StoreDRegDeclare {{ 7287397Sgblack@eecs.umich.edu /** 7297381Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7307397Sgblack@eecs.umich.edu */ 7317397Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7327639Sgblack@eecs.umich.edu { 7337397Sgblack@eecs.umich.edu public: 7347397Sgblack@eecs.umich.edu 7357397Sgblack@eecs.umich.edu /// Constructor. 7367373Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7377396Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7387373Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7397373Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7407396Sgblack@eecs.umich.edu uint32_t _index); 7417396Sgblack@eecs.umich.edu 7427373Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7437373Sgblack@eecs.umich.edu 7447380Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7457397Sgblack@eecs.umich.edu 7467397Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7477397Sgblack@eecs.umich.edu }; 7487381Sgblack@eecs.umich.edu}}; 7497388Sgblack@eecs.umich.edu 7507381Sgblack@eecs.umich.edudef template StoreRegDeclare {{ 7517639Sgblack@eecs.umich.edu /** 7527397Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7537380Sgblack@eecs.umich.edu */ 7547396Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7557380Sgblack@eecs.umich.edu { 7567380Sgblack@eecs.umich.edu public: 7577396Sgblack@eecs.umich.edu 7587396Sgblack@eecs.umich.edu /// Constructor. 7597380Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7607380Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7617380Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7627397Sgblack@eecs.umich.edu uint32_t _index); 7637397Sgblack@eecs.umich.edu 7647397Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7657397Sgblack@eecs.umich.edu 7667397Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7677397Sgblack@eecs.umich.edu 7687381Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7697639Sgblack@eecs.umich.edu 7707397Sgblack@eecs.umich.edu virtual void 7717380Sgblack@eecs.umich.edu annotateFault(ArmFault *fault) { 7727380Sgblack@eecs.umich.edu %(fa_code)s 7737396Sgblack@eecs.umich.edu } 7747380Sgblack@eecs.umich.edu }; 7757380Sgblack@eecs.umich.edu}}; 7767396Sgblack@eecs.umich.edu 7777396Sgblack@eecs.umich.edudef template LoadDRegDeclare {{ 7787380Sgblack@eecs.umich.edu /** 7797380Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7807380Sgblack@eecs.umich.edu */ 7817397Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7827397Sgblack@eecs.umich.edu { 7837397Sgblack@eecs.umich.edu public: 7847381Sgblack@eecs.umich.edu 7857388Sgblack@eecs.umich.edu /// Constructor. 7867381Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7877639Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7887397Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7897380Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7907396Sgblack@eecs.umich.edu uint32_t _index); 7917380Sgblack@eecs.umich.edu 7927380Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7937396Sgblack@eecs.umich.edu 7947396Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7957380Sgblack@eecs.umich.edu 7967380Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7977380Sgblack@eecs.umich.edu }; 7987397Sgblack@eecs.umich.edu}}; 7997397Sgblack@eecs.umich.edu 8007397Sgblack@eecs.umich.edudef template LoadRegDeclare {{ 8017397Sgblack@eecs.umich.edu /** 8027397Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8037397Sgblack@eecs.umich.edu */ 8047381Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8057639Sgblack@eecs.umich.edu { 8067397Sgblack@eecs.umich.edu public: 8077380Sgblack@eecs.umich.edu 8087380Sgblack@eecs.umich.edu /// Constructor. 8097396Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8107380Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 8117380Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 8127396Sgblack@eecs.umich.edu uint32_t _index); 8137396Sgblack@eecs.umich.edu 8147380Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8157380Sgblack@eecs.umich.edu 8167373Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8177397Sgblack@eecs.umich.edu 8187397Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8197397Sgblack@eecs.umich.edu 8207380Sgblack@eecs.umich.edu virtual void 8217381Sgblack@eecs.umich.edu annotateFault(ArmFault *fault) { 8227387Sgblack@eecs.umich.edu %(fa_code)s 8237381Sgblack@eecs.umich.edu } 8247639Sgblack@eecs.umich.edu }; 8257397Sgblack@eecs.umich.edu}}; 8267373Sgblack@eecs.umich.edu 8277396Sgblack@eecs.umich.edudef template LoadImmDeclare {{ 8287373Sgblack@eecs.umich.edu /** 8297373Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 8307396Sgblack@eecs.umich.edu */ 8317396Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 8327373Sgblack@eecs.umich.edu { 8337373Sgblack@eecs.umich.edu public: 8347373Sgblack@eecs.umich.edu 8357397Sgblack@eecs.umich.edu /// Constructor. 8367397Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 8377397Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8387397Sgblack@eecs.umich.edu 8397380Sgblack@eecs.umich.edu %(BasicExecDeclare)s 8407397Sgblack@eecs.umich.edu 8417397Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 8427381Sgblack@eecs.umich.edu 8437639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 8447397Sgblack@eecs.umich.edu 8457373Sgblack@eecs.umich.edu virtual void 8467373Sgblack@eecs.umich.edu annotateFault(ArmFault *fault) { 8477396Sgblack@eecs.umich.edu %(fa_code)s 8487373Sgblack@eecs.umich.edu } 8497373Sgblack@eecs.umich.edu }; 8507396Sgblack@eecs.umich.edu}}; 8517396Sgblack@eecs.umich.edu 8527373Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 8537373Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8547373Sgblack@eecs.umich.edu}}; 8557397Sgblack@eecs.umich.edu 8567397Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 8577397Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 8587380Sgblack@eecs.umich.edu}}; 8597381Sgblack@eecs.umich.edu 8607387Sgblack@eecs.umich.edudef template RfeConstructor {{ 8617381Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 8627639Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb) 8637397Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8647373Sgblack@eecs.umich.edu (IntRegIndex)_base, (AddrMode)_mode, _wb) 8657396Sgblack@eecs.umich.edu { 8667373Sgblack@eecs.umich.edu %(constructor)s; 8677373Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 8687396Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 8697396Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8707373Sgblack@eecs.umich.edu } 8717373Sgblack@eecs.umich.edu } 8727373Sgblack@eecs.umich.edu#if %(use_uops)d 8737397Sgblack@eecs.umich.edu uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8747397Sgblack@eecs.umich.edu int uopIdx = 0; 8757397Sgblack@eecs.umich.edu uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8767397Sgblack@eecs.umich.edu uops[uopIdx]->setDelayedCommit(); 8777380Sgblack@eecs.umich.edu#if %(use_wb)d 8787397Sgblack@eecs.umich.edu uops[++uopIdx] = new %(wb_decl)s; 8797397Sgblack@eecs.umich.edu uops[uopIdx]->setDelayedCommit(); 8807381Sgblack@eecs.umich.edu#endif 8817639Sgblack@eecs.umich.edu#if %(use_pc)d 8827397Sgblack@eecs.umich.edu uops[++uopIdx] = new %(pc_decl)s; 8837373Sgblack@eecs.umich.edu#endif 8847373Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 8857396Sgblack@eecs.umich.edu uops[uopIdx]->setLastMicroop(); 8867373Sgblack@eecs.umich.edu#endif 8877373Sgblack@eecs.umich.edu } 8887396Sgblack@eecs.umich.edu}}; 8897396Sgblack@eecs.umich.edu 8907373Sgblack@eecs.umich.edudef template SrsConstructor {{ 8917374Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 8927374Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8937397Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8947397Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8957397Sgblack@eecs.umich.edu { 8967381Sgblack@eecs.umich.edu %(constructor)s; 8977397Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 8987397Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 8997639Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9007397Sgblack@eecs.umich.edu } 9017397Sgblack@eecs.umich.edu } 9027397Sgblack@eecs.umich.edu#if %(use_uops)d 9037374Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9047396Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9057374Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9067374Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9077396Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 9087396Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9097374Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9107374Sgblack@eecs.umich.edu#endif 9117374Sgblack@eecs.umich.edu } 9127397Sgblack@eecs.umich.edu}}; 9137397Sgblack@eecs.umich.edu 9147397Sgblack@eecs.umich.edudef template SwapConstructor {{ 9157397Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 9167397Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9177397Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9187381Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9197639Sgblack@eecs.umich.edu { 9207397Sgblack@eecs.umich.edu %(constructor)s; 9217374Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9227396Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9237374Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9247374Sgblack@eecs.umich.edu } 9257396Sgblack@eecs.umich.edu } 9267396Sgblack@eecs.umich.edu } 9277374Sgblack@eecs.umich.edu}}; 9287377Sgblack@eecs.umich.edu 9297398Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 9307398Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 9317398Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9327398Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9337398Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9347639Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9357639Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9367398Sgblack@eecs.umich.edu { 9377639Sgblack@eecs.umich.edu %(constructor)s; 9387398Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9397398Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9407398Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9417398Sgblack@eecs.umich.edu } 9427398Sgblack@eecs.umich.edu } 9437398Sgblack@eecs.umich.edu#if %(use_uops)d 9447398Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9457398Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9467398Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 9477398Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 9487398Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9497398Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9507398Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9517639Sgblack@eecs.umich.edu#endif 9527639Sgblack@eecs.umich.edu } 9537398Sgblack@eecs.umich.edu}}; 9547639Sgblack@eecs.umich.edu 9557398Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 9567398Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 9577398Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9587398Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9597398Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9607398Sgblack@eecs.umich.edu (IntRegIndex)_result, 9617398Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9627398Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9637398Sgblack@eecs.umich.edu { 9647398Sgblack@eecs.umich.edu %(constructor)s; 9657398Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9667398Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9677398Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9687639Sgblack@eecs.umich.edu } 9697639Sgblack@eecs.umich.edu } 9707639Sgblack@eecs.umich.edu#if %(use_uops)d 9717639Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9727639Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9737639Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9747639Sgblack@eecs.umich.edu _base, _add, _imm); 9757398Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 9767398Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 9777398Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 9787398Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 9797398Sgblack@eecs.umich.edu#endif 9807398Sgblack@eecs.umich.edu } 9817398Sgblack@eecs.umich.edu}}; 9827398Sgblack@eecs.umich.edu 9837398Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 9847398Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 9857398Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9867398Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9877398Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9887639Sgblack@eecs.umich.edu { 9897639Sgblack@eecs.umich.edu %(constructor)s; 9907639Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9917639Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 9927639Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9937639Sgblack@eecs.umich.edu } 9947639Sgblack@eecs.umich.edu } 9957398Sgblack@eecs.umich.edu#if %(use_uops)d 9967398Sgblack@eecs.umich.edu assert(numMicroops >= 2); 9977398Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 9987398Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9997398Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10007398Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 10017398Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10027398Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10037398Sgblack@eecs.umich.edu#endif 10047377Sgblack@eecs.umich.edu } 10057377Sgblack@eecs.umich.edu}}; 10067397Sgblack@eecs.umich.edu 10077377Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 10087377Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 10097377Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10107377Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10117377Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10127377Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10137377Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10147389Sgblack@eecs.umich.edu { 10157389Sgblack@eecs.umich.edu %(constructor)s; 10167396Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 10177389Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 10187396Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10197389Sgblack@eecs.umich.edu } 10207389Sgblack@eecs.umich.edu } 10217377Sgblack@eecs.umich.edu#if %(use_uops)d 10227377Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10237377Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10247377Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _result, _dest, 10257396Sgblack@eecs.umich.edu _base, _add, _imm); 10267377Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10277377Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 10287396Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10297396Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10307377Sgblack@eecs.umich.edu#endif 10317377Sgblack@eecs.umich.edu } 10327377Sgblack@eecs.umich.edu}}; 10337397Sgblack@eecs.umich.edu 10347397Sgblack@eecs.umich.edudef template StoreDRegConstructor {{ 10357377Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 10367397Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10377397Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10387377Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10397397Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10407377Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10417397Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10427377Sgblack@eecs.umich.edu (IntRegIndex)_index) 10437377Sgblack@eecs.umich.edu { 10447389Sgblack@eecs.umich.edu %(constructor)s; 10457397Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 10467397Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 10477397Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10487397Sgblack@eecs.umich.edu } 10497389Sgblack@eecs.umich.edu } 10507389Sgblack@eecs.umich.edu#if %(use_uops)d 10517377Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10527377Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10537377Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10547377Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 10557396Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10567377Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 10577377Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10587396Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10597396Sgblack@eecs.umich.edu#endif 10607377Sgblack@eecs.umich.edu } 10617377Sgblack@eecs.umich.edu}}; 10627377Sgblack@eecs.umich.edu 10637377Sgblack@eecs.umich.edudef template StoreRegConstructor {{ 10647397Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 10657389Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10667389Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10677377Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10687377Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10697377Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10707377Sgblack@eecs.umich.edu (IntRegIndex)_index) 10717377Sgblack@eecs.umich.edu { 10727377Sgblack@eecs.umich.edu %(constructor)s; 10737377Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 10747389Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 10757389Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10767396Sgblack@eecs.umich.edu } 10777389Sgblack@eecs.umich.edu } 10787389Sgblack@eecs.umich.edu#if %(use_uops)d 10797377Sgblack@eecs.umich.edu assert(numMicroops >= 2); 10807377Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 10817377Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10827377Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 10837396Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 10847377Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 10857377Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 10867396Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 10877396Sgblack@eecs.umich.edu#endif 10887377Sgblack@eecs.umich.edu } 10897377Sgblack@eecs.umich.edu}}; 10907377Sgblack@eecs.umich.edu 10917389Sgblack@eecs.umich.edudef template LoadDRegConstructor {{ 10927389Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 10937397Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10947377Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10957397Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10967397Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10977377Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10987397Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10997377Sgblack@eecs.umich.edu (IntRegIndex)_index) 11007397Sgblack@eecs.umich.edu { 11017377Sgblack@eecs.umich.edu %(constructor)s; 11027377Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 11037389Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 11047397Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11057397Sgblack@eecs.umich.edu } 11067389Sgblack@eecs.umich.edu } 11077389Sgblack@eecs.umich.edu#if %(use_uops)d 11087377Sgblack@eecs.umich.edu assert(numMicroops >= 2); 11097377Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 11107377Sgblack@eecs.umich.edu if ((_dest == _index) || (_dest2 == _index)) { 11117377Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = INTREG_UREG0; 11127396Sgblack@eecs.umich.edu uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11137377Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 11147377Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 11157396Sgblack@eecs.umich.edu uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11167396Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 11177377Sgblack@eecs.umich.edu uops[1]->setDelayedCommit(); 11187389Sgblack@eecs.umich.edu uops[2] = new %(wb_decl)s; 11197389Sgblack@eecs.umich.edu uops[2]->setLastMicroop(); 11207389Sgblack@eecs.umich.edu } else { 11217397Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = index; 11227389Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11237389Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 11247389Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 11257389Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 11267389Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 11277389Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 11287389Sgblack@eecs.umich.edu } 11297389Sgblack@eecs.umich.edu#endif 11307389Sgblack@eecs.umich.edu } 11317389Sgblack@eecs.umich.edu}}; 11327389Sgblack@eecs.umich.edu 11337389Sgblack@eecs.umich.edudef template LoadRegConstructor {{ 11347396Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 11357389Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 11367389Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11377396Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11387396Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11397389Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 11407389Sgblack@eecs.umich.edu (IntRegIndex)_index) 11417389Sgblack@eecs.umich.edu { 11427397Sgblack@eecs.umich.edu %(constructor)s; 11437397Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11447389Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 11457397Sgblack@eecs.umich.edu conditional = true; 11467397Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 11477389Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11487397Sgblack@eecs.umich.edu } 11497389Sgblack@eecs.umich.edu } 11507397Sgblack@eecs.umich.edu#if %(use_uops)d 11517389Sgblack@eecs.umich.edu assert(numMicroops >= 2); 11527389Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 11537389Sgblack@eecs.umich.edu if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11547389Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = index; 11557389Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11567389Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 11577389Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 11587396Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 11597389Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 11607389Sgblack@eecs.umich.edu uops[1]->setDelayedCommit(); 11617396Sgblack@eecs.umich.edu uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11627396Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsControl); 11637389Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsIndirectControl); 11647389Sgblack@eecs.umich.edu if (conditional) 11657389Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsCondControl); 11667389Sgblack@eecs.umich.edu else 11677397Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsUncondControl); 11687389Sgblack@eecs.umich.edu uops[2]->setLastMicroop(); 11697389Sgblack@eecs.umich.edu } else if(_dest == _index) { 11707389Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = INTREG_UREG0; 11717389Sgblack@eecs.umich.edu uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11727389Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 11737389Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 11747389Sgblack@eecs.umich.edu uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11757389Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 11767389Sgblack@eecs.umich.edu uops[1]->setDelayedCommit(); 11777389Sgblack@eecs.umich.edu uops[2] = new %(wb_decl)s; 11787389Sgblack@eecs.umich.edu uops[2]->setLastMicroop(); 11797389Sgblack@eecs.umich.edu } else { 11807396Sgblack@eecs.umich.edu IntRegIndex wbIndexReg = index; 11817389Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11827389Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index); 11837396Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 11847396Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 11857389Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 11867389Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 11877389Sgblack@eecs.umich.edu 11887397Sgblack@eecs.umich.edu } 11897389Sgblack@eecs.umich.edu#else 11907397Sgblack@eecs.umich.edu if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11917397Sgblack@eecs.umich.edu flags[IsControl] = true; 11927389Sgblack@eecs.umich.edu flags[IsIndirectControl] = true; 11937397Sgblack@eecs.umich.edu if (conditional) 11947389Sgblack@eecs.umich.edu flags[IsCondControl] = true; 11957397Sgblack@eecs.umich.edu else 11967389Sgblack@eecs.umich.edu flags[IsUncondControl] = true; 11977389Sgblack@eecs.umich.edu } 11987389Sgblack@eecs.umich.edu#endif 11997389Sgblack@eecs.umich.edu } 12007389Sgblack@eecs.umich.edu}}; 12017389Sgblack@eecs.umich.edu 12027389Sgblack@eecs.umich.edudef template LoadImmConstructor {{ 12037396Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 12047389Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 12057389Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 12067396Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 12077396Sgblack@eecs.umich.edu { 12087389Sgblack@eecs.umich.edu %(constructor)s; 12097322Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 12107379Sgblack@eecs.umich.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 12117379Sgblack@eecs.umich.edu conditional = true; 12127379Sgblack@eecs.umich.edu for (int x = 0; x < _numDestRegs; x++) { 12137379Sgblack@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12147379Sgblack@eecs.umich.edu } 12157379Sgblack@eecs.umich.edu } 12167379Sgblack@eecs.umich.edu#if %(use_uops)d 12177379Sgblack@eecs.umich.edu assert(numMicroops >= 2); 12187397Sgblack@eecs.umich.edu uops = new StaticInstPtr[numMicroops]; 12197397Sgblack@eecs.umich.edu if (_dest == INTREG_PC && !isFloating() && !isVector()) { 12207397Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 12217381Sgblack@eecs.umich.edu _imm); 12227379Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 12237381Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 12247639Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 12257397Sgblack@eecs.umich.edu uops[1]->setDelayedCommit(); 12267379Sgblack@eecs.umich.edu uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12277396Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsControl); 12287379Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsIndirectControl); 12297379Sgblack@eecs.umich.edu /* Also set flags on the macroop so that pre-microop decomposition 12307396Sgblack@eecs.umich.edu branch prediction can work */ 12317396Sgblack@eecs.umich.edu setFlag(StaticInst::IsControl); 12327379Sgblack@eecs.umich.edu setFlag(StaticInst::IsIndirectControl); 12337379Sgblack@eecs.umich.edu if (conditional) { 12347379Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsCondControl); 12357397Sgblack@eecs.umich.edu setFlag(StaticInst::IsCondControl); 12367397Sgblack@eecs.umich.edu } else { 12377397Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsUncondControl); 12387397Sgblack@eecs.umich.edu setFlag(StaticInst::IsUncondControl); 12397397Sgblack@eecs.umich.edu } 12407397Sgblack@eecs.umich.edu if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) { 12417381Sgblack@eecs.umich.edu uops[2]->setFlag(StaticInst::IsReturn); 12427639Sgblack@eecs.umich.edu setFlag(StaticInst::IsReturn); 12437397Sgblack@eecs.umich.edu } 12447379Sgblack@eecs.umich.edu uops[2]->setLastMicroop(); 12457379Sgblack@eecs.umich.edu } else { 12467379Sgblack@eecs.umich.edu uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12477396Sgblack@eecs.umich.edu uops[0]->setDelayedCommit(); 12487379Sgblack@eecs.umich.edu uops[0]->setFirstMicroop(); 12497379Sgblack@eecs.umich.edu uops[1] = new %(wb_decl)s; 12507396Sgblack@eecs.umich.edu uops[1]->setLastMicroop(); 12517396Sgblack@eecs.umich.edu } 12527379Sgblack@eecs.umich.edu#else 12537379Sgblack@eecs.umich.edu if (_dest == INTREG_PC && !isFloating() && !isVector()) { 12547379Sgblack@eecs.umich.edu flags[IsControl] = true; 12557397Sgblack@eecs.umich.edu flags[IsIndirectControl] = true; 12567397Sgblack@eecs.umich.edu if (conditional) 12577397Sgblack@eecs.umich.edu flags[IsCondControl] = true; 12587381Sgblack@eecs.umich.edu else 12597379Sgblack@eecs.umich.edu flags[IsUncondControl] = true; 12607381Sgblack@eecs.umich.edu } 12617639Sgblack@eecs.umich.edu#endif 12627397Sgblack@eecs.umich.edu } 12637379Sgblack@eecs.umich.edu}}; 12647396Sgblack@eecs.umich.edu 12657379Sgblack@eecs.umich.edu