mem.isa revision 11303
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 310666SAli.Saidi@ARM.com// Copyright (c) 2010, 2012, 2014 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 4510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 5410196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 637646Sgene.wu@arm.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 6410196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 657646Sgene.wu@arm.com Trace::InstRecord *traceData) const 667646Sgene.wu@arm.com { 677646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 687646Sgene.wu@arm.com return NoFault; 697646Sgene.wu@arm.com } 707646Sgene.wu@arm.com}}; 717646Sgene.wu@arm.com 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edudef template SwapExecute {{ 7410196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 757205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767205Sgblack@eecs.umich.edu { 777205Sgblack@eecs.umich.edu Addr EA; 787205Sgblack@eecs.umich.edu Fault fault = NoFault; 797205Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu %(op_decl)s; 817205Sgblack@eecs.umich.edu uint64_t memData = 0; 827205Sgblack@eecs.umich.edu %(op_rd)s; 837205Sgblack@eecs.umich.edu %(ea_code)s; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu if (%(predicate_test)s) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu %(preacc_code)s; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu if (fault == NoFault) { 908442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 918442Sgblack@eecs.umich.edu &memData); 927205Sgblack@eecs.umich.edu } 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu %(postacc_code)s; 967205Sgblack@eecs.umich.edu } 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu %(op_wb)s; 1007205Sgblack@eecs.umich.edu } 1017597Sminkyu.jeong@arm.com } else { 1027597Sminkyu.jeong@arm.com xc->setPredicate(false); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057205Sgblack@eecs.umich.edu return fault; 1067205Sgblack@eecs.umich.edu } 1077205Sgblack@eecs.umich.edu}}; 1087205Sgblack@eecs.umich.edu 1097205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 11010196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 1117205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1127205Sgblack@eecs.umich.edu { 1137205Sgblack@eecs.umich.edu Addr EA; 1147205Sgblack@eecs.umich.edu Fault fault = NoFault; 1157205Sgblack@eecs.umich.edu 1167205Sgblack@eecs.umich.edu %(op_decl)s; 1177205Sgblack@eecs.umich.edu uint64_t memData = 0; 1187205Sgblack@eecs.umich.edu %(op_rd)s; 1197205Sgblack@eecs.umich.edu %(ea_code)s; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1227205Sgblack@eecs.umich.edu { 1237205Sgblack@eecs.umich.edu %(preacc_code)s; 1247205Sgblack@eecs.umich.edu 1257205Sgblack@eecs.umich.edu if (fault == NoFault) { 1268442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1278442Sgblack@eecs.umich.edu &memData); 1287205Sgblack@eecs.umich.edu } 1297597Sminkyu.jeong@arm.com } else { 1307597Sminkyu.jeong@arm.com xc->setPredicate(false); 1317205Sgblack@eecs.umich.edu } 1327205Sgblack@eecs.umich.edu 1337205Sgblack@eecs.umich.edu return fault; 1347205Sgblack@eecs.umich.edu } 1357205Sgblack@eecs.umich.edu}}; 1367205Sgblack@eecs.umich.edu 1377205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1387205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 13910196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 1407205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1417205Sgblack@eecs.umich.edu { 1427205Sgblack@eecs.umich.edu Fault fault = NoFault; 1437205Sgblack@eecs.umich.edu 1447205Sgblack@eecs.umich.edu %(op_decl)s; 1457205Sgblack@eecs.umich.edu %(op_rd)s; 1467205Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1487205Sgblack@eecs.umich.edu { 1497205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1508442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1518442Sgblack@eecs.umich.edu uint64_t memData = Mem; 1527205Sgblack@eecs.umich.edu 1537205Sgblack@eecs.umich.edu %(postacc_code)s; 1547205Sgblack@eecs.umich.edu 1557205Sgblack@eecs.umich.edu if (fault == NoFault) { 1567205Sgblack@eecs.umich.edu %(op_wb)s; 1577205Sgblack@eecs.umich.edu } 1587205Sgblack@eecs.umich.edu } 1597205Sgblack@eecs.umich.edu 1607205Sgblack@eecs.umich.edu return fault; 1617205Sgblack@eecs.umich.edu } 1627205Sgblack@eecs.umich.edu}}; 1637205Sgblack@eecs.umich.edu 1647119Sgblack@eecs.umich.edudef template LoadExecute {{ 16510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 1667119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1677119Sgblack@eecs.umich.edu { 1687119Sgblack@eecs.umich.edu Addr EA; 1697119Sgblack@eecs.umich.edu Fault fault = NoFault; 1707119Sgblack@eecs.umich.edu 1717119Sgblack@eecs.umich.edu %(op_decl)s; 1727119Sgblack@eecs.umich.edu %(op_rd)s; 1737119Sgblack@eecs.umich.edu %(ea_code)s; 1747119Sgblack@eecs.umich.edu 1757119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1767119Sgblack@eecs.umich.edu { 1777119Sgblack@eecs.umich.edu if (fault == NoFault) { 1788442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1797119Sgblack@eecs.umich.edu %(memacc_code)s; 1807119Sgblack@eecs.umich.edu } 1817119Sgblack@eecs.umich.edu 1827119Sgblack@eecs.umich.edu if (fault == NoFault) { 1837119Sgblack@eecs.umich.edu %(op_wb)s; 1847119Sgblack@eecs.umich.edu } 1857597Sminkyu.jeong@arm.com } else { 1867597Sminkyu.jeong@arm.com xc->setPredicate(false); 1877119Sgblack@eecs.umich.edu } 1887119Sgblack@eecs.umich.edu 1897119Sgblack@eecs.umich.edu return fault; 1907119Sgblack@eecs.umich.edu } 1917119Sgblack@eecs.umich.edu}}; 1927119Sgblack@eecs.umich.edu 1937639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1947639Sgblack@eecs.umich.edu template <class Element> 1957639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 19610196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1977639Sgblack@eecs.umich.edu { 1987639Sgblack@eecs.umich.edu Addr EA; 1997639Sgblack@eecs.umich.edu Fault fault = NoFault; 2007639Sgblack@eecs.umich.edu 2017639Sgblack@eecs.umich.edu %(op_decl)s; 2027639Sgblack@eecs.umich.edu %(mem_decl)s; 2037639Sgblack@eecs.umich.edu %(op_rd)s; 2047639Sgblack@eecs.umich.edu %(ea_code)s; 2057639Sgblack@eecs.umich.edu 2067639Sgblack@eecs.umich.edu MemUnion memUnion; 2077639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2087639Sgblack@eecs.umich.edu 2097639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2107639Sgblack@eecs.umich.edu { 2117639Sgblack@eecs.umich.edu if (fault == NoFault) { 2128444Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 2137639Sgblack@eecs.umich.edu %(memacc_code)s; 2147639Sgblack@eecs.umich.edu } 2157639Sgblack@eecs.umich.edu 2167639Sgblack@eecs.umich.edu if (fault == NoFault) { 2177639Sgblack@eecs.umich.edu %(op_wb)s; 2187639Sgblack@eecs.umich.edu } 2198072SGiacomo.Gabrielli@arm.com } else { 2208072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2217639Sgblack@eecs.umich.edu } 2227639Sgblack@eecs.umich.edu 2237639Sgblack@eecs.umich.edu return fault; 2247639Sgblack@eecs.umich.edu } 2257639Sgblack@eecs.umich.edu}}; 2267639Sgblack@eecs.umich.edu 2277120Sgblack@eecs.umich.edudef template StoreExecute {{ 22810196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 2297120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2307120Sgblack@eecs.umich.edu { 2317120Sgblack@eecs.umich.edu Addr EA; 2327120Sgblack@eecs.umich.edu Fault fault = NoFault; 2337120Sgblack@eecs.umich.edu 2347120Sgblack@eecs.umich.edu %(op_decl)s; 2357120Sgblack@eecs.umich.edu %(op_rd)s; 2367120Sgblack@eecs.umich.edu %(ea_code)s; 2377120Sgblack@eecs.umich.edu 2387120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2397120Sgblack@eecs.umich.edu { 2407120Sgblack@eecs.umich.edu if (fault == NoFault) { 2417120Sgblack@eecs.umich.edu %(memacc_code)s; 2427120Sgblack@eecs.umich.edu } 2437120Sgblack@eecs.umich.edu 2447120Sgblack@eecs.umich.edu if (fault == NoFault) { 2458442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2468442Sgblack@eecs.umich.edu memAccessFlags, NULL); 2477120Sgblack@eecs.umich.edu } 2487120Sgblack@eecs.umich.edu 2497120Sgblack@eecs.umich.edu if (fault == NoFault) { 2507120Sgblack@eecs.umich.edu %(op_wb)s; 2517120Sgblack@eecs.umich.edu } 2527597Sminkyu.jeong@arm.com } else { 2537597Sminkyu.jeong@arm.com xc->setPredicate(false); 2547120Sgblack@eecs.umich.edu } 2557120Sgblack@eecs.umich.edu 2567120Sgblack@eecs.umich.edu return fault; 2577120Sgblack@eecs.umich.edu } 2587120Sgblack@eecs.umich.edu}}; 2597120Sgblack@eecs.umich.edu 2607639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2617639Sgblack@eecs.umich.edu template <class Element> 2627639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 26310196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 2647639Sgblack@eecs.umich.edu { 2657639Sgblack@eecs.umich.edu Addr EA; 2667639Sgblack@eecs.umich.edu Fault fault = NoFault; 2677639Sgblack@eecs.umich.edu 2687639Sgblack@eecs.umich.edu %(op_decl)s; 2697639Sgblack@eecs.umich.edu %(mem_decl)s; 2707639Sgblack@eecs.umich.edu %(op_rd)s; 2717639Sgblack@eecs.umich.edu %(ea_code)s; 2727639Sgblack@eecs.umich.edu 2737639Sgblack@eecs.umich.edu MemUnion memUnion; 2747639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2757639Sgblack@eecs.umich.edu 2767639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2777639Sgblack@eecs.umich.edu { 2787639Sgblack@eecs.umich.edu if (fault == NoFault) { 2797639Sgblack@eecs.umich.edu %(memacc_code)s; 2807639Sgblack@eecs.umich.edu } 2817639Sgblack@eecs.umich.edu 2827639Sgblack@eecs.umich.edu if (fault == NoFault) { 2838444Sgblack@eecs.umich.edu fault = xc->writeMem(dataPtr, %(size)d, EA, 2848444Sgblack@eecs.umich.edu memAccessFlags, NULL); 2857639Sgblack@eecs.umich.edu } 2867639Sgblack@eecs.umich.edu 2877639Sgblack@eecs.umich.edu if (fault == NoFault) { 2887639Sgblack@eecs.umich.edu %(op_wb)s; 2897639Sgblack@eecs.umich.edu } 2908072SGiacomo.Gabrielli@arm.com } else { 2918072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2927639Sgblack@eecs.umich.edu } 2937639Sgblack@eecs.umich.edu 2947639Sgblack@eecs.umich.edu return fault; 2957639Sgblack@eecs.umich.edu } 2967639Sgblack@eecs.umich.edu}}; 2977639Sgblack@eecs.umich.edu 2987303Sgblack@eecs.umich.edudef template StoreExExecute {{ 29910196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 3007303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3017303Sgblack@eecs.umich.edu { 3027303Sgblack@eecs.umich.edu Addr EA; 3037303Sgblack@eecs.umich.edu Fault fault = NoFault; 3047303Sgblack@eecs.umich.edu 3057303Sgblack@eecs.umich.edu %(op_decl)s; 3067303Sgblack@eecs.umich.edu %(op_rd)s; 3077303Sgblack@eecs.umich.edu %(ea_code)s; 3087303Sgblack@eecs.umich.edu 3097303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3107303Sgblack@eecs.umich.edu { 3117303Sgblack@eecs.umich.edu if (fault == NoFault) { 3127303Sgblack@eecs.umich.edu %(memacc_code)s; 3137303Sgblack@eecs.umich.edu } 3147303Sgblack@eecs.umich.edu 3157303Sgblack@eecs.umich.edu uint64_t writeResult; 3167303Sgblack@eecs.umich.edu 3177303Sgblack@eecs.umich.edu if (fault == NoFault) { 3188442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3198442Sgblack@eecs.umich.edu &writeResult); 3207303Sgblack@eecs.umich.edu } 3217303Sgblack@eecs.umich.edu 3227303Sgblack@eecs.umich.edu if (fault == NoFault) { 3237303Sgblack@eecs.umich.edu %(postacc_code)s; 3247303Sgblack@eecs.umich.edu } 3257303Sgblack@eecs.umich.edu 3267303Sgblack@eecs.umich.edu if (fault == NoFault) { 3277303Sgblack@eecs.umich.edu %(op_wb)s; 3287303Sgblack@eecs.umich.edu } 3297597Sminkyu.jeong@arm.com } else { 3307597Sminkyu.jeong@arm.com xc->setPredicate(false); 3317303Sgblack@eecs.umich.edu } 3327303Sgblack@eecs.umich.edu 3337303Sgblack@eecs.umich.edu return fault; 3347303Sgblack@eecs.umich.edu } 3357303Sgblack@eecs.umich.edu}}; 3367303Sgblack@eecs.umich.edu 3377303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 33810196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 3397303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3407303Sgblack@eecs.umich.edu { 3417303Sgblack@eecs.umich.edu Addr EA; 3427303Sgblack@eecs.umich.edu Fault fault = NoFault; 3437303Sgblack@eecs.umich.edu 3447303Sgblack@eecs.umich.edu %(op_decl)s; 3457303Sgblack@eecs.umich.edu %(op_rd)s; 3467303Sgblack@eecs.umich.edu %(ea_code)s; 3477303Sgblack@eecs.umich.edu 3487303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3497303Sgblack@eecs.umich.edu { 3507303Sgblack@eecs.umich.edu if (fault == NoFault) { 3517303Sgblack@eecs.umich.edu %(memacc_code)s; 3527303Sgblack@eecs.umich.edu } 3537303Sgblack@eecs.umich.edu 3547303Sgblack@eecs.umich.edu if (fault == NoFault) { 3558442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3568442Sgblack@eecs.umich.edu NULL); 3577303Sgblack@eecs.umich.edu } 3587597Sminkyu.jeong@arm.com } else { 3597597Sminkyu.jeong@arm.com xc->setPredicate(false); 3607303Sgblack@eecs.umich.edu } 3617408Sgblack@eecs.umich.edu 3627303Sgblack@eecs.umich.edu return fault; 3637303Sgblack@eecs.umich.edu } 3647303Sgblack@eecs.umich.edu}}; 3657303Sgblack@eecs.umich.edu 3667120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 36710196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 3687120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3697120Sgblack@eecs.umich.edu { 3707120Sgblack@eecs.umich.edu Addr EA; 3717120Sgblack@eecs.umich.edu Fault fault = NoFault; 3727120Sgblack@eecs.umich.edu 3737120Sgblack@eecs.umich.edu %(op_decl)s; 3747120Sgblack@eecs.umich.edu %(op_rd)s; 3757120Sgblack@eecs.umich.edu %(ea_code)s; 3767120Sgblack@eecs.umich.edu 3777120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3787120Sgblack@eecs.umich.edu { 3797120Sgblack@eecs.umich.edu if (fault == NoFault) { 3807120Sgblack@eecs.umich.edu %(memacc_code)s; 3817120Sgblack@eecs.umich.edu } 3827120Sgblack@eecs.umich.edu 3837120Sgblack@eecs.umich.edu if (fault == NoFault) { 3848442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3858442Sgblack@eecs.umich.edu NULL); 3867120Sgblack@eecs.umich.edu } 3877597Sminkyu.jeong@arm.com } else { 3887597Sminkyu.jeong@arm.com xc->setPredicate(false); 3897120Sgblack@eecs.umich.edu } 3907120Sgblack@eecs.umich.edu 3917120Sgblack@eecs.umich.edu return fault; 3927120Sgblack@eecs.umich.edu } 3937120Sgblack@eecs.umich.edu}}; 3947120Sgblack@eecs.umich.edu 3957639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3967639Sgblack@eecs.umich.edu template <class Element> 3977639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 39810196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 3997639Sgblack@eecs.umich.edu { 4007639Sgblack@eecs.umich.edu Addr EA; 4017639Sgblack@eecs.umich.edu Fault fault = NoFault; 4027639Sgblack@eecs.umich.edu 4037639Sgblack@eecs.umich.edu %(op_decl)s; 4047639Sgblack@eecs.umich.edu %(mem_decl)s; 4057639Sgblack@eecs.umich.edu %(op_rd)s; 4067639Sgblack@eecs.umich.edu %(ea_code)s; 4077639Sgblack@eecs.umich.edu 4087639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4097639Sgblack@eecs.umich.edu { 4107639Sgblack@eecs.umich.edu MemUnion memUnion; 4117639Sgblack@eecs.umich.edu if (fault == NoFault) { 4127639Sgblack@eecs.umich.edu %(memacc_code)s; 4137639Sgblack@eecs.umich.edu } 4147639Sgblack@eecs.umich.edu 4157639Sgblack@eecs.umich.edu if (fault == NoFault) { 4168444Sgblack@eecs.umich.edu fault = xc->writeMem(memUnion.bytes, %(size)d, EA, 4178444Sgblack@eecs.umich.edu memAccessFlags, NULL); 4187639Sgblack@eecs.umich.edu } 4198072SGiacomo.Gabrielli@arm.com } else { 4208072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4217639Sgblack@eecs.umich.edu } 4227639Sgblack@eecs.umich.edu 4237639Sgblack@eecs.umich.edu return fault; 4247639Sgblack@eecs.umich.edu } 4257639Sgblack@eecs.umich.edu}}; 4267639Sgblack@eecs.umich.edu 4277119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 42810196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 4297119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4307119Sgblack@eecs.umich.edu { 4317119Sgblack@eecs.umich.edu Addr EA; 4327119Sgblack@eecs.umich.edu Fault fault = NoFault; 4337119Sgblack@eecs.umich.edu 4347119Sgblack@eecs.umich.edu %(op_src_decl)s; 4357119Sgblack@eecs.umich.edu %(op_rd)s; 4367119Sgblack@eecs.umich.edu %(ea_code)s; 4377119Sgblack@eecs.umich.edu 4387119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4397119Sgblack@eecs.umich.edu { 4407119Sgblack@eecs.umich.edu if (fault == NoFault) { 44111303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, 44211303Ssteve.reinhardt@amd.com memAccessFlags); 4437119Sgblack@eecs.umich.edu } 4447597Sminkyu.jeong@arm.com } else { 4457597Sminkyu.jeong@arm.com xc->setPredicate(false); 4467119Sgblack@eecs.umich.edu } 4477119Sgblack@eecs.umich.edu 4487119Sgblack@eecs.umich.edu return fault; 4497119Sgblack@eecs.umich.edu } 4507119Sgblack@eecs.umich.edu}}; 4517119Sgblack@eecs.umich.edu 4527639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4537639Sgblack@eecs.umich.edu template <class Element> 4547639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 45510196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 4567639Sgblack@eecs.umich.edu { 4577639Sgblack@eecs.umich.edu Addr EA; 4587639Sgblack@eecs.umich.edu Fault fault = NoFault; 4597639Sgblack@eecs.umich.edu 4608207SAli.Saidi@ARM.com %(op_decl)s; 4618207SAli.Saidi@ARM.com %(mem_decl)s; 4627639Sgblack@eecs.umich.edu %(op_rd)s; 4637639Sgblack@eecs.umich.edu %(ea_code)s; 4647639Sgblack@eecs.umich.edu 4657639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4667639Sgblack@eecs.umich.edu { 4677639Sgblack@eecs.umich.edu if (fault == NoFault) { 46811303Ssteve.reinhardt@amd.com fault = xc->initiateMemRead(EA, %(size)d, memAccessFlags); 4697639Sgblack@eecs.umich.edu } 4708072SGiacomo.Gabrielli@arm.com } else { 4718072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4727639Sgblack@eecs.umich.edu } 4737639Sgblack@eecs.umich.edu 4747639Sgblack@eecs.umich.edu return fault; 4757639Sgblack@eecs.umich.edu } 4767639Sgblack@eecs.umich.edu}}; 4777639Sgblack@eecs.umich.edu 4787119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 4797119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 48010196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 4817119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4827119Sgblack@eecs.umich.edu { 4837119Sgblack@eecs.umich.edu Fault fault = NoFault; 4847119Sgblack@eecs.umich.edu 4857119Sgblack@eecs.umich.edu %(op_decl)s; 4867119Sgblack@eecs.umich.edu %(op_rd)s; 4877119Sgblack@eecs.umich.edu 4887119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4897119Sgblack@eecs.umich.edu { 4907119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4918442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 4927119Sgblack@eecs.umich.edu 4937119Sgblack@eecs.umich.edu if (fault == NoFault) { 4947119Sgblack@eecs.umich.edu %(memacc_code)s; 4957119Sgblack@eecs.umich.edu } 4967119Sgblack@eecs.umich.edu 4977119Sgblack@eecs.umich.edu if (fault == NoFault) { 4987119Sgblack@eecs.umich.edu %(op_wb)s; 4997119Sgblack@eecs.umich.edu } 5007119Sgblack@eecs.umich.edu } 5017119Sgblack@eecs.umich.edu 5027119Sgblack@eecs.umich.edu return fault; 5037119Sgblack@eecs.umich.edu } 5047119Sgblack@eecs.umich.edu}}; 5057119Sgblack@eecs.umich.edu 5067639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5077639Sgblack@eecs.umich.edu template <class Element> 5087639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 50910196SCurtis.Dunham@arm.com PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 5107639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5117639Sgblack@eecs.umich.edu { 5127639Sgblack@eecs.umich.edu Fault fault = NoFault; 5137639Sgblack@eecs.umich.edu 5147639Sgblack@eecs.umich.edu %(mem_decl)s; 5157639Sgblack@eecs.umich.edu %(op_decl)s; 5167639Sgblack@eecs.umich.edu %(op_rd)s; 5177639Sgblack@eecs.umich.edu 5187639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5197639Sgblack@eecs.umich.edu { 5207639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5217639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5227639Sgblack@eecs.umich.edu 5237639Sgblack@eecs.umich.edu if (fault == NoFault) { 5247639Sgblack@eecs.umich.edu %(memacc_code)s; 5257639Sgblack@eecs.umich.edu } 5267639Sgblack@eecs.umich.edu 5277639Sgblack@eecs.umich.edu if (fault == NoFault) { 5287639Sgblack@eecs.umich.edu %(op_wb)s; 5297639Sgblack@eecs.umich.edu } 5307639Sgblack@eecs.umich.edu } 5317639Sgblack@eecs.umich.edu 5327639Sgblack@eecs.umich.edu return fault; 5337639Sgblack@eecs.umich.edu } 5347639Sgblack@eecs.umich.edu}}; 5357639Sgblack@eecs.umich.edu 5367120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5377120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 53810196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 5397120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5407120Sgblack@eecs.umich.edu { 5417712Sgblack@eecs.umich.edu return NoFault; 5427120Sgblack@eecs.umich.edu } 5437120Sgblack@eecs.umich.edu}}; 5447120Sgblack@eecs.umich.edu 5457639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5467639Sgblack@eecs.umich.edu template <class Element> 5477639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 54810196SCurtis.Dunham@arm.com PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 5497639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5507639Sgblack@eecs.umich.edu { 5517712Sgblack@eecs.umich.edu return NoFault; 5527639Sgblack@eecs.umich.edu } 5537639Sgblack@eecs.umich.edu}}; 5547639Sgblack@eecs.umich.edu 5557303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 5567303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 55710196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 5587303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5597303Sgblack@eecs.umich.edu { 5607303Sgblack@eecs.umich.edu Fault fault = NoFault; 5617303Sgblack@eecs.umich.edu 5627303Sgblack@eecs.umich.edu %(op_decl)s; 5637303Sgblack@eecs.umich.edu %(op_rd)s; 5647303Sgblack@eecs.umich.edu 5657303Sgblack@eecs.umich.edu if (%(predicate_test)s) 5667303Sgblack@eecs.umich.edu { 5677303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5687303Sgblack@eecs.umich.edu %(postacc_code)s; 5697303Sgblack@eecs.umich.edu 5707303Sgblack@eecs.umich.edu if (fault == NoFault) { 5717303Sgblack@eecs.umich.edu %(op_wb)s; 5727303Sgblack@eecs.umich.edu } 5737303Sgblack@eecs.umich.edu } 5747303Sgblack@eecs.umich.edu 5757303Sgblack@eecs.umich.edu return fault; 5767303Sgblack@eecs.umich.edu } 5777303Sgblack@eecs.umich.edu}}; 5787303Sgblack@eecs.umich.edu 5797291Sgblack@eecs.umich.edudef template RfeDeclare {{ 5807291Sgblack@eecs.umich.edu /** 5817291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5827291Sgblack@eecs.umich.edu */ 5837291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5847291Sgblack@eecs.umich.edu { 5857291Sgblack@eecs.umich.edu public: 5867291Sgblack@eecs.umich.edu 5877291Sgblack@eecs.umich.edu /// Constructor. 5887291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5897291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5907291Sgblack@eecs.umich.edu 5917291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5927291Sgblack@eecs.umich.edu 5937291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5947291Sgblack@eecs.umich.edu 5957291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5967291Sgblack@eecs.umich.edu }; 5977291Sgblack@eecs.umich.edu}}; 5987291Sgblack@eecs.umich.edu 5997312Sgblack@eecs.umich.edudef template SrsDeclare {{ 6007312Sgblack@eecs.umich.edu /** 6017312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6027312Sgblack@eecs.umich.edu */ 6037312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6047312Sgblack@eecs.umich.edu { 6057312Sgblack@eecs.umich.edu public: 6067312Sgblack@eecs.umich.edu 6077312Sgblack@eecs.umich.edu /// Constructor. 6087312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6097312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6107312Sgblack@eecs.umich.edu 6117312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6127312Sgblack@eecs.umich.edu 6137312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6147312Sgblack@eecs.umich.edu 6157312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6167312Sgblack@eecs.umich.edu }; 6177312Sgblack@eecs.umich.edu}}; 6187312Sgblack@eecs.umich.edu 6197205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6207205Sgblack@eecs.umich.edu /** 6217205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6227205Sgblack@eecs.umich.edu */ 6237205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6247205Sgblack@eecs.umich.edu { 6257205Sgblack@eecs.umich.edu public: 6267205Sgblack@eecs.umich.edu 6277205Sgblack@eecs.umich.edu /// Constructor. 6287205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6297205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6307205Sgblack@eecs.umich.edu 6317205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6327205Sgblack@eecs.umich.edu 6337205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6347205Sgblack@eecs.umich.edu 6357205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6367205Sgblack@eecs.umich.edu }; 6377205Sgblack@eecs.umich.edu}}; 6387205Sgblack@eecs.umich.edu 6397279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6407279Sgblack@eecs.umich.edu /** 6417279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6427279Sgblack@eecs.umich.edu */ 6437279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6447279Sgblack@eecs.umich.edu { 6457279Sgblack@eecs.umich.edu public: 6467279Sgblack@eecs.umich.edu 6477279Sgblack@eecs.umich.edu /// Constructor. 6487279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6497279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6507279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6517279Sgblack@eecs.umich.edu 6527279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6537279Sgblack@eecs.umich.edu 6547279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6557279Sgblack@eecs.umich.edu 6567279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6577279Sgblack@eecs.umich.edu }; 6587279Sgblack@eecs.umich.edu}}; 6597279Sgblack@eecs.umich.edu 6607303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6617303Sgblack@eecs.umich.edu /** 6627303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6637303Sgblack@eecs.umich.edu */ 6647303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6657303Sgblack@eecs.umich.edu { 6667303Sgblack@eecs.umich.edu public: 6677303Sgblack@eecs.umich.edu 6687303Sgblack@eecs.umich.edu /// Constructor. 6697303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6707303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6717303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6727303Sgblack@eecs.umich.edu 6737303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6747303Sgblack@eecs.umich.edu 6757303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6767303Sgblack@eecs.umich.edu 6777303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6787303Sgblack@eecs.umich.edu }; 6797303Sgblack@eecs.umich.edu}}; 6807303Sgblack@eecs.umich.edu 6817119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6827119Sgblack@eecs.umich.edu /** 6837119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6847119Sgblack@eecs.umich.edu */ 6857119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6867119Sgblack@eecs.umich.edu { 6877119Sgblack@eecs.umich.edu public: 6887119Sgblack@eecs.umich.edu 6897119Sgblack@eecs.umich.edu /// Constructor. 6907119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6917119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6927119Sgblack@eecs.umich.edu 6937119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6947119Sgblack@eecs.umich.edu 6957119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6967119Sgblack@eecs.umich.edu 6977119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 69810037SARM gem5 Developers 69910037SARM gem5 Developers virtual void 70010037SARM gem5 Developers annotateFault(ArmFault *fault) { 70110037SARM gem5 Developers %(fa_code)s 70210037SARM gem5 Developers } 7037119Sgblack@eecs.umich.edu }; 7047119Sgblack@eecs.umich.edu}}; 7057119Sgblack@eecs.umich.edu 7067303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7077303Sgblack@eecs.umich.edu /** 7087303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7097303Sgblack@eecs.umich.edu */ 7107303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7117303Sgblack@eecs.umich.edu { 7127303Sgblack@eecs.umich.edu public: 7137303Sgblack@eecs.umich.edu 7147303Sgblack@eecs.umich.edu /// Constructor. 7157303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7167303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7177303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7187303Sgblack@eecs.umich.edu 7197303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7207303Sgblack@eecs.umich.edu 7217303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7227303Sgblack@eecs.umich.edu 7237303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7247303Sgblack@eecs.umich.edu }; 7257303Sgblack@eecs.umich.edu}}; 7267303Sgblack@eecs.umich.edu 7277646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 7287279Sgblack@eecs.umich.edu /** 7297279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7307279Sgblack@eecs.umich.edu */ 7317279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7327279Sgblack@eecs.umich.edu { 7337279Sgblack@eecs.umich.edu public: 7347279Sgblack@eecs.umich.edu 7357279Sgblack@eecs.umich.edu /// Constructor. 7367279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7377279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7387279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7397279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7407279Sgblack@eecs.umich.edu uint32_t _index); 7417279Sgblack@eecs.umich.edu 7427279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7437279Sgblack@eecs.umich.edu 7447279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7457279Sgblack@eecs.umich.edu 7467279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7477279Sgblack@eecs.umich.edu }; 7487279Sgblack@eecs.umich.edu}}; 7497279Sgblack@eecs.umich.edu 7507646Sgene.wu@arm.comdef template StoreRegDeclare {{ 7517119Sgblack@eecs.umich.edu /** 7527119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7537119Sgblack@eecs.umich.edu */ 7547119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7557119Sgblack@eecs.umich.edu { 7567119Sgblack@eecs.umich.edu public: 7577119Sgblack@eecs.umich.edu 7587119Sgblack@eecs.umich.edu /// Constructor. 7597119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7607119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7617119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7627119Sgblack@eecs.umich.edu uint32_t _index); 7637119Sgblack@eecs.umich.edu 7647119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7657119Sgblack@eecs.umich.edu 7667119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7677119Sgblack@eecs.umich.edu 7687119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 76910037SARM gem5 Developers 77010037SARM gem5 Developers virtual void 77110037SARM gem5 Developers annotateFault(ArmFault *fault) { 77210037SARM gem5 Developers %(fa_code)s 77310037SARM gem5 Developers } 7747119Sgblack@eecs.umich.edu }; 7757119Sgblack@eecs.umich.edu}}; 7767119Sgblack@eecs.umich.edu 7777646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 7787646Sgene.wu@arm.com /** 7797646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7807646Sgene.wu@arm.com */ 7817646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7827646Sgene.wu@arm.com { 7837646Sgene.wu@arm.com public: 7847646Sgene.wu@arm.com 7857646Sgene.wu@arm.com /// Constructor. 7867646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 7877646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 7887646Sgene.wu@arm.com uint32_t _base, bool _add, 7897646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 7907646Sgene.wu@arm.com uint32_t _index); 7917646Sgene.wu@arm.com 7927646Sgene.wu@arm.com %(BasicExecDeclare)s 7937646Sgene.wu@arm.com 7947646Sgene.wu@arm.com %(InitiateAccDeclare)s 7957646Sgene.wu@arm.com 7967646Sgene.wu@arm.com %(CompleteAccDeclare)s 7977646Sgene.wu@arm.com }; 7987646Sgene.wu@arm.com}}; 7997646Sgene.wu@arm.com 8007646Sgene.wu@arm.comdef template LoadRegDeclare {{ 8017646Sgene.wu@arm.com /** 8027646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8037646Sgene.wu@arm.com */ 8047646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8057646Sgene.wu@arm.com { 8067646Sgene.wu@arm.com public: 8077646Sgene.wu@arm.com 8087646Sgene.wu@arm.com /// Constructor. 8097646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8107646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 8117646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8127646Sgene.wu@arm.com uint32_t _index); 8137646Sgene.wu@arm.com 8147646Sgene.wu@arm.com %(BasicExecDeclare)s 8157646Sgene.wu@arm.com 8167646Sgene.wu@arm.com %(InitiateAccDeclare)s 8177646Sgene.wu@arm.com 8187646Sgene.wu@arm.com %(CompleteAccDeclare)s 81910037SARM gem5 Developers 82010037SARM gem5 Developers virtual void 82110037SARM gem5 Developers annotateFault(ArmFault *fault) { 82210037SARM gem5 Developers %(fa_code)s 82310037SARM gem5 Developers } 8247646Sgene.wu@arm.com }; 8257646Sgene.wu@arm.com}}; 8267646Sgene.wu@arm.com 8277646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8287646Sgene.wu@arm.com /** 8297646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8307646Sgene.wu@arm.com */ 8317646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8327646Sgene.wu@arm.com { 8337646Sgene.wu@arm.com public: 8347646Sgene.wu@arm.com 8357646Sgene.wu@arm.com /// Constructor. 8367646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8377646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8387646Sgene.wu@arm.com 8397646Sgene.wu@arm.com %(BasicExecDeclare)s 8407646Sgene.wu@arm.com 8417646Sgene.wu@arm.com %(InitiateAccDeclare)s 8427646Sgene.wu@arm.com 8437646Sgene.wu@arm.com %(CompleteAccDeclare)s 84410037SARM gem5 Developers 84510037SARM gem5 Developers virtual void 84610037SARM gem5 Developers annotateFault(ArmFault *fault) { 84710037SARM gem5 Developers %(fa_code)s 84810037SARM gem5 Developers } 8497646Sgene.wu@arm.com }; 8507646Sgene.wu@arm.com}}; 8517646Sgene.wu@arm.com 8527119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 8537119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8547119Sgblack@eecs.umich.edu}}; 8557119Sgblack@eecs.umich.edu 8567119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 8577119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 8587119Sgblack@eecs.umich.edu}}; 8597119Sgblack@eecs.umich.edu 8607291Sgblack@eecs.umich.edudef template RfeConstructor {{ 86110184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8628140SMatt.Horsnell@arm.com uint32_t _base, int _mode, bool _wb) 8638140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8648140SMatt.Horsnell@arm.com (IntRegIndex)_base, (AddrMode)_mode, _wb) 8657291Sgblack@eecs.umich.edu { 8667291Sgblack@eecs.umich.edu %(constructor)s; 8677848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8687848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8697848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8707848SAli.Saidi@ARM.com } 8717848SAli.Saidi@ARM.com } 8727646Sgene.wu@arm.com#if %(use_uops)d 8738140SMatt.Horsnell@arm.com uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8748140SMatt.Horsnell@arm.com int uopIdx = 0; 8758140SMatt.Horsnell@arm.com uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8768140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8778140SMatt.Horsnell@arm.com#if %(use_wb)d 8788140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(wb_decl)s; 8798140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8808140SMatt.Horsnell@arm.com#endif 8818140SMatt.Horsnell@arm.com#if %(use_pc)d 8828140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(pc_decl)s; 8838140SMatt.Horsnell@arm.com#endif 88410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 8858140SMatt.Horsnell@arm.com uops[uopIdx]->setLastMicroop(); 8867646Sgene.wu@arm.com#endif 8877291Sgblack@eecs.umich.edu } 8887291Sgblack@eecs.umich.edu}}; 8897291Sgblack@eecs.umich.edu 8907312Sgblack@eecs.umich.edudef template SrsConstructor {{ 89110184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8927312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8937312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8947312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8957312Sgblack@eecs.umich.edu { 8967312Sgblack@eecs.umich.edu %(constructor)s; 8977848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8987848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8997848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9007848SAli.Saidi@ARM.com } 9017848SAli.Saidi@ARM.com } 9027646Sgene.wu@arm.com#if %(use_uops)d 9037646Sgene.wu@arm.com assert(numMicroops >= 2); 9047646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9057646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9067724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 90710666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9087646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9097646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9107646Sgene.wu@arm.com#endif 9117312Sgblack@eecs.umich.edu } 9127312Sgblack@eecs.umich.edu}}; 9137312Sgblack@eecs.umich.edu 9147205Sgblack@eecs.umich.edudef template SwapConstructor {{ 91510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9167205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9177205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9187205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9197205Sgblack@eecs.umich.edu { 9207205Sgblack@eecs.umich.edu %(constructor)s; 9217848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9227848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9237848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9247848SAli.Saidi@ARM.com } 9257848SAli.Saidi@ARM.com } 9267205Sgblack@eecs.umich.edu } 9277205Sgblack@eecs.umich.edu}}; 9287205Sgblack@eecs.umich.edu 9297279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 93010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9317279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9327279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9337279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9347279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9357279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9367279Sgblack@eecs.umich.edu { 9377279Sgblack@eecs.umich.edu %(constructor)s; 9387848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9397848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9407848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9417848SAli.Saidi@ARM.com } 9427848SAli.Saidi@ARM.com } 9437646Sgene.wu@arm.com#if %(use_uops)d 9447646Sgene.wu@arm.com assert(numMicroops >= 2); 9457646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9467646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 94710666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9487724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9497646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9507646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9517646Sgene.wu@arm.com#endif 9527279Sgblack@eecs.umich.edu } 9537279Sgblack@eecs.umich.edu}}; 9547279Sgblack@eecs.umich.edu 9557303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 95610184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9577303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9587303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9597303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9607303Sgblack@eecs.umich.edu (IntRegIndex)_result, 9617303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9627303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9637303Sgblack@eecs.umich.edu { 9647303Sgblack@eecs.umich.edu %(constructor)s; 9657848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9667848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9677848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9687848SAli.Saidi@ARM.com } 9697848SAli.Saidi@ARM.com } 9707646Sgene.wu@arm.com#if %(use_uops)d 9717646Sgene.wu@arm.com assert(numMicroops >= 2); 9727646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9737646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9747646Sgene.wu@arm.com _base, _add, _imm); 9757724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 97610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9777646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9787646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9797646Sgene.wu@arm.com#endif 9807303Sgblack@eecs.umich.edu } 9817303Sgblack@eecs.umich.edu}}; 9827303Sgblack@eecs.umich.edu 9837119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 98410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9857119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9867119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9877119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9887119Sgblack@eecs.umich.edu { 9897119Sgblack@eecs.umich.edu %(constructor)s; 9907848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9917848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9927848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9937848SAli.Saidi@ARM.com } 9947848SAli.Saidi@ARM.com } 9957646Sgene.wu@arm.com#if %(use_uops)d 9967646Sgene.wu@arm.com assert(numMicroops >= 2); 9977646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9987646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9997724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 100010666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10017646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10027646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10037646Sgene.wu@arm.com#endif 10047119Sgblack@eecs.umich.edu } 10057119Sgblack@eecs.umich.edu}}; 10067119Sgblack@eecs.umich.edu 10077303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 100810184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10097303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10107303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10117303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10127303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10137303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10147303Sgblack@eecs.umich.edu { 10157303Sgblack@eecs.umich.edu %(constructor)s; 10167848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10177848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10187848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10197848SAli.Saidi@ARM.com } 10207848SAli.Saidi@ARM.com } 10217646Sgene.wu@arm.com#if %(use_uops)d 10227646Sgene.wu@arm.com assert(numMicroops >= 2); 10237646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10247646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10257646Sgene.wu@arm.com _base, _add, _imm); 10267724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 102710666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10287646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10297646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10307646Sgene.wu@arm.com#endif 10317303Sgblack@eecs.umich.edu } 10327303Sgblack@eecs.umich.edu}}; 10337303Sgblack@eecs.umich.edu 10347646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 103510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10367279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10377279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10387279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10397279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10407279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10417279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10427279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10437279Sgblack@eecs.umich.edu { 10447279Sgblack@eecs.umich.edu %(constructor)s; 10457848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10467848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10477848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10487848SAli.Saidi@ARM.com } 10497848SAli.Saidi@ARM.com } 10507646Sgene.wu@arm.com#if %(use_uops)d 10517646Sgene.wu@arm.com assert(numMicroops >= 2); 10527646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10537646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10547646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10557724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 105610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10577646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10587646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10597646Sgene.wu@arm.com#endif 10607279Sgblack@eecs.umich.edu } 10617279Sgblack@eecs.umich.edu}}; 10627279Sgblack@eecs.umich.edu 10637646Sgene.wu@arm.comdef template StoreRegConstructor {{ 106410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10657119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10667119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10677119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10687119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10697119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10707119Sgblack@eecs.umich.edu (IntRegIndex)_index) 10717119Sgblack@eecs.umich.edu { 10727119Sgblack@eecs.umich.edu %(constructor)s; 10737848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10747848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10757848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10767848SAli.Saidi@ARM.com } 10777848SAli.Saidi@ARM.com } 10787646Sgene.wu@arm.com#if %(use_uops)d 10797646Sgene.wu@arm.com assert(numMicroops >= 2); 10807646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10817646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10827646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10837724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 108410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10857646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10867646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10877646Sgene.wu@arm.com#endif 10887119Sgblack@eecs.umich.edu } 10897119Sgblack@eecs.umich.edu}}; 10907646Sgene.wu@arm.com 10917646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 109210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10937646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10947646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10957646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10967646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 10977646Sgene.wu@arm.com (IntRegIndex)_base, _add, 10987646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 10997646Sgene.wu@arm.com (IntRegIndex)_index) 11007646Sgene.wu@arm.com { 11017646Sgene.wu@arm.com %(constructor)s; 11027848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11037848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11047848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11057848SAli.Saidi@ARM.com } 11067848SAli.Saidi@ARM.com } 11077646Sgene.wu@arm.com#if %(use_uops)d 11087646Sgene.wu@arm.com assert(numMicroops >= 2); 11097646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11107646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 11117646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11127646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11137724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 111410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11157646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11167646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11177724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11187646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11197646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11207646Sgene.wu@arm.com } else { 11217646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11227646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11237646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11247724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 112510666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11267646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11277646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11287646Sgene.wu@arm.com } 11297646Sgene.wu@arm.com#endif 11307646Sgene.wu@arm.com } 11317646Sgene.wu@arm.com}}; 11327646Sgene.wu@arm.com 11337646Sgene.wu@arm.comdef template LoadRegConstructor {{ 113410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 11357646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11367646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11377646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11387646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11397646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11407646Sgene.wu@arm.com (IntRegIndex)_index) 11417646Sgene.wu@arm.com { 11427646Sgene.wu@arm.com %(constructor)s; 11438607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11447848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11458203SAli.Saidi@ARM.com conditional = true; 11467848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11477848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11487848SAli.Saidi@ARM.com } 11497848SAli.Saidi@ARM.com } 11507646Sgene.wu@arm.com#if %(use_uops)d 11517646Sgene.wu@arm.com assert(numMicroops >= 2); 11527646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11539573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 11547646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11557646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11567646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11577724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 115810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11597646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11607724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11617646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11628203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 11638203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11648203SAli.Saidi@ARM.com if (conditional) 11658203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 11668203SAli.Saidi@ARM.com else 11678203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 11687646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11697646Sgene.wu@arm.com } else if(_dest == _index) { 11707646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11717646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11727724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 117310666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11747646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11757646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11767724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11777646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11787646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11797646Sgene.wu@arm.com } else { 11807646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11817646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11827646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11837724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 118410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11857646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11867646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11877646Sgene.wu@arm.com 11887646Sgene.wu@arm.com } 11899250SAli.Saidi@ARM.com#else 11909573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 11919250SAli.Saidi@ARM.com flags[IsControl] = true; 11929250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 11939250SAli.Saidi@ARM.com if (conditional) 11949250SAli.Saidi@ARM.com flags[IsCondControl] = true; 11959250SAli.Saidi@ARM.com else 11969250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 11979250SAli.Saidi@ARM.com } 11987646Sgene.wu@arm.com#endif 11997646Sgene.wu@arm.com } 12007646Sgene.wu@arm.com}}; 12017646Sgene.wu@arm.com 12027646Sgene.wu@arm.comdef template LoadImmConstructor {{ 120310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 12047646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 12057646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 12067646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 12077646Sgene.wu@arm.com { 12087646Sgene.wu@arm.com %(constructor)s; 12098607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 12107848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 12118203SAli.Saidi@ARM.com conditional = true; 12127848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 12137848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12147848SAli.Saidi@ARM.com } 12157848SAli.Saidi@ARM.com } 12167646Sgene.wu@arm.com#if %(use_uops)d 12177646Sgene.wu@arm.com assert(numMicroops >= 2); 12187646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 12199573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 12207646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 12217646Sgene.wu@arm.com _imm); 12227724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 122310666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12247646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12257724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12267646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12278203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 12288203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 122910199SAndrew.Bardsley@arm.com /* Also set flags on the macroop so that pre-microop decomposition 123010199SAndrew.Bardsley@arm.com branch prediction can work */ 123110199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsControl); 123210199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsIndirectControl); 123310199SAndrew.Bardsley@arm.com if (conditional) { 12348203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 123510199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsCondControl); 123610199SAndrew.Bardsley@arm.com } else { 12378203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 123810199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsUncondControl); 123910199SAndrew.Bardsley@arm.com } 124010199SAndrew.Bardsley@arm.com if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) { 12418203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsReturn); 124210199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsReturn); 124310199SAndrew.Bardsley@arm.com } 12447646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12457646Sgene.wu@arm.com } else { 12467646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12477724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 124810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12497646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12507646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12517646Sgene.wu@arm.com } 12529250SAli.Saidi@ARM.com#else 12539573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 12549250SAli.Saidi@ARM.com flags[IsControl] = true; 12559250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 12569250SAli.Saidi@ARM.com if (conditional) 12579250SAli.Saidi@ARM.com flags[IsCondControl] = true; 12589250SAli.Saidi@ARM.com else 12599250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 12609250SAli.Saidi@ARM.com } 12617646Sgene.wu@arm.com#endif 12627646Sgene.wu@arm.com } 12637646Sgene.wu@arm.com}}; 12647646Sgene.wu@arm.com 1265