macromem.isa revision 8205:7ecbffb674aa
16145Snate@binkert.org// -*- mode:c++ -*- 26145Snate@binkert.org 36145Snate@binkert.org// Copyright (c) 2010 ARM Limited 46145Snate@binkert.org// All rights reserved 56145Snate@binkert.org// 66145Snate@binkert.org// The license below extends only to copyright in the software and shall 76145Snate@binkert.org// not be construed as granting a license to any other intellectual 86145Snate@binkert.org// property including but not limited to intellectual property relating 96145Snate@binkert.org// to a hardware implementation of the functionality of the software 106145Snate@binkert.org// licensed hereunder. You may use the software subject to the license 116145Snate@binkert.org// terms below provided that you ensure that this notice is replicated 126145Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 136145Snate@binkert.org// modified or unmodified, in source code or in binary form. 146145Snate@binkert.org// 156145Snate@binkert.org// Copyright (c) 2007-2008 The Florida State University 166145Snate@binkert.org// All rights reserved. 176145Snate@binkert.org// 186145Snate@binkert.org// Redistribution and use in source and binary forms, with or without 196145Snate@binkert.org// modification, are permitted provided that the following conditions are 206145Snate@binkert.org// met: redistributions of source code must retain the above copyright 216145Snate@binkert.org// notice, this list of conditions and the following disclaimer; 226145Snate@binkert.org// redistributions in binary form must reproduce the above copyright 236145Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 246145Snate@binkert.org// documentation and/or other materials provided with the distribution; 256145Snate@binkert.org// neither the name of the copyright holders nor the names of its 266145Snate@binkert.org// contributors may be used to endorse or promote products derived from 276145Snate@binkert.org// this software without specific prior written permission. 286145Snate@binkert.org// 297832Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307832Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317054Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327054Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336154Snate@binkert.org// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346154Snate@binkert.org// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357054Snate@binkert.org// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367054Snate@binkert.org// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376154Snate@binkert.org// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386145Snate@binkert.org// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397055Snate@binkert.org// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407055Snate@binkert.org// 416145Snate@binkert.org// Authors: Stephen Hines 426145Snate@binkert.org// Gabe Black 436145Snate@binkert.org 446145Snate@binkert.org//////////////////////////////////////////////////////////////////// 456145Snate@binkert.org// 466145Snate@binkert.org// Load/store microops 476145Snate@binkert.org// 486145Snate@binkert.org 496145Snate@binkert.orgdef template MicroMemDeclare {{ 507054Snate@binkert.org class %(class_name)s : public %(base_class)s 517054Snate@binkert.org { 526145Snate@binkert.org public: 537054Snate@binkert.org %(class_name)s(ExtMachInst machInst, 547054Snate@binkert.org RegIndex _ura, RegIndex _urb, bool _up, 556145Snate@binkert.org uint8_t _imm); 566145Snate@binkert.org %(BasicExecDeclare)s 577054Snate@binkert.org %(InitiateAccDeclare)s 587054Snate@binkert.org %(CompleteAccDeclare)s 596145Snate@binkert.org }; 607054Snate@binkert.org}}; 617054Snate@binkert.org 626145Snate@binkert.orgdef template MicroMemConstructor {{ 636145Snate@binkert.org %(class_name)s::%(class_name)s(ExtMachInst machInst, 647054Snate@binkert.org RegIndex _ura, 657054Snate@binkert.org RegIndex _urb, 666145Snate@binkert.org bool _up, 677054Snate@binkert.org uint8_t _imm) 687054Snate@binkert.org : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 696145Snate@binkert.org _ura, _urb, _up, _imm) 707832Snate@binkert.org { 717054Snate@binkert.org %(constructor)s; 727054Snate@binkert.org if (!(condCode == COND_AL || condCode == COND_UC)) { 736145Snate@binkert.org for (int x = 0; x < _numDestRegs; x++) { 747054Snate@binkert.org _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 757054Snate@binkert.org } 766145Snate@binkert.org } 776145Snate@binkert.org } 787054Snate@binkert.org}}; 797054Snate@binkert.org 806145Snate@binkert.org//////////////////////////////////////////////////////////////////// 817054Snate@binkert.org// 827054Snate@binkert.org// Neon load/store microops 837054Snate@binkert.org// 847054Snate@binkert.org 856145Snate@binkert.orgdef template MicroNeonMemDeclare {{ 866145Snate@binkert.org template <class Element> 877054Snate@binkert.org class %(class_name)s : public %(base_class)s 887454Snate@binkert.org { 897454Snate@binkert.org public: 906145Snate@binkert.org %(class_name)s(ExtMachInst machInst, RegIndex _dest, 917054Snate@binkert.org RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 927054Snate@binkert.org : %(base_class)s("%(mnemonic)s", machInst, 937054Snate@binkert.org %(op_class)s, _dest, _ura, _imm) 947054Snate@binkert.org { 956145Snate@binkert.org memAccessFlags |= extraMemFlags; 967454Snate@binkert.org %(constructor)s; 977054Snate@binkert.org if (!(condCode == COND_AL || condCode == COND_UC)) { 987454Snate@binkert.org for (int x = 0; x < _numDestRegs; x++) { 997054Snate@binkert.org _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1007054Snate@binkert.org } 1017054Snate@binkert.org } 1026145Snate@binkert.org } 1036145Snate@binkert.org 1046145Snate@binkert.org %(BasicExecDeclare)s 1057054Snate@binkert.org %(InitiateAccDeclare)s 1067054Snate@binkert.org %(CompleteAccDeclare)s 1076145Snate@binkert.org }; 1087454Snate@binkert.org}}; 1097454Snate@binkert.org 1107454Snate@binkert.org//////////////////////////////////////////////////////////////////// 1116145Snate@binkert.org// 1127054Snate@binkert.org// PC = Integer(ura) 1137054Snate@binkert.org// CPSR = Integer(urb) 1147054Snate@binkert.org// 1157054Snate@binkert.org 1167054Snate@binkert.orgdef template MicroSetPCCPSRDeclare {{ 1177054Snate@binkert.org class %(class_name)s : public %(base_class)s 1186145Snate@binkert.org { 1196145Snate@binkert.org public: 1207054Snate@binkert.org %(class_name)s(ExtMachInst machInst, 1217054Snate@binkert.org IntRegIndex _ura, 1226145Snate@binkert.org IntRegIndex _urb, 1237054Snate@binkert.org IntRegIndex _urc); 1247054Snate@binkert.org %(BasicExecDeclare)s 1257054Snate@binkert.org }; 1266145Snate@binkert.org}}; 1277054Snate@binkert.org 1287054Snate@binkert.orgdef template MicroSetPCCPSRConstructor {{ 1297054Snate@binkert.org %(class_name)s::%(class_name)s(ExtMachInst machInst, 1307054Snate@binkert.org IntRegIndex _ura, 1317054Snate@binkert.org IntRegIndex _urb, 1327054Snate@binkert.org IntRegIndex _urc) 1336145Snate@binkert.org : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1347054Snate@binkert.org _ura, _urb, _urc) 1357054Snate@binkert.org { 1367054Snate@binkert.org %(constructor)s; 1377054Snate@binkert.org if (!(condCode == COND_AL || condCode == COND_UC)) { 1387054Snate@binkert.org for (int x = 0; x < _numDestRegs; x++) { 1397054Snate@binkert.org _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1406145Snate@binkert.org } 1416145Snate@binkert.org } 1427054Snate@binkert.org } 1437054Snate@binkert.org}}; 1447054Snate@binkert.org 1457054Snate@binkert.org//////////////////////////////////////////////////////////////////// 1467054Snate@binkert.org// 1477054Snate@binkert.org// Integer = Integer op Integer microops 1487054Snate@binkert.org// 1497054Snate@binkert.org 1507054Snate@binkert.orgdef template MicroIntDeclare {{ 1517054Snate@binkert.org class %(class_name)s : public %(base_class)s 1527054Snate@binkert.org { 1537054Snate@binkert.org public: 1547054Snate@binkert.org %(class_name)s(ExtMachInst machInst, 1557054Snate@binkert.org RegIndex _ura, RegIndex _urb, RegIndex _urc); 1567054Snate@binkert.org %(BasicExecDeclare)s 1577054Snate@binkert.org }; 1587054Snate@binkert.org}}; 1597054Snate@binkert.org 1607453Snate@binkert.orgdef template MicroIntConstructor {{ 1617054Snate@binkert.org %(class_name)s::%(class_name)s(ExtMachInst machInst, 1627054Snate@binkert.org RegIndex _ura, 1637054Snate@binkert.org RegIndex _urb, 1647780Snilay@cs.wisc.edu RegIndex _urc) 1657780Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1667054Snate@binkert.org _ura, _urb, _urc) 1677780Snilay@cs.wisc.edu { 1687054Snate@binkert.org %(constructor)s; 1697054Snate@binkert.org if (!(condCode == COND_AL || condCode == COND_UC)) { 1707054Snate@binkert.org for (int x = 0; x < _numDestRegs; x++) { 1717054Snate@binkert.org _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1727054Snate@binkert.org } 1737054Snate@binkert.org } 1747054Snate@binkert.org } 1757054Snate@binkert.org}}; 1767780Snilay@cs.wisc.edu 1777054Snate@binkert.orgdef template MicroNeonMemExecDeclare {{ 1787054Snate@binkert.org template 1797054Snate@binkert.org Fault %(class_name)s<%(targs)s>::execute( 1807054Snate@binkert.org %(CPU_exec_context)s *, Trace::InstRecord *) const; 1817054Snate@binkert.org template 1827054Snate@binkert.org Fault %(class_name)s<%(targs)s>::initiateAcc( 1837054Snate@binkert.org %(CPU_exec_context)s *, Trace::InstRecord *) const; 1847054Snate@binkert.org template 1857054Snate@binkert.org Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 1867054Snate@binkert.org %(CPU_exec_context)s *, Trace::InstRecord *) const; 1877054Snate@binkert.org}}; 1887780Snilay@cs.wisc.edu 1897054Snate@binkert.orgdef template MicroNeonExecDeclare {{ 1907054Snate@binkert.org template 1917054Snate@binkert.org Fault %(class_name)s<%(targs)s>::execute( 1927054Snate@binkert.org %(CPU_exec_context)s *, Trace::InstRecord *) const; 1936145Snate@binkert.org}}; 1946145Snate@binkert.org 1957054Snate@binkert.org//////////////////////////////////////////////////////////////////// 1967054Snate@binkert.org// 1977054Snate@binkert.org// Neon (de)interlacing microops 1986145Snate@binkert.org// 1997054Snate@binkert.org 2007054Snate@binkert.orgdef template MicroNeonMixDeclare {{ 2016145Snate@binkert.org template <class Element> 2027054Snate@binkert.org class %(class_name)s : public %(base_class)s 2037054Snate@binkert.org { 2047054Snate@binkert.org public: 2057054Snate@binkert.org %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2067054Snate@binkert.org uint8_t _step) : 2077054Snate@binkert.org %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2087054Snate@binkert.org _dest, _op1, _step) 2097780Snilay@cs.wisc.edu { 2107054Snate@binkert.org %(constructor)s; 2117780Snilay@cs.wisc.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 2127054Snate@binkert.org for (int x = 0; x < _numDestRegs; x++) { 2137054Snate@binkert.org _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2147054Snate@binkert.org } 2157054Snate@binkert.org } 2167054Snate@binkert.org } 2176145Snate@binkert.org 2186145Snate@binkert.org %(BasicExecDeclare)s 2197054Snate@binkert.org }; 2207054Snate@binkert.org}}; 2216145Snate@binkert.org 2227054Snate@binkert.orgdef template MicroNeonMixExecute {{ 2236145Snate@binkert.org template <class Element> 2246145Snate@binkert.org Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 2257054Snate@binkert.org Trace::InstRecord *traceData) const 2267054Snate@binkert.org { 2276145Snate@binkert.org Fault fault = NoFault; 2287054Snate@binkert.org uint64_t resTemp = 0; 2297054Snate@binkert.org resTemp = resTemp; 2306145Snate@binkert.org %(op_decl)s; 2317054Snate@binkert.org %(op_rd)s; 2327054Snate@binkert.org 2337054Snate@binkert.org if (%(predicate_test)s) 2347054Snate@binkert.org { 2356145Snate@binkert.org %(code)s; 2366145Snate@binkert.org if (fault == NoFault) 2376145Snate@binkert.org { 2387054Snate@binkert.org %(op_wb)s; 2397054Snate@binkert.org } 2406145Snate@binkert.org } else { 2416145Snate@binkert.org xc->setPredicate(false); 2426145Snate@binkert.org } 2437054Snate@binkert.org 2447054Snate@binkert.org return fault; 2456145Snate@binkert.org } 2467054Snate@binkert.org}}; 2477054Snate@binkert.org 2486145Snate@binkert.org//////////////////////////////////////////////////////////////////// 2496145Snate@binkert.org// 2507054Snate@binkert.org// Neon (un)packing microops using a particular lane 2517054Snate@binkert.org// 2526145Snate@binkert.org 2538054Sksewell@umich.edudef template MicroNeonMixLaneDeclare {{ 2546145Snate@binkert.org template <class Element> 2556145Snate@binkert.org class %(class_name)s : public %(base_class)s 2567054Snate@binkert.org { 2577054Snate@binkert.org public: 2587054Snate@binkert.org %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2597054Snate@binkert.org uint8_t _step, unsigned _lane) : 2606145Snate@binkert.org %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2617054Snate@binkert.org _dest, _op1, _step, _lane) 2627054Snate@binkert.org { 2637054Snate@binkert.org %(constructor)s; 2646145Snate@binkert.org if (!(condCode == COND_AL || condCode == COND_UC)) { 2657054Snate@binkert.org for (int x = 0; x < _numDestRegs; x++) { 2667054Snate@binkert.org _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2677054Snate@binkert.org } 2687054Snate@binkert.org } 2697054Snate@binkert.org } 2706145Snate@binkert.org 271 %(BasicExecDeclare)s 272 }; 273}}; 274 275//////////////////////////////////////////////////////////////////// 276// 277// Integer = Integer 278// 279 280def template MicroIntMovDeclare {{ 281 class %(class_name)s : public %(base_class)s 282 { 283 public: 284 %(class_name)s(ExtMachInst machInst, 285 RegIndex _ura, RegIndex _urb); 286 %(BasicExecDeclare)s 287 }; 288}}; 289def template MicroIntMovConstructor {{ 290 %(class_name)s::%(class_name)s(ExtMachInst machInst, 291 RegIndex _ura, 292 RegIndex _urb) 293 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 294 _ura, _urb) 295 { 296 %(constructor)s; 297 if (!(condCode == COND_AL || condCode == COND_UC)) { 298 for (int x = 0; x < _numDestRegs; x++) { 299 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 300 } 301 } 302 } 303}}; 304 305//////////////////////////////////////////////////////////////////// 306// 307// Integer = Integer op Immediate microops 308// 309 310def template MicroIntImmDeclare {{ 311 class %(class_name)s : public %(base_class)s 312 { 313 public: 314 %(class_name)s(ExtMachInst machInst, 315 RegIndex _ura, RegIndex _urb, 316 int32_t _imm); 317 %(BasicExecDeclare)s 318 }; 319}}; 320 321def template MicroIntImmConstructor {{ 322 %(class_name)s::%(class_name)s(ExtMachInst machInst, 323 RegIndex _ura, 324 RegIndex _urb, 325 int32_t _imm) 326 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 327 _ura, _urb, _imm) 328 { 329 %(constructor)s; 330 if (!(condCode == COND_AL || condCode == COND_UC)) { 331 for (int x = 0; x < _numDestRegs; x++) { 332 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 333 } 334 } 335 } 336}}; 337 338def template MicroIntRegDeclare {{ 339 class %(class_name)s : public %(base_class)s 340 { 341 public: 342 %(class_name)s(ExtMachInst machInst, 343 RegIndex _ura, RegIndex _urb, RegIndex _urc, 344 int32_t _shiftAmt, ArmShiftType _shiftType); 345 %(BasicExecDeclare)s 346 }; 347}}; 348 349def template MicroIntRegConstructor {{ 350 %(class_name)s::%(class_name)s(ExtMachInst machInst, 351 RegIndex _ura, RegIndex _urb, RegIndex _urc, 352 int32_t _shiftAmt, ArmShiftType _shiftType) 353 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 354 _ura, _urb, _urc, _shiftAmt, _shiftType) 355 { 356 %(constructor)s; 357 if (!(condCode == COND_AL || condCode == COND_UC)) { 358 for (int x = 0; x < _numDestRegs; x++) { 359 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 360 } 361 } 362 } 363}}; 364 365//////////////////////////////////////////////////////////////////// 366// 367// Macro Memory-format instructions 368// 369 370def template MacroMemDeclare {{ 371/** 372 * Static instructions class for a store multiple instruction 373 */ 374class %(class_name)s : public %(base_class)s 375{ 376 public: 377 // Constructor 378 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 379 bool index, bool up, bool user, bool writeback, bool load, 380 uint32_t reglist); 381 %(BasicExecPanic)s 382}; 383}}; 384 385def template MacroMemConstructor {{ 386%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 387 bool index, bool up, bool user, bool writeback, bool load, 388 uint32_t reglist) 389 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 390 index, up, user, writeback, load, reglist) 391{ 392 %(constructor)s; 393 if (!(condCode == COND_AL || condCode == COND_UC)) { 394 for (int x = 0; x < _numDestRegs; x++) { 395 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 396 } 397 } 398} 399 400}}; 401 402def template VMemMultDeclare {{ 403class %(class_name)s : public %(base_class)s 404{ 405 public: 406 // Constructor 407 %(class_name)s(ExtMachInst machInst, unsigned width, 408 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 409 uint32_t size, uint32_t align, RegIndex rm); 410 %(BasicExecPanic)s 411}; 412}}; 413 414def template VMemMultConstructor {{ 415%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 416 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 417 uint32_t size, uint32_t align, RegIndex rm) 418 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 419 rn, vd, regs, inc, size, align, rm) 420{ 421 %(constructor)s; 422 if (!(condCode == COND_AL || condCode == COND_UC)) { 423 for (int x = 0; x < _numDestRegs; x++) { 424 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 425 } 426 } 427} 428}}; 429 430def template VMemSingleDeclare {{ 431class %(class_name)s : public %(base_class)s 432{ 433 public: 434 // Constructor 435 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 436 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 437 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 438 %(BasicExecPanic)s 439}; 440}}; 441 442def template VMemSingleConstructor {{ 443%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 444 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 445 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 446 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 447 rn, vd, regs, inc, size, align, rm, lane) 448{ 449 %(constructor)s; 450 if (!(condCode == COND_AL || condCode == COND_UC)) { 451 for (int x = 0; x < _numDestRegs; x++) { 452 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 453 } 454 } 455} 456}}; 457 458def template MacroVFPMemDeclare {{ 459/** 460 * Static instructions class for a store multiple instruction 461 */ 462class %(class_name)s : public %(base_class)s 463{ 464 public: 465 // Constructor 466 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 467 RegIndex vd, bool single, bool up, bool writeback, 468 bool load, uint32_t offset); 469 %(BasicExecPanic)s 470}; 471}}; 472 473def template MacroVFPMemConstructor {{ 474%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 475 RegIndex vd, bool single, bool up, bool writeback, bool load, 476 uint32_t offset) 477 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 478 vd, single, up, writeback, load, offset) 479{ 480 %(constructor)s; 481 if (!(condCode == COND_AL || condCode == COND_UC)) { 482 for (int x = 0; x < _numDestRegs; x++) { 483 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 484 } 485 } 486} 487 488}}; 489