macromem.isa revision 12236:126ac9da6050
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010-2014 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42// Gabe Black 43 44//////////////////////////////////////////////////////////////////// 45// 46// Load/store microops 47// 48 49def template MicroMemDeclare {{ 50 class %(class_name)s : public %(base_class)s 51 { 52 public: 53 %(class_name)s(ExtMachInst machInst, 54 RegIndex _ura, RegIndex _urb, bool _up, 55 uint8_t _imm); 56 Fault execute(ExecContext *, Trace::InstRecord *) const; 57 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 58 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 59 }; 60}}; 61 62def template MicroMemConstructor {{ 63 %(class_name)s::%(class_name)s(ExtMachInst machInst, 64 RegIndex _ura, 65 RegIndex _urb, 66 bool _up, 67 uint8_t _imm) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; 72 if (!(condCode == COND_AL || condCode == COND_UC)) { 73 for (int x = 0; x < _numDestRegs; x++) { 74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 75 } 76 } 77 } 78}}; 79 80 81def template MicroMemPairDeclare {{ 82 class %(class_name)s : public %(base_class)s 83 { 84 public: 85 %(class_name)s(ExtMachInst machInst, 86 RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, 87 bool _up, uint8_t _imm); 88 Fault execute(ExecContext *, Trace::InstRecord *) const; 89 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 90 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 91 }; 92}}; 93 94def template MicroMemPairConstructor {{ 95 %(class_name)s::%(class_name)s(ExtMachInst machInst, 96 RegIndex _dreg1, 97 RegIndex _dreg2, 98 RegIndex _base, 99 bool _up, 100 uint8_t _imm) 101 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 102 _dreg1, _dreg2, _base, _up, _imm) 103 { 104 %(constructor)s; 105 if (!(condCode == COND_AL || condCode == COND_UC)) { 106 for (int x = 0; x < _numDestRegs; x++) { 107 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 108 } 109 } 110 } 111}}; 112 113//////////////////////////////////////////////////////////////////// 114// 115// Neon load/store microops 116// 117 118def template MicroNeonMemDeclare {{ 119 template <class Element> 120 class %(class_name)s : public %(base_class)s 121 { 122 public: 123 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 124 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 125 : %(base_class)s("%(mnemonic)s", machInst, 126 %(op_class)s, _dest, _ura, _imm) 127 { 128 memAccessFlags |= extraMemFlags; 129 %(constructor)s; 130 if (!(condCode == COND_AL || condCode == COND_UC)) { 131 for (int x = 0; x < _numDestRegs; x++) { 132 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 133 } 134 } 135 } 136 137 Fault execute(ExecContext *, Trace::InstRecord *) const; 138 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 139 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 140 }; 141}}; 142 143//////////////////////////////////////////////////////////////////// 144// 145// PC = Integer(ura) 146// CPSR = Integer(urb) 147// 148 149def template MicroSetPCCPSRDeclare {{ 150 class %(class_name)s : public %(base_class)s 151 { 152 public: 153 %(class_name)s(ExtMachInst machInst, 154 IntRegIndex _ura, 155 IntRegIndex _urb, 156 IntRegIndex _urc); 157 Fault execute(ExecContext *, Trace::InstRecord *) const; 158 }; 159}}; 160 161def template MicroSetPCCPSRConstructor {{ 162 %(class_name)s::%(class_name)s(ExtMachInst machInst, 163 IntRegIndex _ura, 164 IntRegIndex _urb, 165 IntRegIndex _urc) 166 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 167 _ura, _urb, _urc) 168 { 169 %(constructor)s; 170 if (!(condCode == COND_AL || condCode == COND_UC)) { 171 flags[IsCondControl] = true; 172 for (int x = 0; x < _numDestRegs; x++) { 173 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 174 } 175 } else { 176 flags[IsUncondControl] = true; 177 } 178 } 179}}; 180 181//////////////////////////////////////////////////////////////////// 182// 183// Integer = Integer op Integer microops 184// 185 186def template MicroIntDeclare {{ 187 class %(class_name)s : public %(base_class)s 188 { 189 public: 190 %(class_name)s(ExtMachInst machInst, 191 RegIndex _ura, RegIndex _urb, RegIndex _urc); 192 Fault execute(ExecContext *, Trace::InstRecord *) const; 193 }; 194}}; 195 196def template MicroIntConstructor {{ 197 %(class_name)s::%(class_name)s(ExtMachInst machInst, 198 RegIndex _ura, 199 RegIndex _urb, 200 RegIndex _urc) 201 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 202 _ura, _urb, _urc) 203 { 204 %(constructor)s; 205 if (!(condCode == COND_AL || condCode == COND_UC)) { 206 for (int x = 0; x < _numDestRegs; x++) { 207 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 208 } 209 } 210 } 211}}; 212 213def template MicroNeonMemExecDeclare {{ 214 template 215 Fault %(class_name)s<%(targs)s>::execute( 216 ExecContext *, Trace::InstRecord *) const; 217 template 218 Fault %(class_name)s<%(targs)s>::initiateAcc( 219 ExecContext *, Trace::InstRecord *) const; 220 template 221 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 222 ExecContext *, Trace::InstRecord *) const; 223}}; 224 225def template MicroNeonExecDeclare {{ 226 template 227 Fault %(class_name)s<%(targs)s>::execute( 228 ExecContext *, Trace::InstRecord *) const; 229}}; 230 231//////////////////////////////////////////////////////////////////// 232// 233// Neon (de)interlacing microops 234// 235 236def template MicroNeonMixDeclare {{ 237 template <class Element> 238 class %(class_name)s : public %(base_class)s 239 { 240 public: 241 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 242 uint8_t _step) : 243 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 244 _dest, _op1, _step) 245 { 246 %(constructor)s; 247 if (!(condCode == COND_AL || condCode == COND_UC)) { 248 for (int x = 0; x < _numDestRegs; x++) { 249 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 250 } 251 } 252 } 253 254 Fault execute(ExecContext *, Trace::InstRecord *) const; 255 }; 256}}; 257 258def template MicroNeonMixExecute {{ 259 template <class Element> 260 Fault %(class_name)s<Element>::execute(ExecContext *xc, 261 Trace::InstRecord *traceData) const 262 { 263 Fault fault = NoFault; 264 uint64_t resTemp = 0; 265 resTemp = resTemp; 266 %(op_decl)s; 267 %(op_rd)s; 268 269 if (%(predicate_test)s) 270 { 271 %(code)s; 272 if (fault == NoFault) 273 { 274 %(op_wb)s; 275 } 276 } else { 277 xc->setPredicate(false); 278 } 279 280 return fault; 281 } 282}}; 283 284//////////////////////////////////////////////////////////////////// 285// 286// Neon (un)packing microops using a particular lane 287// 288 289def template MicroNeonMixLaneDeclare {{ 290 template <class Element> 291 class %(class_name)s : public %(base_class)s 292 { 293 public: 294 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 295 uint8_t _step, unsigned _lane) : 296 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 297 _dest, _op1, _step, _lane) 298 { 299 %(constructor)s; 300 if (!(condCode == COND_AL || condCode == COND_UC)) { 301 for (int x = 0; x < _numDestRegs; x++) { 302 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 303 } 304 } 305 } 306 307 Fault execute(ExecContext *, Trace::InstRecord *) const; 308 }; 309}}; 310 311//////////////////////////////////////////////////////////////////// 312// 313// Integer = Integer 314// 315 316def template MicroIntMovDeclare {{ 317 class %(class_name)s : public %(base_class)s 318 { 319 public: 320 %(class_name)s(ExtMachInst machInst, 321 RegIndex _ura, RegIndex _urb); 322 Fault execute(ExecContext *, Trace::InstRecord *) const; 323 }; 324}}; 325def template MicroIntMovConstructor {{ 326 %(class_name)s::%(class_name)s(ExtMachInst machInst, 327 RegIndex _ura, 328 RegIndex _urb) 329 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 330 _ura, _urb) 331 { 332 %(constructor)s; 333 if (!(condCode == COND_AL || condCode == COND_UC)) { 334 for (int x = 0; x < _numDestRegs; x++) { 335 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 336 } 337 } 338 } 339}}; 340 341//////////////////////////////////////////////////////////////////// 342// 343// Integer = Integer op Immediate microops 344// 345 346def template MicroIntImmDeclare {{ 347 class %(class_name)s : public %(base_class)s 348 { 349 public: 350 %(class_name)s(ExtMachInst machInst, 351 RegIndex _ura, RegIndex _urb, 352 int32_t _imm); 353 Fault execute(ExecContext *, Trace::InstRecord *) const; 354 }; 355}}; 356 357def template MicroIntImmConstructor {{ 358 %(class_name)s::%(class_name)s(ExtMachInst machInst, 359 RegIndex _ura, 360 RegIndex _urb, 361 int32_t _imm) 362 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 363 _ura, _urb, _imm) 364 { 365 %(constructor)s; 366 if (!(condCode == COND_AL || condCode == COND_UC)) { 367 for (int x = 0; x < _numDestRegs; x++) { 368 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 369 } 370 } 371 } 372}}; 373 374def template MicroIntImmXConstructor {{ 375 %(class_name)s::%(class_name)s(ExtMachInst machInst, 376 RegIndex _ura, 377 RegIndex _urb, 378 int32_t _imm) 379 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 380 _ura, _urb, _imm) 381 { 382 %(constructor)s; 383 } 384}}; 385 386def template MicroIntRegDeclare {{ 387 class %(class_name)s : public %(base_class)s 388 { 389 public: 390 %(class_name)s(ExtMachInst machInst, 391 RegIndex _ura, RegIndex _urb, RegIndex _urc, 392 int32_t _shiftAmt, ArmShiftType _shiftType); 393 Fault execute(ExecContext *, Trace::InstRecord *) const; 394 }; 395}}; 396 397def template MicroIntXERegConstructor {{ 398 %(class_name)s::%(class_name)s(ExtMachInst machInst, 399 RegIndex _ura, RegIndex _urb, RegIndex _urc, 400 ArmExtendType _type, uint32_t _shiftAmt) 401 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 402 _ura, _urb, _urc, _type, _shiftAmt) 403 { 404 %(constructor)s; 405 } 406}}; 407 408def template MicroIntXERegDeclare {{ 409 class %(class_name)s : public %(base_class)s 410 { 411 public: 412 %(class_name)s(ExtMachInst machInst, 413 RegIndex _ura, RegIndex _urb, RegIndex _urc, 414 ArmExtendType _type, uint32_t _shiftAmt); 415 Fault execute(ExecContext *, Trace::InstRecord *) const; 416 }; 417}}; 418 419def template MicroIntRegConstructor {{ 420 %(class_name)s::%(class_name)s(ExtMachInst machInst, 421 RegIndex _ura, RegIndex _urb, RegIndex _urc, 422 int32_t _shiftAmt, ArmShiftType _shiftType) 423 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 424 _ura, _urb, _urc, _shiftAmt, _shiftType) 425 { 426 %(constructor)s; 427 if (!(condCode == COND_AL || condCode == COND_UC)) { 428 for (int x = 0; x < _numDestRegs; x++) { 429 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 430 } 431 } 432 } 433}}; 434 435//////////////////////////////////////////////////////////////////// 436// 437// Macro Memory-format instructions 438// 439 440def template MacroMemDeclare {{ 441/** 442 * Static instructions class for a store multiple instruction 443 */ 444class %(class_name)s : public %(base_class)s 445{ 446 public: 447 // Constructor 448 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 449 bool index, bool up, bool user, bool writeback, bool load, 450 uint32_t reglist); 451}; 452}}; 453 454def template MacroMemConstructor {{ 455%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 456 bool index, bool up, bool user, bool writeback, bool load, 457 uint32_t reglist) 458 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 459 index, up, user, writeback, load, reglist) 460{ 461 %(constructor)s; 462 if (!(condCode == COND_AL || condCode == COND_UC)) { 463 for (int x = 0; x < _numDestRegs; x++) { 464 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 465 } 466 } 467} 468 469}}; 470 471def template BigFpMemImmDeclare {{ 472class %(class_name)s : public %(base_class)s 473{ 474 public: 475 // Constructor 476 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 477 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 478}; 479}}; 480 481def template BigFpMemImmConstructor {{ 482%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 483 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) 484 : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) 485{ 486 %(constructor)s; 487} 488}}; 489 490def template BigFpMemRegDeclare {{ 491class %(class_name)s : public %(base_class)s 492{ 493 public: 494 // Constructor 495 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 496 bool load, IntRegIndex dest, IntRegIndex base, 497 IntRegIndex offset, ArmExtendType type, int64_t imm); 498}; 499}}; 500 501def template BigFpMemRegConstructor {{ 502%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 503 bool load, IntRegIndex dest, IntRegIndex base, 504 IntRegIndex offset, ArmExtendType type, int64_t imm) 505 : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, 506 offset, type, imm) 507{ 508 %(constructor)s; 509} 510}}; 511 512def template BigFpMemLitDeclare {{ 513class %(class_name)s : public %(base_class)s 514{ 515 public: 516 // Constructor 517 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 518 IntRegIndex dest, int64_t imm); 519}; 520}}; 521 522def template BigFpMemLitConstructor {{ 523%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 524 IntRegIndex dest, int64_t imm) 525 : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) 526{ 527 %(constructor)s; 528} 529}}; 530 531def template PairMemDeclare {{ 532class %(class_name)s : public %(base_class)s 533{ 534 public: 535 // Constructor 536 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 537 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 538 bool exclusive, bool acrel, uint32_t imm, 539 AddrMode mode, IntRegIndex rn, IntRegIndex rt, 540 IntRegIndex rt2); 541}; 542}}; 543 544def template PairMemConstructor {{ 545%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 546 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 547 bool exclusive, bool acrel, uint32_t imm, AddrMode mode, 548 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) 549 : %(base_class)s(mnemonic, machInst, %(op_class)s, size, 550 fp, load, noAlloc, signExt, exclusive, acrel, 551 imm, mode, rn, rt, rt2) 552{ 553 %(constructor)s; 554} 555}}; 556 557def template VMemMultDeclare {{ 558class %(class_name)s : public %(base_class)s 559{ 560 public: 561 // Constructor 562 %(class_name)s(ExtMachInst machInst, unsigned width, 563 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 564 uint32_t size, uint32_t align, RegIndex rm); 565}; 566}}; 567 568def template VMemMultConstructor {{ 569%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 570 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 571 uint32_t size, uint32_t align, RegIndex rm) 572 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 573 rn, vd, regs, inc, size, align, rm) 574{ 575 %(constructor)s; 576 if (!(condCode == COND_AL || condCode == COND_UC)) { 577 for (int x = 0; x < _numDestRegs; x++) { 578 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 579 } 580 } 581} 582}}; 583 584def template VMemSingleDeclare {{ 585class %(class_name)s : public %(base_class)s 586{ 587 public: 588 // Constructor 589 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 590 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 591 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 592}; 593}}; 594 595def template VMemSingleConstructor {{ 596%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 597 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 598 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 599 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 600 rn, vd, regs, inc, size, align, rm, lane) 601{ 602 %(constructor)s; 603 if (!(condCode == COND_AL || condCode == COND_UC)) { 604 for (int x = 0; x < _numDestRegs; x++) { 605 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 606 } 607 } 608} 609}}; 610 611def template MacroVFPMemDeclare {{ 612/** 613 * Static instructions class for a store multiple instruction 614 */ 615class %(class_name)s : public %(base_class)s 616{ 617 public: 618 // Constructor 619 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 620 RegIndex vd, bool single, bool up, bool writeback, 621 bool load, uint32_t offset); 622}; 623}}; 624 625def template MacroVFPMemConstructor {{ 626%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 627 RegIndex vd, bool single, bool up, bool writeback, bool load, 628 uint32_t offset) 629 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 630 vd, single, up, writeback, load, offset) 631{ 632 %(constructor)s; 633 if (!(condCode == COND_AL || condCode == COND_UC)) { 634 for (int x = 0; x < _numDestRegs; x++) { 635 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 636 } 637 } 638} 639 640}}; 641