macromem.isa revision 9369
16019SN/A// -*- mode:c++ -*- 26019SN/A 37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 566309SN/A %(BasicExecDeclare)s 576309SN/A %(InitiateAccDeclare)s 586309SN/A %(CompleteAccDeclare)s 596309SN/A }; 606309SN/A}}; 616309SN/A 627134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 637170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 647170Sgblack@eecs.umich.edu RegIndex _ura, 657170Sgblack@eecs.umich.edu RegIndex _urb, 667170Sgblack@eecs.umich.edu bool _up, 677170Sgblack@eecs.umich.edu uint8_t _imm) 687134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 697134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 707134Sgblack@eecs.umich.edu { 717134Sgblack@eecs.umich.edu %(constructor)s; 727848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 737848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 747848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 757848SAli.Saidi@ARM.com } 767848SAli.Saidi@ARM.com } 777134Sgblack@eecs.umich.edu } 786309SN/A}}; 796308SN/A 806308SN/A//////////////////////////////////////////////////////////////////// 816308SN/A// 827639Sgblack@eecs.umich.edu// Neon load/store microops 837639Sgblack@eecs.umich.edu// 847639Sgblack@eecs.umich.edu 857639Sgblack@eecs.umich.edudef template MicroNeonMemDeclare {{ 867639Sgblack@eecs.umich.edu template <class Element> 877639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 887639Sgblack@eecs.umich.edu { 897639Sgblack@eecs.umich.edu public: 907639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 917639Sgblack@eecs.umich.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 927639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, 937639Sgblack@eecs.umich.edu %(op_class)s, _dest, _ura, _imm) 947639Sgblack@eecs.umich.edu { 957639Sgblack@eecs.umich.edu memAccessFlags |= extraMemFlags; 967639Sgblack@eecs.umich.edu %(constructor)s; 977848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 987848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 997848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1007848SAli.Saidi@ARM.com } 1017848SAli.Saidi@ARM.com } 1027639Sgblack@eecs.umich.edu } 1037639Sgblack@eecs.umich.edu 1047639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1057639Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1067639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1077639Sgblack@eecs.umich.edu }; 1087639Sgblack@eecs.umich.edu}}; 1097639Sgblack@eecs.umich.edu 1107639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1117639Sgblack@eecs.umich.edu// 1128140SMatt.Horsnell@arm.com// PC = Integer(ura) 1138140SMatt.Horsnell@arm.com// CPSR = Integer(urb) 1148140SMatt.Horsnell@arm.com// 1158140SMatt.Horsnell@arm.com 1168140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRDeclare {{ 1178140SMatt.Horsnell@arm.com class %(class_name)s : public %(base_class)s 1188140SMatt.Horsnell@arm.com { 1198140SMatt.Horsnell@arm.com public: 1208140SMatt.Horsnell@arm.com %(class_name)s(ExtMachInst machInst, 1218140SMatt.Horsnell@arm.com IntRegIndex _ura, 1228140SMatt.Horsnell@arm.com IntRegIndex _urb, 1238140SMatt.Horsnell@arm.com IntRegIndex _urc); 1248140SMatt.Horsnell@arm.com %(BasicExecDeclare)s 1258140SMatt.Horsnell@arm.com }; 1268140SMatt.Horsnell@arm.com}}; 1278140SMatt.Horsnell@arm.com 1288140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRConstructor {{ 1298140SMatt.Horsnell@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1308140SMatt.Horsnell@arm.com IntRegIndex _ura, 1318140SMatt.Horsnell@arm.com IntRegIndex _urb, 1328140SMatt.Horsnell@arm.com IntRegIndex _urc) 1338140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1348140SMatt.Horsnell@arm.com _ura, _urb, _urc) 1358140SMatt.Horsnell@arm.com { 1368140SMatt.Horsnell@arm.com %(constructor)s; 1378140SMatt.Horsnell@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1389369Snathanael.premillieu@irisa.fr flags[IsCondControl] = true; 1398140SMatt.Horsnell@arm.com for (int x = 0; x < _numDestRegs; x++) { 1408140SMatt.Horsnell@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1418140SMatt.Horsnell@arm.com } 1429369Snathanael.premillieu@irisa.fr } else { 1439369Snathanael.premillieu@irisa.fr flags[IsUncondControl] = true; 1448140SMatt.Horsnell@arm.com } 1458140SMatt.Horsnell@arm.com } 1468140SMatt.Horsnell@arm.com}}; 1478140SMatt.Horsnell@arm.com 1488140SMatt.Horsnell@arm.com//////////////////////////////////////////////////////////////////// 1498140SMatt.Horsnell@arm.com// 1507639Sgblack@eecs.umich.edu// Integer = Integer op Integer microops 1517639Sgblack@eecs.umich.edu// 1527639Sgblack@eecs.umich.edu 1537639Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1547639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1557639Sgblack@eecs.umich.edu { 1567639Sgblack@eecs.umich.edu public: 1577639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1587639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 1597639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1607639Sgblack@eecs.umich.edu }; 1617639Sgblack@eecs.umich.edu}}; 1627639Sgblack@eecs.umich.edu 1637639Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 1647639Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1657639Sgblack@eecs.umich.edu RegIndex _ura, 1667639Sgblack@eecs.umich.edu RegIndex _urb, 1677639Sgblack@eecs.umich.edu RegIndex _urc) 1687639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1697639Sgblack@eecs.umich.edu _ura, _urb, _urc) 1707639Sgblack@eecs.umich.edu { 1717639Sgblack@eecs.umich.edu %(constructor)s; 1727848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1737848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1747848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1757848SAli.Saidi@ARM.com } 1767848SAli.Saidi@ARM.com } 1777639Sgblack@eecs.umich.edu } 1787639Sgblack@eecs.umich.edu}}; 1797639Sgblack@eecs.umich.edu 1807639Sgblack@eecs.umich.edudef template MicroNeonMemExecDeclare {{ 1817639Sgblack@eecs.umich.edu template 1827639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 1837639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1847639Sgblack@eecs.umich.edu template 1857639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 1867639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1877639Sgblack@eecs.umich.edu template 1887639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 1897639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1907639Sgblack@eecs.umich.edu}}; 1917639Sgblack@eecs.umich.edu 1927639Sgblack@eecs.umich.edudef template MicroNeonExecDeclare {{ 1937639Sgblack@eecs.umich.edu template 1947639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 1957639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1967639Sgblack@eecs.umich.edu}}; 1977639Sgblack@eecs.umich.edu 1987639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1997639Sgblack@eecs.umich.edu// 2007639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 2017639Sgblack@eecs.umich.edu// 2027639Sgblack@eecs.umich.edu 2037639Sgblack@eecs.umich.edudef template MicroNeonMixDeclare {{ 2047639Sgblack@eecs.umich.edu template <class Element> 2057639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2067639Sgblack@eecs.umich.edu { 2077639Sgblack@eecs.umich.edu public: 2087639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2097639Sgblack@eecs.umich.edu uint8_t _step) : 2107639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2117639Sgblack@eecs.umich.edu _dest, _op1, _step) 2127639Sgblack@eecs.umich.edu { 2137639Sgblack@eecs.umich.edu %(constructor)s; 2147848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2157848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2167848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2177848SAli.Saidi@ARM.com } 2187848SAli.Saidi@ARM.com } 2197639Sgblack@eecs.umich.edu } 2207639Sgblack@eecs.umich.edu 2217639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2227639Sgblack@eecs.umich.edu }; 2237639Sgblack@eecs.umich.edu}}; 2247639Sgblack@eecs.umich.edu 2257639Sgblack@eecs.umich.edudef template MicroNeonMixExecute {{ 2267639Sgblack@eecs.umich.edu template <class Element> 2277639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 2287639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2297639Sgblack@eecs.umich.edu { 2307639Sgblack@eecs.umich.edu Fault fault = NoFault; 2317639Sgblack@eecs.umich.edu uint64_t resTemp = 0; 2327639Sgblack@eecs.umich.edu resTemp = resTemp; 2337639Sgblack@eecs.umich.edu %(op_decl)s; 2347639Sgblack@eecs.umich.edu %(op_rd)s; 2357639Sgblack@eecs.umich.edu 2367639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2377639Sgblack@eecs.umich.edu { 2387639Sgblack@eecs.umich.edu %(code)s; 2397639Sgblack@eecs.umich.edu if (fault == NoFault) 2407639Sgblack@eecs.umich.edu { 2417639Sgblack@eecs.umich.edu %(op_wb)s; 2427639Sgblack@eecs.umich.edu } 2438072SGiacomo.Gabrielli@arm.com } else { 2448072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2457639Sgblack@eecs.umich.edu } 2467639Sgblack@eecs.umich.edu 2477639Sgblack@eecs.umich.edu return fault; 2487639Sgblack@eecs.umich.edu } 2497639Sgblack@eecs.umich.edu}}; 2507639Sgblack@eecs.umich.edu 2517639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2527639Sgblack@eecs.umich.edu// 2537639Sgblack@eecs.umich.edu// Neon (un)packing microops using a particular lane 2547639Sgblack@eecs.umich.edu// 2557639Sgblack@eecs.umich.edu 2567639Sgblack@eecs.umich.edudef template MicroNeonMixLaneDeclare {{ 2577639Sgblack@eecs.umich.edu template <class Element> 2587639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2597639Sgblack@eecs.umich.edu { 2607639Sgblack@eecs.umich.edu public: 2617639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2627639Sgblack@eecs.umich.edu uint8_t _step, unsigned _lane) : 2637639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2647639Sgblack@eecs.umich.edu _dest, _op1, _step, _lane) 2657639Sgblack@eecs.umich.edu { 2667639Sgblack@eecs.umich.edu %(constructor)s; 2677848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2687848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2697848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2707848SAli.Saidi@ARM.com } 2717848SAli.Saidi@ARM.com } 2727639Sgblack@eecs.umich.edu } 2737639Sgblack@eecs.umich.edu 2747639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2757639Sgblack@eecs.umich.edu }; 2767639Sgblack@eecs.umich.edu}}; 2777639Sgblack@eecs.umich.edu 2787639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2797639Sgblack@eecs.umich.edu// 2807646Sgene.wu@arm.com// Integer = Integer 2817646Sgene.wu@arm.com// 2827646Sgene.wu@arm.com 2837646Sgene.wu@arm.comdef template MicroIntMovDeclare {{ 2847646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 2857646Sgene.wu@arm.com { 2867646Sgene.wu@arm.com public: 2877646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 2887646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb); 2897646Sgene.wu@arm.com %(BasicExecDeclare)s 2907646Sgene.wu@arm.com }; 2917646Sgene.wu@arm.com}}; 2927646Sgene.wu@arm.comdef template MicroIntMovConstructor {{ 2937646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 2947646Sgene.wu@arm.com RegIndex _ura, 2957646Sgene.wu@arm.com RegIndex _urb) 2967646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2977646Sgene.wu@arm.com _ura, _urb) 2987646Sgene.wu@arm.com { 2997646Sgene.wu@arm.com %(constructor)s; 3007848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3017848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3027848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3037848SAli.Saidi@ARM.com } 3047848SAli.Saidi@ARM.com } 3057646Sgene.wu@arm.com } 3067646Sgene.wu@arm.com}}; 3077646Sgene.wu@arm.com 3087646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////// 3097646Sgene.wu@arm.com// 3106308SN/A// Integer = Integer op Immediate microops 3116308SN/A// 3126308SN/A 3137639Sgblack@eecs.umich.edudef template MicroIntImmDeclare {{ 3146308SN/A class %(class_name)s : public %(base_class)s 3156308SN/A { 3166308SN/A public: 3176308SN/A %(class_name)s(ExtMachInst machInst, 3186308SN/A RegIndex _ura, RegIndex _urb, 3197646Sgene.wu@arm.com int32_t _imm); 3206308SN/A %(BasicExecDeclare)s 3216308SN/A }; 3226308SN/A}}; 3236308SN/A 3247639Sgblack@eecs.umich.edudef template MicroIntImmConstructor {{ 3257170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3267170Sgblack@eecs.umich.edu RegIndex _ura, 3277170Sgblack@eecs.umich.edu RegIndex _urb, 3287646Sgene.wu@arm.com int32_t _imm) 3297134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3307134Sgblack@eecs.umich.edu _ura, _urb, _imm) 3317134Sgblack@eecs.umich.edu { 3327134Sgblack@eecs.umich.edu %(constructor)s; 3337848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3347848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3357848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3367848SAli.Saidi@ARM.com } 3377848SAli.Saidi@ARM.com } 3387134Sgblack@eecs.umich.edu } 3396308SN/A}}; 3406019SN/A 3417646Sgene.wu@arm.comdef template MicroIntRegDeclare {{ 3427646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3437646Sgene.wu@arm.com { 3447646Sgene.wu@arm.com public: 3457646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3467646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3477646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType); 3487646Sgene.wu@arm.com %(BasicExecDeclare)s 3497646Sgene.wu@arm.com }; 3507646Sgene.wu@arm.com}}; 3517646Sgene.wu@arm.com 3527646Sgene.wu@arm.comdef template MicroIntRegConstructor {{ 3537646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 3547646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3557646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 3567646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3577646Sgene.wu@arm.com _ura, _urb, _urc, _shiftAmt, _shiftType) 3587646Sgene.wu@arm.com { 3597646Sgene.wu@arm.com %(constructor)s; 3607848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3617848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3627848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3637848SAli.Saidi@ARM.com } 3647848SAli.Saidi@ARM.com } 3657646Sgene.wu@arm.com } 3667646Sgene.wu@arm.com}}; 3677646Sgene.wu@arm.com 3686019SN/A//////////////////////////////////////////////////////////////////// 3696019SN/A// 3706019SN/A// Macro Memory-format instructions 3716019SN/A// 3726019SN/A 3737134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 3746253SN/A/** 3756253SN/A * Static instructions class for a store multiple instruction 3766253SN/A */ 3776253SN/Aclass %(class_name)s : public %(base_class)s 3786253SN/A{ 3796253SN/A public: 3806253SN/A // Constructor 3817134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3827134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 3837134Sgblack@eecs.umich.edu uint32_t reglist); 3847169Sgblack@eecs.umich.edu %(BasicExecPanic)s 3856253SN/A}; 3866019SN/A}}; 3876019SN/A 3887134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 3897170Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3907134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 3917134Sgblack@eecs.umich.edu uint32_t reglist) 3927170Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 3937170Sgblack@eecs.umich.edu index, up, user, writeback, load, reglist) 3946253SN/A{ 3956253SN/A %(constructor)s; 3967848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3977848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3987848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3997848SAli.Saidi@ARM.com } 4007848SAli.Saidi@ARM.com } 4016253SN/A} 4026019SN/A 4036019SN/A}}; 4047176Sgblack@eecs.umich.edu 4057639Sgblack@eecs.umich.edudef template VMemMultDeclare {{ 4067639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 4077639Sgblack@eecs.umich.edu{ 4087639Sgblack@eecs.umich.edu public: 4097639Sgblack@eecs.umich.edu // Constructor 4107639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, unsigned width, 4117639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 4127639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm); 4137639Sgblack@eecs.umich.edu %(BasicExecPanic)s 4147639Sgblack@eecs.umich.edu}; 4157639Sgblack@eecs.umich.edu}}; 4167639Sgblack@eecs.umich.edu 4177639Sgblack@eecs.umich.edudef template VMemMultConstructor {{ 4187639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 4197639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 4207639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm) 4217639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 4227639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm) 4237639Sgblack@eecs.umich.edu{ 4247639Sgblack@eecs.umich.edu %(constructor)s; 4257848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4267848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4277848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4287848SAli.Saidi@ARM.com } 4297848SAli.Saidi@ARM.com } 4307639Sgblack@eecs.umich.edu} 4317639Sgblack@eecs.umich.edu}}; 4327639Sgblack@eecs.umich.edu 4337639Sgblack@eecs.umich.edudef template VMemSingleDeclare {{ 4347639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 4357639Sgblack@eecs.umich.edu{ 4367639Sgblack@eecs.umich.edu public: 4377639Sgblack@eecs.umich.edu // Constructor 4387639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 4397639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 4407639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 4417639Sgblack@eecs.umich.edu %(BasicExecPanic)s 4427639Sgblack@eecs.umich.edu}; 4437639Sgblack@eecs.umich.edu}}; 4447639Sgblack@eecs.umich.edu 4457639Sgblack@eecs.umich.edudef template VMemSingleConstructor {{ 4467639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 4477639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 4487639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 4497639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 4507639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm, lane) 4517639Sgblack@eecs.umich.edu{ 4527639Sgblack@eecs.umich.edu %(constructor)s; 4537848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4547848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4557848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4567848SAli.Saidi@ARM.com } 4577848SAli.Saidi@ARM.com } 4587639Sgblack@eecs.umich.edu} 4597639Sgblack@eecs.umich.edu}}; 4607639Sgblack@eecs.umich.edu 4617176Sgblack@eecs.umich.edudef template MacroVFPMemDeclare {{ 4627176Sgblack@eecs.umich.edu/** 4637176Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 4647176Sgblack@eecs.umich.edu */ 4657176Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 4667176Sgblack@eecs.umich.edu{ 4677176Sgblack@eecs.umich.edu public: 4687176Sgblack@eecs.umich.edu // Constructor 4697176Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4707176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, 4717176Sgblack@eecs.umich.edu bool load, uint32_t offset); 4727176Sgblack@eecs.umich.edu %(BasicExecPanic)s 4737176Sgblack@eecs.umich.edu}; 4747176Sgblack@eecs.umich.edu}}; 4757176Sgblack@eecs.umich.edu 4767176Sgblack@eecs.umich.edudef template MacroVFPMemConstructor {{ 4777176Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4787176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, bool load, 4797176Sgblack@eecs.umich.edu uint32_t offset) 4807176Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 4817176Sgblack@eecs.umich.edu vd, single, up, writeback, load, offset) 4827176Sgblack@eecs.umich.edu{ 4837176Sgblack@eecs.umich.edu %(constructor)s; 4847848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4857848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4867848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4877848SAli.Saidi@ARM.com } 4887848SAli.Saidi@ARM.com } 4897176Sgblack@eecs.umich.edu} 4907176Sgblack@eecs.umich.edu 4917176Sgblack@eecs.umich.edu}}; 492