macromem.isa revision 8072
16019SN/A// -*- mode:c++ -*- 26019SN/A 37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 566309SN/A %(BasicExecDeclare)s 576309SN/A %(InitiateAccDeclare)s 586309SN/A %(CompleteAccDeclare)s 596309SN/A }; 606309SN/A}}; 616309SN/A 627134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 637170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 647170Sgblack@eecs.umich.edu RegIndex _ura, 657170Sgblack@eecs.umich.edu RegIndex _urb, 667170Sgblack@eecs.umich.edu bool _up, 677170Sgblack@eecs.umich.edu uint8_t _imm) 687134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 697134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 707134Sgblack@eecs.umich.edu { 717134Sgblack@eecs.umich.edu %(constructor)s; 727848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 737848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 747848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 757848SAli.Saidi@ARM.com } 767848SAli.Saidi@ARM.com } 777134Sgblack@eecs.umich.edu } 786309SN/A}}; 796308SN/A 806308SN/A//////////////////////////////////////////////////////////////////// 816308SN/A// 827639Sgblack@eecs.umich.edu// Neon load/store microops 837639Sgblack@eecs.umich.edu// 847639Sgblack@eecs.umich.edu 857639Sgblack@eecs.umich.edudef template MicroNeonMemDeclare {{ 867639Sgblack@eecs.umich.edu template <class Element> 877639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 887639Sgblack@eecs.umich.edu { 897639Sgblack@eecs.umich.edu public: 907639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 917639Sgblack@eecs.umich.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 927639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, 937639Sgblack@eecs.umich.edu %(op_class)s, _dest, _ura, _imm) 947639Sgblack@eecs.umich.edu { 957639Sgblack@eecs.umich.edu memAccessFlags |= extraMemFlags; 967639Sgblack@eecs.umich.edu %(constructor)s; 977848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 987848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 997848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1007848SAli.Saidi@ARM.com } 1017848SAli.Saidi@ARM.com } 1027639Sgblack@eecs.umich.edu } 1037639Sgblack@eecs.umich.edu 1047639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1057639Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1067639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1077639Sgblack@eecs.umich.edu }; 1087639Sgblack@eecs.umich.edu}}; 1097639Sgblack@eecs.umich.edu 1107639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1117639Sgblack@eecs.umich.edu// 1127639Sgblack@eecs.umich.edu// Integer = Integer op Integer microops 1137639Sgblack@eecs.umich.edu// 1147639Sgblack@eecs.umich.edu 1157639Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1167639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1177639Sgblack@eecs.umich.edu { 1187639Sgblack@eecs.umich.edu public: 1197639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1207639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 1217639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1227639Sgblack@eecs.umich.edu }; 1237639Sgblack@eecs.umich.edu}}; 1247639Sgblack@eecs.umich.edu 1257639Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 1267639Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1277639Sgblack@eecs.umich.edu RegIndex _ura, 1287639Sgblack@eecs.umich.edu RegIndex _urb, 1297639Sgblack@eecs.umich.edu RegIndex _urc) 1307639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1317639Sgblack@eecs.umich.edu _ura, _urb, _urc) 1327639Sgblack@eecs.umich.edu { 1337639Sgblack@eecs.umich.edu %(constructor)s; 1347848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1357848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1367848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1377848SAli.Saidi@ARM.com } 1387848SAli.Saidi@ARM.com } 1397639Sgblack@eecs.umich.edu } 1407639Sgblack@eecs.umich.edu}}; 1417639Sgblack@eecs.umich.edu 1427639Sgblack@eecs.umich.edudef template MicroNeonMemExecDeclare {{ 1437639Sgblack@eecs.umich.edu template 1447639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 1457639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1467639Sgblack@eecs.umich.edu template 1477639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 1487639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1497639Sgblack@eecs.umich.edu template 1507639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 1517639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1527639Sgblack@eecs.umich.edu}}; 1537639Sgblack@eecs.umich.edu 1547639Sgblack@eecs.umich.edudef template MicroNeonExecDeclare {{ 1557639Sgblack@eecs.umich.edu template 1567639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 1577639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1587639Sgblack@eecs.umich.edu}}; 1597639Sgblack@eecs.umich.edu 1607639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1617639Sgblack@eecs.umich.edu// 1627639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 1637639Sgblack@eecs.umich.edu// 1647639Sgblack@eecs.umich.edu 1657639Sgblack@eecs.umich.edudef template MicroNeonMixDeclare {{ 1667639Sgblack@eecs.umich.edu template <class Element> 1677639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1687639Sgblack@eecs.umich.edu { 1697639Sgblack@eecs.umich.edu public: 1707639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 1717639Sgblack@eecs.umich.edu uint8_t _step) : 1727639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1737639Sgblack@eecs.umich.edu _dest, _op1, _step) 1747639Sgblack@eecs.umich.edu { 1757639Sgblack@eecs.umich.edu %(constructor)s; 1767848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1777848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1787848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1797848SAli.Saidi@ARM.com } 1807848SAli.Saidi@ARM.com } 1817639Sgblack@eecs.umich.edu } 1827639Sgblack@eecs.umich.edu 1837639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1847639Sgblack@eecs.umich.edu }; 1857639Sgblack@eecs.umich.edu}}; 1867639Sgblack@eecs.umich.edu 1877639Sgblack@eecs.umich.edudef template MicroNeonMixExecute {{ 1887639Sgblack@eecs.umich.edu template <class Element> 1897639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 1907639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1917639Sgblack@eecs.umich.edu { 1927639Sgblack@eecs.umich.edu Fault fault = NoFault; 1937639Sgblack@eecs.umich.edu uint64_t resTemp = 0; 1947639Sgblack@eecs.umich.edu resTemp = resTemp; 1957639Sgblack@eecs.umich.edu %(op_decl)s; 1967639Sgblack@eecs.umich.edu %(op_rd)s; 1977639Sgblack@eecs.umich.edu 1987639Sgblack@eecs.umich.edu if (%(predicate_test)s) 1997639Sgblack@eecs.umich.edu { 2007639Sgblack@eecs.umich.edu %(code)s; 2017639Sgblack@eecs.umich.edu if (fault == NoFault) 2027639Sgblack@eecs.umich.edu { 2037639Sgblack@eecs.umich.edu %(op_wb)s; 2047639Sgblack@eecs.umich.edu } 2058072SGiacomo.Gabrielli@arm.com } else { 2068072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2077639Sgblack@eecs.umich.edu } 2087639Sgblack@eecs.umich.edu 2097639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 2107639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 2117639Sgblack@eecs.umich.edu } 2127639Sgblack@eecs.umich.edu 2137639Sgblack@eecs.umich.edu return fault; 2147639Sgblack@eecs.umich.edu } 2157639Sgblack@eecs.umich.edu}}; 2167639Sgblack@eecs.umich.edu 2177639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2187639Sgblack@eecs.umich.edu// 2197639Sgblack@eecs.umich.edu// Neon (un)packing microops using a particular lane 2207639Sgblack@eecs.umich.edu// 2217639Sgblack@eecs.umich.edu 2227639Sgblack@eecs.umich.edudef template MicroNeonMixLaneDeclare {{ 2237639Sgblack@eecs.umich.edu template <class Element> 2247639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2257639Sgblack@eecs.umich.edu { 2267639Sgblack@eecs.umich.edu public: 2277639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2287639Sgblack@eecs.umich.edu uint8_t _step, unsigned _lane) : 2297639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2307639Sgblack@eecs.umich.edu _dest, _op1, _step, _lane) 2317639Sgblack@eecs.umich.edu { 2327639Sgblack@eecs.umich.edu %(constructor)s; 2337848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2347848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2357848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2367848SAli.Saidi@ARM.com } 2377848SAli.Saidi@ARM.com } 2387639Sgblack@eecs.umich.edu } 2397639Sgblack@eecs.umich.edu 2407639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2417639Sgblack@eecs.umich.edu }; 2427639Sgblack@eecs.umich.edu}}; 2437639Sgblack@eecs.umich.edu 2447639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2457639Sgblack@eecs.umich.edu// 2467646Sgene.wu@arm.com// Integer = Integer 2477646Sgene.wu@arm.com// 2487646Sgene.wu@arm.com 2497646Sgene.wu@arm.comdef template MicroIntMovDeclare {{ 2507646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 2517646Sgene.wu@arm.com { 2527646Sgene.wu@arm.com public: 2537646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 2547646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb); 2557646Sgene.wu@arm.com %(BasicExecDeclare)s 2567646Sgene.wu@arm.com }; 2577646Sgene.wu@arm.com}}; 2587646Sgene.wu@arm.comdef template MicroIntMovConstructor {{ 2597646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 2607646Sgene.wu@arm.com RegIndex _ura, 2617646Sgene.wu@arm.com RegIndex _urb) 2627646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2637646Sgene.wu@arm.com _ura, _urb) 2647646Sgene.wu@arm.com { 2657646Sgene.wu@arm.com %(constructor)s; 2667848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2677848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2687848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2697848SAli.Saidi@ARM.com } 2707848SAli.Saidi@ARM.com } 2717646Sgene.wu@arm.com } 2727646Sgene.wu@arm.com}}; 2737646Sgene.wu@arm.com 2747646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////// 2757646Sgene.wu@arm.com// 2766308SN/A// Integer = Integer op Immediate microops 2776308SN/A// 2786308SN/A 2797639Sgblack@eecs.umich.edudef template MicroIntImmDeclare {{ 2806308SN/A class %(class_name)s : public %(base_class)s 2816308SN/A { 2826308SN/A public: 2836308SN/A %(class_name)s(ExtMachInst machInst, 2846308SN/A RegIndex _ura, RegIndex _urb, 2857646Sgene.wu@arm.com int32_t _imm); 2866308SN/A %(BasicExecDeclare)s 2876308SN/A }; 2886308SN/A}}; 2896308SN/A 2907639Sgblack@eecs.umich.edudef template MicroIntImmConstructor {{ 2917170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 2927170Sgblack@eecs.umich.edu RegIndex _ura, 2937170Sgblack@eecs.umich.edu RegIndex _urb, 2947646Sgene.wu@arm.com int32_t _imm) 2957134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2967134Sgblack@eecs.umich.edu _ura, _urb, _imm) 2977134Sgblack@eecs.umich.edu { 2987134Sgblack@eecs.umich.edu %(constructor)s; 2997848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3007848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3017848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3027848SAli.Saidi@ARM.com } 3037848SAli.Saidi@ARM.com } 3047134Sgblack@eecs.umich.edu } 3056308SN/A}}; 3066019SN/A 3077646Sgene.wu@arm.comdef template MicroIntRegDeclare {{ 3087646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3097646Sgene.wu@arm.com { 3107646Sgene.wu@arm.com public: 3117646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3127646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3137646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType); 3147646Sgene.wu@arm.com %(BasicExecDeclare)s 3157646Sgene.wu@arm.com }; 3167646Sgene.wu@arm.com}}; 3177646Sgene.wu@arm.com 3187646Sgene.wu@arm.comdef template MicroIntRegConstructor {{ 3197646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 3207646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3217646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 3227646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3237646Sgene.wu@arm.com _ura, _urb, _urc, _shiftAmt, _shiftType) 3247646Sgene.wu@arm.com { 3257646Sgene.wu@arm.com %(constructor)s; 3267848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3277848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3287848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3297848SAli.Saidi@ARM.com } 3307848SAli.Saidi@ARM.com } 3317646Sgene.wu@arm.com } 3327646Sgene.wu@arm.com}}; 3337646Sgene.wu@arm.com 3346019SN/A//////////////////////////////////////////////////////////////////// 3356019SN/A// 3366019SN/A// Macro Memory-format instructions 3376019SN/A// 3386019SN/A 3397134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 3406253SN/A/** 3416253SN/A * Static instructions class for a store multiple instruction 3426253SN/A */ 3436253SN/Aclass %(class_name)s : public %(base_class)s 3446253SN/A{ 3456253SN/A public: 3466253SN/A // Constructor 3477134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3487134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 3497134Sgblack@eecs.umich.edu uint32_t reglist); 3507169Sgblack@eecs.umich.edu %(BasicExecPanic)s 3516253SN/A}; 3526019SN/A}}; 3536019SN/A 3547134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 3557170Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3567134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 3577134Sgblack@eecs.umich.edu uint32_t reglist) 3587170Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 3597170Sgblack@eecs.umich.edu index, up, user, writeback, load, reglist) 3606253SN/A{ 3616253SN/A %(constructor)s; 3627848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3637848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3647848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3657848SAli.Saidi@ARM.com } 3667848SAli.Saidi@ARM.com } 3676253SN/A} 3686019SN/A 3696019SN/A}}; 3707176Sgblack@eecs.umich.edu 3717639Sgblack@eecs.umich.edudef template VMemMultDeclare {{ 3727639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 3737639Sgblack@eecs.umich.edu{ 3747639Sgblack@eecs.umich.edu public: 3757639Sgblack@eecs.umich.edu // Constructor 3767639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, unsigned width, 3777639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 3787639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm); 3797639Sgblack@eecs.umich.edu %(BasicExecPanic)s 3807639Sgblack@eecs.umich.edu}; 3817639Sgblack@eecs.umich.edu}}; 3827639Sgblack@eecs.umich.edu 3837639Sgblack@eecs.umich.edudef template VMemMultConstructor {{ 3847639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 3857639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 3867639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm) 3877639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 3887639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm) 3897639Sgblack@eecs.umich.edu{ 3907639Sgblack@eecs.umich.edu %(constructor)s; 3917848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3927848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3937848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3947848SAli.Saidi@ARM.com } 3957848SAli.Saidi@ARM.com } 3967639Sgblack@eecs.umich.edu} 3977639Sgblack@eecs.umich.edu}}; 3987639Sgblack@eecs.umich.edu 3997639Sgblack@eecs.umich.edudef template VMemSingleDeclare {{ 4007639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 4017639Sgblack@eecs.umich.edu{ 4027639Sgblack@eecs.umich.edu public: 4037639Sgblack@eecs.umich.edu // Constructor 4047639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 4057639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 4067639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 4077639Sgblack@eecs.umich.edu %(BasicExecPanic)s 4087639Sgblack@eecs.umich.edu}; 4097639Sgblack@eecs.umich.edu}}; 4107639Sgblack@eecs.umich.edu 4117639Sgblack@eecs.umich.edudef template VMemSingleConstructor {{ 4127639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 4137639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 4147639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 4157639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 4167639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm, lane) 4177639Sgblack@eecs.umich.edu{ 4187639Sgblack@eecs.umich.edu %(constructor)s; 4197848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4207848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4217848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4227848SAli.Saidi@ARM.com } 4237848SAli.Saidi@ARM.com } 4247639Sgblack@eecs.umich.edu} 4257639Sgblack@eecs.umich.edu}}; 4267639Sgblack@eecs.umich.edu 4277176Sgblack@eecs.umich.edudef template MacroVFPMemDeclare {{ 4287176Sgblack@eecs.umich.edu/** 4297176Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 4307176Sgblack@eecs.umich.edu */ 4317176Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 4327176Sgblack@eecs.umich.edu{ 4337176Sgblack@eecs.umich.edu public: 4347176Sgblack@eecs.umich.edu // Constructor 4357176Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4367176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, 4377176Sgblack@eecs.umich.edu bool load, uint32_t offset); 4387176Sgblack@eecs.umich.edu %(BasicExecPanic)s 4397176Sgblack@eecs.umich.edu}; 4407176Sgblack@eecs.umich.edu}}; 4417176Sgblack@eecs.umich.edu 4427176Sgblack@eecs.umich.edudef template MacroVFPMemConstructor {{ 4437176Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4447176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, bool load, 4457176Sgblack@eecs.umich.edu uint32_t offset) 4467176Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 4477176Sgblack@eecs.umich.edu vd, single, up, writeback, load, offset) 4487176Sgblack@eecs.umich.edu{ 4497176Sgblack@eecs.umich.edu %(constructor)s; 4507848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4517848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4527848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4537848SAli.Saidi@ARM.com } 4547848SAli.Saidi@ARM.com } 4557176Sgblack@eecs.umich.edu} 4567176Sgblack@eecs.umich.edu 4577176Sgblack@eecs.umich.edu}}; 458