macromem.isa revision 7646
16019SN/A// -*- mode:c++ -*- 26019SN/A 37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 566309SN/A %(BasicExecDeclare)s 576309SN/A %(InitiateAccDeclare)s 586309SN/A %(CompleteAccDeclare)s 596309SN/A }; 606309SN/A}}; 616309SN/A 627134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 637170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 647170Sgblack@eecs.umich.edu RegIndex _ura, 657170Sgblack@eecs.umich.edu RegIndex _urb, 667170Sgblack@eecs.umich.edu bool _up, 677170Sgblack@eecs.umich.edu uint8_t _imm) 687134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 697134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 707134Sgblack@eecs.umich.edu { 717134Sgblack@eecs.umich.edu %(constructor)s; 727134Sgblack@eecs.umich.edu } 736309SN/A}}; 746308SN/A 756308SN/A//////////////////////////////////////////////////////////////////// 766308SN/A// 777639Sgblack@eecs.umich.edu// Neon load/store microops 787639Sgblack@eecs.umich.edu// 797639Sgblack@eecs.umich.edu 807639Sgblack@eecs.umich.edudef template MicroNeonMemDeclare {{ 817639Sgblack@eecs.umich.edu template <class Element> 827639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 837639Sgblack@eecs.umich.edu { 847639Sgblack@eecs.umich.edu public: 857639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 867639Sgblack@eecs.umich.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 877639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, 887639Sgblack@eecs.umich.edu %(op_class)s, _dest, _ura, _imm) 897639Sgblack@eecs.umich.edu { 907639Sgblack@eecs.umich.edu memAccessFlags |= extraMemFlags; 917639Sgblack@eecs.umich.edu %(constructor)s; 927639Sgblack@eecs.umich.edu } 937639Sgblack@eecs.umich.edu 947639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 957639Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 967639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 977639Sgblack@eecs.umich.edu }; 987639Sgblack@eecs.umich.edu}}; 997639Sgblack@eecs.umich.edu 1007639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1017639Sgblack@eecs.umich.edu// 1027639Sgblack@eecs.umich.edu// Integer = Integer op Integer microops 1037639Sgblack@eecs.umich.edu// 1047639Sgblack@eecs.umich.edu 1057639Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1067639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1077639Sgblack@eecs.umich.edu { 1087639Sgblack@eecs.umich.edu public: 1097639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1107639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 1117639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1127639Sgblack@eecs.umich.edu }; 1137639Sgblack@eecs.umich.edu}}; 1147639Sgblack@eecs.umich.edu 1157639Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 1167639Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1177639Sgblack@eecs.umich.edu RegIndex _ura, 1187639Sgblack@eecs.umich.edu RegIndex _urb, 1197639Sgblack@eecs.umich.edu RegIndex _urc) 1207639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1217639Sgblack@eecs.umich.edu _ura, _urb, _urc) 1227639Sgblack@eecs.umich.edu { 1237639Sgblack@eecs.umich.edu %(constructor)s; 1247639Sgblack@eecs.umich.edu } 1257639Sgblack@eecs.umich.edu}}; 1267639Sgblack@eecs.umich.edu 1277639Sgblack@eecs.umich.edudef template MicroNeonMemExecDeclare {{ 1287639Sgblack@eecs.umich.edu template 1297639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 1307639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1317639Sgblack@eecs.umich.edu template 1327639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 1337639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1347639Sgblack@eecs.umich.edu template 1357639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 1367639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1377639Sgblack@eecs.umich.edu}}; 1387639Sgblack@eecs.umich.edu 1397639Sgblack@eecs.umich.edudef template MicroNeonExecDeclare {{ 1407639Sgblack@eecs.umich.edu template 1417639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 1427639Sgblack@eecs.umich.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 1437639Sgblack@eecs.umich.edu}}; 1447639Sgblack@eecs.umich.edu 1457639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1467639Sgblack@eecs.umich.edu// 1477639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 1487639Sgblack@eecs.umich.edu// 1497639Sgblack@eecs.umich.edu 1507639Sgblack@eecs.umich.edudef template MicroNeonMixDeclare {{ 1517639Sgblack@eecs.umich.edu template <class Element> 1527639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1537639Sgblack@eecs.umich.edu { 1547639Sgblack@eecs.umich.edu public: 1557639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 1567639Sgblack@eecs.umich.edu uint8_t _step) : 1577639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1587639Sgblack@eecs.umich.edu _dest, _op1, _step) 1597639Sgblack@eecs.umich.edu { 1607639Sgblack@eecs.umich.edu %(constructor)s; 1617639Sgblack@eecs.umich.edu } 1627639Sgblack@eecs.umich.edu 1637639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1647639Sgblack@eecs.umich.edu }; 1657639Sgblack@eecs.umich.edu}}; 1667639Sgblack@eecs.umich.edu 1677639Sgblack@eecs.umich.edudef template MicroNeonMixExecute {{ 1687639Sgblack@eecs.umich.edu template <class Element> 1697639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 1707639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1717639Sgblack@eecs.umich.edu { 1727639Sgblack@eecs.umich.edu Fault fault = NoFault; 1737639Sgblack@eecs.umich.edu uint64_t resTemp = 0; 1747639Sgblack@eecs.umich.edu resTemp = resTemp; 1757639Sgblack@eecs.umich.edu %(op_decl)s; 1767639Sgblack@eecs.umich.edu %(op_rd)s; 1777639Sgblack@eecs.umich.edu 1787639Sgblack@eecs.umich.edu if (%(predicate_test)s) 1797639Sgblack@eecs.umich.edu { 1807639Sgblack@eecs.umich.edu %(code)s; 1817639Sgblack@eecs.umich.edu if (fault == NoFault) 1827639Sgblack@eecs.umich.edu { 1837639Sgblack@eecs.umich.edu %(op_wb)s; 1847639Sgblack@eecs.umich.edu } 1857639Sgblack@eecs.umich.edu } 1867639Sgblack@eecs.umich.edu 1877639Sgblack@eecs.umich.edu if (fault == NoFault && machInst.itstateMask != 0) { 1887639Sgblack@eecs.umich.edu xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 1897639Sgblack@eecs.umich.edu } 1907639Sgblack@eecs.umich.edu 1917639Sgblack@eecs.umich.edu return fault; 1927639Sgblack@eecs.umich.edu } 1937639Sgblack@eecs.umich.edu}}; 1947639Sgblack@eecs.umich.edu 1957639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1967639Sgblack@eecs.umich.edu// 1977639Sgblack@eecs.umich.edu// Neon (un)packing microops using a particular lane 1987639Sgblack@eecs.umich.edu// 1997639Sgblack@eecs.umich.edu 2007639Sgblack@eecs.umich.edudef template MicroNeonMixLaneDeclare {{ 2017639Sgblack@eecs.umich.edu template <class Element> 2027639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2037639Sgblack@eecs.umich.edu { 2047639Sgblack@eecs.umich.edu public: 2057639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2067639Sgblack@eecs.umich.edu uint8_t _step, unsigned _lane) : 2077639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2087639Sgblack@eecs.umich.edu _dest, _op1, _step, _lane) 2097639Sgblack@eecs.umich.edu { 2107639Sgblack@eecs.umich.edu %(constructor)s; 2117639Sgblack@eecs.umich.edu } 2127639Sgblack@eecs.umich.edu 2137639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2147639Sgblack@eecs.umich.edu }; 2157639Sgblack@eecs.umich.edu}}; 2167639Sgblack@eecs.umich.edu 2177639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2187639Sgblack@eecs.umich.edu// 2197646Sgene.wu@arm.com// Integer = Integer 2207646Sgene.wu@arm.com// 2217646Sgene.wu@arm.com 2227646Sgene.wu@arm.comdef template MicroIntMovDeclare {{ 2237646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 2247646Sgene.wu@arm.com { 2257646Sgene.wu@arm.com public: 2267646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 2277646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb); 2287646Sgene.wu@arm.com %(BasicExecDeclare)s 2297646Sgene.wu@arm.com }; 2307646Sgene.wu@arm.com}}; 2317646Sgene.wu@arm.comdef template MicroIntMovConstructor {{ 2327646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 2337646Sgene.wu@arm.com RegIndex _ura, 2347646Sgene.wu@arm.com RegIndex _urb) 2357646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2367646Sgene.wu@arm.com _ura, _urb) 2377646Sgene.wu@arm.com { 2387646Sgene.wu@arm.com %(constructor)s; 2397646Sgene.wu@arm.com } 2407646Sgene.wu@arm.com}}; 2417646Sgene.wu@arm.com 2427646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////// 2437646Sgene.wu@arm.com// 2446308SN/A// Integer = Integer op Immediate microops 2456308SN/A// 2466308SN/A 2477639Sgblack@eecs.umich.edudef template MicroIntImmDeclare {{ 2486308SN/A class %(class_name)s : public %(base_class)s 2496308SN/A { 2506308SN/A public: 2516308SN/A %(class_name)s(ExtMachInst machInst, 2526308SN/A RegIndex _ura, RegIndex _urb, 2537646Sgene.wu@arm.com int32_t _imm); 2546308SN/A %(BasicExecDeclare)s 2556308SN/A }; 2566308SN/A}}; 2576308SN/A 2587639Sgblack@eecs.umich.edudef template MicroIntImmConstructor {{ 2597170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 2607170Sgblack@eecs.umich.edu RegIndex _ura, 2617170Sgblack@eecs.umich.edu RegIndex _urb, 2627646Sgene.wu@arm.com int32_t _imm) 2637134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2647134Sgblack@eecs.umich.edu _ura, _urb, _imm) 2657134Sgblack@eecs.umich.edu { 2667134Sgblack@eecs.umich.edu %(constructor)s; 2677134Sgblack@eecs.umich.edu } 2686308SN/A}}; 2696019SN/A 2707646Sgene.wu@arm.comdef template MicroIntRegDeclare {{ 2717646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 2727646Sgene.wu@arm.com { 2737646Sgene.wu@arm.com public: 2747646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 2757646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 2767646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType); 2777646Sgene.wu@arm.com %(BasicExecDeclare)s 2787646Sgene.wu@arm.com }; 2797646Sgene.wu@arm.com}}; 2807646Sgene.wu@arm.com 2817646Sgene.wu@arm.comdef template MicroIntRegConstructor {{ 2827646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 2837646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 2847646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 2857646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2867646Sgene.wu@arm.com _ura, _urb, _urc, _shiftAmt, _shiftType) 2877646Sgene.wu@arm.com { 2887646Sgene.wu@arm.com %(constructor)s; 2897646Sgene.wu@arm.com } 2907646Sgene.wu@arm.com}}; 2917646Sgene.wu@arm.com 2926019SN/A//////////////////////////////////////////////////////////////////// 2936019SN/A// 2946019SN/A// Macro Memory-format instructions 2956019SN/A// 2966019SN/A 2977134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 2986253SN/A/** 2996253SN/A * Static instructions class for a store multiple instruction 3006253SN/A */ 3016253SN/Aclass %(class_name)s : public %(base_class)s 3026253SN/A{ 3036253SN/A public: 3046253SN/A // Constructor 3057134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3067134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 3077134Sgblack@eecs.umich.edu uint32_t reglist); 3087169Sgblack@eecs.umich.edu %(BasicExecPanic)s 3096253SN/A}; 3106019SN/A}}; 3116019SN/A 3127134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 3137170Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3147134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 3157134Sgblack@eecs.umich.edu uint32_t reglist) 3167170Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 3177170Sgblack@eecs.umich.edu index, up, user, writeback, load, reglist) 3186253SN/A{ 3196253SN/A %(constructor)s; 3206253SN/A} 3216019SN/A 3226019SN/A}}; 3237176Sgblack@eecs.umich.edu 3247639Sgblack@eecs.umich.edudef template VMemMultDeclare {{ 3257639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 3267639Sgblack@eecs.umich.edu{ 3277639Sgblack@eecs.umich.edu public: 3287639Sgblack@eecs.umich.edu // Constructor 3297639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, unsigned width, 3307639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 3317639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm); 3327639Sgblack@eecs.umich.edu %(BasicExecPanic)s 3337639Sgblack@eecs.umich.edu}; 3347639Sgblack@eecs.umich.edu}}; 3357639Sgblack@eecs.umich.edu 3367639Sgblack@eecs.umich.edudef template VMemMultConstructor {{ 3377639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 3387639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 3397639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm) 3407639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 3417639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm) 3427639Sgblack@eecs.umich.edu{ 3437639Sgblack@eecs.umich.edu %(constructor)s; 3447639Sgblack@eecs.umich.edu} 3457639Sgblack@eecs.umich.edu}}; 3467639Sgblack@eecs.umich.edu 3477639Sgblack@eecs.umich.edudef template VMemSingleDeclare {{ 3487639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 3497639Sgblack@eecs.umich.edu{ 3507639Sgblack@eecs.umich.edu public: 3517639Sgblack@eecs.umich.edu // Constructor 3527639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 3537639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 3547639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 3557639Sgblack@eecs.umich.edu %(BasicExecPanic)s 3567639Sgblack@eecs.umich.edu}; 3577639Sgblack@eecs.umich.edu}}; 3587639Sgblack@eecs.umich.edu 3597639Sgblack@eecs.umich.edudef template VMemSingleConstructor {{ 3607639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 3617639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 3627639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 3637639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 3647639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm, lane) 3657639Sgblack@eecs.umich.edu{ 3667639Sgblack@eecs.umich.edu %(constructor)s; 3677639Sgblack@eecs.umich.edu} 3687639Sgblack@eecs.umich.edu}}; 3697639Sgblack@eecs.umich.edu 3707176Sgblack@eecs.umich.edudef template MacroVFPMemDeclare {{ 3717176Sgblack@eecs.umich.edu/** 3727176Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 3737176Sgblack@eecs.umich.edu */ 3747176Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 3757176Sgblack@eecs.umich.edu{ 3767176Sgblack@eecs.umich.edu public: 3777176Sgblack@eecs.umich.edu // Constructor 3787176Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3797176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, 3807176Sgblack@eecs.umich.edu bool load, uint32_t offset); 3817176Sgblack@eecs.umich.edu %(BasicExecPanic)s 3827176Sgblack@eecs.umich.edu}; 3837176Sgblack@eecs.umich.edu}}; 3847176Sgblack@eecs.umich.edu 3857176Sgblack@eecs.umich.edudef template MacroVFPMemConstructor {{ 3867176Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 3877176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, bool load, 3887176Sgblack@eecs.umich.edu uint32_t offset) 3897176Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 3907176Sgblack@eecs.umich.edu vd, single, up, writeback, load, offset) 3917176Sgblack@eecs.umich.edu{ 3927176Sgblack@eecs.umich.edu %(constructor)s; 3937176Sgblack@eecs.umich.edu} 3947176Sgblack@eecs.umich.edu 3957176Sgblack@eecs.umich.edu}}; 396