macromem.isa revision 12616
16019SN/A// -*- mode:c++ -*- 26019SN/A 310346Smitch.hayenga@arm.com// Copyright (c) 2010-2014 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 5612616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 5712616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 5812616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 5912616Sgabeblack@google.com Trace::InstRecord *) const override; 606309SN/A }; 616309SN/A}}; 626309SN/A 637134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 647170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 657170Sgblack@eecs.umich.edu RegIndex _ura, 667170Sgblack@eecs.umich.edu RegIndex _urb, 677170Sgblack@eecs.umich.edu bool _up, 687170Sgblack@eecs.umich.edu uint8_t _imm) 697134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 707134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 717134Sgblack@eecs.umich.edu { 727134Sgblack@eecs.umich.edu %(constructor)s; 737848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 747848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 757848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 767848SAli.Saidi@ARM.com } 777848SAli.Saidi@ARM.com } 787134Sgblack@eecs.umich.edu } 796309SN/A}}; 806308SN/A 8110346Smitch.hayenga@arm.com 8210346Smitch.hayenga@arm.comdef template MicroMemPairDeclare {{ 8310346Smitch.hayenga@arm.com class %(class_name)s : public %(base_class)s 8410346Smitch.hayenga@arm.com { 8510346Smitch.hayenga@arm.com public: 8610346Smitch.hayenga@arm.com %(class_name)s(ExtMachInst machInst, 8710346Smitch.hayenga@arm.com RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, 8810346Smitch.hayenga@arm.com bool _up, uint8_t _imm); 8912616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 9012616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 9112616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 9212616Sgabeblack@google.com Trace::InstRecord *) const override; 9310346Smitch.hayenga@arm.com }; 9410346Smitch.hayenga@arm.com}}; 9510346Smitch.hayenga@arm.com 9610346Smitch.hayenga@arm.comdef template MicroMemPairConstructor {{ 9710346Smitch.hayenga@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9810346Smitch.hayenga@arm.com RegIndex _dreg1, 9910346Smitch.hayenga@arm.com RegIndex _dreg2, 10010346Smitch.hayenga@arm.com RegIndex _base, 10110346Smitch.hayenga@arm.com bool _up, 10210346Smitch.hayenga@arm.com uint8_t _imm) 10310346Smitch.hayenga@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10410346Smitch.hayenga@arm.com _dreg1, _dreg2, _base, _up, _imm) 10510346Smitch.hayenga@arm.com { 10610346Smitch.hayenga@arm.com %(constructor)s; 10710346Smitch.hayenga@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10810346Smitch.hayenga@arm.com for (int x = 0; x < _numDestRegs; x++) { 10910346Smitch.hayenga@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11010346Smitch.hayenga@arm.com } 11110346Smitch.hayenga@arm.com } 11210346Smitch.hayenga@arm.com } 11310346Smitch.hayenga@arm.com}}; 11410346Smitch.hayenga@arm.com 1156308SN/A//////////////////////////////////////////////////////////////////// 1166308SN/A// 1177639Sgblack@eecs.umich.edu// Neon load/store microops 1187639Sgblack@eecs.umich.edu// 1197639Sgblack@eecs.umich.edu 1207639Sgblack@eecs.umich.edudef template MicroNeonMemDeclare {{ 1217639Sgblack@eecs.umich.edu template <class Element> 1227639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1237639Sgblack@eecs.umich.edu { 1247639Sgblack@eecs.umich.edu public: 1257639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 1267639Sgblack@eecs.umich.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 1277639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, 1287639Sgblack@eecs.umich.edu %(op_class)s, _dest, _ura, _imm) 1297639Sgblack@eecs.umich.edu { 1307639Sgblack@eecs.umich.edu memAccessFlags |= extraMemFlags; 1317639Sgblack@eecs.umich.edu %(constructor)s; 1327848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1337848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1347848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1357848SAli.Saidi@ARM.com } 1367848SAli.Saidi@ARM.com } 1377639Sgblack@eecs.umich.edu } 1387639Sgblack@eecs.umich.edu 13912616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 14012616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 14112616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 14212616Sgabeblack@google.com Trace::InstRecord *) const override; 1437639Sgblack@eecs.umich.edu }; 1447639Sgblack@eecs.umich.edu}}; 1457639Sgblack@eecs.umich.edu 1467639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1477639Sgblack@eecs.umich.edu// 1488140SMatt.Horsnell@arm.com// PC = Integer(ura) 1498140SMatt.Horsnell@arm.com// CPSR = Integer(urb) 1508140SMatt.Horsnell@arm.com// 1518140SMatt.Horsnell@arm.com 1528140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRDeclare {{ 1538140SMatt.Horsnell@arm.com class %(class_name)s : public %(base_class)s 1548140SMatt.Horsnell@arm.com { 1558140SMatt.Horsnell@arm.com public: 1568140SMatt.Horsnell@arm.com %(class_name)s(ExtMachInst machInst, 1578140SMatt.Horsnell@arm.com IntRegIndex _ura, 1588140SMatt.Horsnell@arm.com IntRegIndex _urb, 1598140SMatt.Horsnell@arm.com IntRegIndex _urc); 16012616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 1618140SMatt.Horsnell@arm.com }; 1628140SMatt.Horsnell@arm.com}}; 1638140SMatt.Horsnell@arm.com 1648140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRConstructor {{ 1658140SMatt.Horsnell@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1668140SMatt.Horsnell@arm.com IntRegIndex _ura, 1678140SMatt.Horsnell@arm.com IntRegIndex _urb, 1688140SMatt.Horsnell@arm.com IntRegIndex _urc) 1698140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1708140SMatt.Horsnell@arm.com _ura, _urb, _urc) 1718140SMatt.Horsnell@arm.com { 1728140SMatt.Horsnell@arm.com %(constructor)s; 1738140SMatt.Horsnell@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1749369Snathanael.premillieu@irisa.fr flags[IsCondControl] = true; 1758140SMatt.Horsnell@arm.com for (int x = 0; x < _numDestRegs; x++) { 1768140SMatt.Horsnell@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1778140SMatt.Horsnell@arm.com } 1789369Snathanael.premillieu@irisa.fr } else { 1799369Snathanael.premillieu@irisa.fr flags[IsUncondControl] = true; 1808140SMatt.Horsnell@arm.com } 1818140SMatt.Horsnell@arm.com } 1828140SMatt.Horsnell@arm.com}}; 1838140SMatt.Horsnell@arm.com 1848140SMatt.Horsnell@arm.com//////////////////////////////////////////////////////////////////// 1858140SMatt.Horsnell@arm.com// 1867639Sgblack@eecs.umich.edu// Integer = Integer op Integer microops 1877639Sgblack@eecs.umich.edu// 1887639Sgblack@eecs.umich.edu 1897639Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1907639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1917639Sgblack@eecs.umich.edu { 1927639Sgblack@eecs.umich.edu public: 1937639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1947639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 19512616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 1967639Sgblack@eecs.umich.edu }; 1977639Sgblack@eecs.umich.edu}}; 1987639Sgblack@eecs.umich.edu 1997639Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 2007639Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 2017639Sgblack@eecs.umich.edu RegIndex _ura, 2027639Sgblack@eecs.umich.edu RegIndex _urb, 2037639Sgblack@eecs.umich.edu RegIndex _urc) 2047639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2057639Sgblack@eecs.umich.edu _ura, _urb, _urc) 2067639Sgblack@eecs.umich.edu { 2077639Sgblack@eecs.umich.edu %(constructor)s; 2087848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2097848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2107848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2117848SAli.Saidi@ARM.com } 2127848SAli.Saidi@ARM.com } 2137639Sgblack@eecs.umich.edu } 2147639Sgblack@eecs.umich.edu}}; 2157639Sgblack@eecs.umich.edu 2167639Sgblack@eecs.umich.edudef template MicroNeonMemExecDeclare {{ 2177639Sgblack@eecs.umich.edu template 2187639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 21912234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2207639Sgblack@eecs.umich.edu template 2217639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 22212234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2237639Sgblack@eecs.umich.edu template 2247639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 22512234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2267639Sgblack@eecs.umich.edu}}; 2277639Sgblack@eecs.umich.edu 2287639Sgblack@eecs.umich.edudef template MicroNeonExecDeclare {{ 2297639Sgblack@eecs.umich.edu template 2307639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 23112234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2327639Sgblack@eecs.umich.edu}}; 2337639Sgblack@eecs.umich.edu 2347639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2357639Sgblack@eecs.umich.edu// 2367639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 2377639Sgblack@eecs.umich.edu// 2387639Sgblack@eecs.umich.edu 2397639Sgblack@eecs.umich.edudef template MicroNeonMixDeclare {{ 2407639Sgblack@eecs.umich.edu template <class Element> 2417639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2427639Sgblack@eecs.umich.edu { 2437639Sgblack@eecs.umich.edu public: 2447639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2457639Sgblack@eecs.umich.edu uint8_t _step) : 2467639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2477639Sgblack@eecs.umich.edu _dest, _op1, _step) 2487639Sgblack@eecs.umich.edu { 2497639Sgblack@eecs.umich.edu %(constructor)s; 2507848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2517848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2527848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2537848SAli.Saidi@ARM.com } 2547848SAli.Saidi@ARM.com } 2557639Sgblack@eecs.umich.edu } 2567639Sgblack@eecs.umich.edu 25712616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 2587639Sgblack@eecs.umich.edu }; 2597639Sgblack@eecs.umich.edu}}; 2607639Sgblack@eecs.umich.edu 2617639Sgblack@eecs.umich.edudef template MicroNeonMixExecute {{ 2627639Sgblack@eecs.umich.edu template <class Element> 26312234Sgabeblack@google.com Fault %(class_name)s<Element>::execute(ExecContext *xc, 2647639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2657639Sgblack@eecs.umich.edu { 2667639Sgblack@eecs.umich.edu Fault fault = NoFault; 2677639Sgblack@eecs.umich.edu uint64_t resTemp = 0; 2687639Sgblack@eecs.umich.edu resTemp = resTemp; 2697639Sgblack@eecs.umich.edu %(op_decl)s; 2707639Sgblack@eecs.umich.edu %(op_rd)s; 2717639Sgblack@eecs.umich.edu 2727639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2737639Sgblack@eecs.umich.edu { 2747639Sgblack@eecs.umich.edu %(code)s; 2757639Sgblack@eecs.umich.edu if (fault == NoFault) 2767639Sgblack@eecs.umich.edu { 2777639Sgblack@eecs.umich.edu %(op_wb)s; 2787639Sgblack@eecs.umich.edu } 2798072SGiacomo.Gabrielli@arm.com } else { 2808072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2817639Sgblack@eecs.umich.edu } 2827639Sgblack@eecs.umich.edu 2837639Sgblack@eecs.umich.edu return fault; 2847639Sgblack@eecs.umich.edu } 2857639Sgblack@eecs.umich.edu}}; 2867639Sgblack@eecs.umich.edu 2877639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2887639Sgblack@eecs.umich.edu// 2897639Sgblack@eecs.umich.edu// Neon (un)packing microops using a particular lane 2907639Sgblack@eecs.umich.edu// 2917639Sgblack@eecs.umich.edu 2927639Sgblack@eecs.umich.edudef template MicroNeonMixLaneDeclare {{ 2937639Sgblack@eecs.umich.edu template <class Element> 2947639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2957639Sgblack@eecs.umich.edu { 2967639Sgblack@eecs.umich.edu public: 2977639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2987639Sgblack@eecs.umich.edu uint8_t _step, unsigned _lane) : 2997639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3007639Sgblack@eecs.umich.edu _dest, _op1, _step, _lane) 3017639Sgblack@eecs.umich.edu { 3027639Sgblack@eecs.umich.edu %(constructor)s; 3037848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3047848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3057848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3067848SAli.Saidi@ARM.com } 3077848SAli.Saidi@ARM.com } 3087639Sgblack@eecs.umich.edu } 3097639Sgblack@eecs.umich.edu 31012616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 3117639Sgblack@eecs.umich.edu }; 3127639Sgblack@eecs.umich.edu}}; 3137639Sgblack@eecs.umich.edu 3147639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 3157639Sgblack@eecs.umich.edu// 3167646Sgene.wu@arm.com// Integer = Integer 3177646Sgene.wu@arm.com// 3187646Sgene.wu@arm.com 3197646Sgene.wu@arm.comdef template MicroIntMovDeclare {{ 3207646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3217646Sgene.wu@arm.com { 3227646Sgene.wu@arm.com public: 3237646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3247646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb); 32512616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 3267646Sgene.wu@arm.com }; 3277646Sgene.wu@arm.com}}; 3287646Sgene.wu@arm.comdef template MicroIntMovConstructor {{ 3297646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 3307646Sgene.wu@arm.com RegIndex _ura, 3317646Sgene.wu@arm.com RegIndex _urb) 3327646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3337646Sgene.wu@arm.com _ura, _urb) 3347646Sgene.wu@arm.com { 3357646Sgene.wu@arm.com %(constructor)s; 3367848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3377848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3387848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3397848SAli.Saidi@ARM.com } 3407848SAli.Saidi@ARM.com } 3417646Sgene.wu@arm.com } 3427646Sgene.wu@arm.com}}; 3437646Sgene.wu@arm.com 3447646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////// 3457646Sgene.wu@arm.com// 3466308SN/A// Integer = Integer op Immediate microops 3476308SN/A// 3486308SN/A 3497639Sgblack@eecs.umich.edudef template MicroIntImmDeclare {{ 3506308SN/A class %(class_name)s : public %(base_class)s 3516308SN/A { 3526308SN/A public: 3536308SN/A %(class_name)s(ExtMachInst machInst, 3546308SN/A RegIndex _ura, RegIndex _urb, 3557646Sgene.wu@arm.com int32_t _imm); 35612616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 3576308SN/A }; 3586308SN/A}}; 3596308SN/A 3607639Sgblack@eecs.umich.edudef template MicroIntImmConstructor {{ 3617170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3627170Sgblack@eecs.umich.edu RegIndex _ura, 3637170Sgblack@eecs.umich.edu RegIndex _urb, 3647646Sgene.wu@arm.com int32_t _imm) 3657134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3667134Sgblack@eecs.umich.edu _ura, _urb, _imm) 3677134Sgblack@eecs.umich.edu { 3687134Sgblack@eecs.umich.edu %(constructor)s; 3697848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3707848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3717848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3727848SAli.Saidi@ARM.com } 3737848SAli.Saidi@ARM.com } 3747134Sgblack@eecs.umich.edu } 3756308SN/A}}; 3766019SN/A 37710037SARM gem5 Developersdef template MicroIntImmXConstructor {{ 37810037SARM gem5 Developers %(class_name)s::%(class_name)s(ExtMachInst machInst, 37910037SARM gem5 Developers RegIndex _ura, 38010037SARM gem5 Developers RegIndex _urb, 38110037SARM gem5 Developers int32_t _imm) 38210037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 38310037SARM gem5 Developers _ura, _urb, _imm) 38410037SARM gem5 Developers { 38510037SARM gem5 Developers %(constructor)s; 38610037SARM gem5 Developers } 38710037SARM gem5 Developers}}; 38810037SARM gem5 Developers 3897646Sgene.wu@arm.comdef template MicroIntRegDeclare {{ 3907646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3917646Sgene.wu@arm.com { 3927646Sgene.wu@arm.com public: 3937646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3947646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3957646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType); 39612616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 3977646Sgene.wu@arm.com }; 3987646Sgene.wu@arm.com}}; 3997646Sgene.wu@arm.com 40010037SARM gem5 Developersdef template MicroIntXERegConstructor {{ 40110037SARM gem5 Developers %(class_name)s::%(class_name)s(ExtMachInst machInst, 40210037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 40310037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt) 40410037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 40510037SARM gem5 Developers _ura, _urb, _urc, _type, _shiftAmt) 40610037SARM gem5 Developers { 40710037SARM gem5 Developers %(constructor)s; 40810037SARM gem5 Developers } 40910037SARM gem5 Developers}}; 41010037SARM gem5 Developers 41110037SARM gem5 Developersdef template MicroIntXERegDeclare {{ 41210037SARM gem5 Developers class %(class_name)s : public %(base_class)s 41310037SARM gem5 Developers { 41410037SARM gem5 Developers public: 41510037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 41610037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 41710037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt); 41812616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 41910037SARM gem5 Developers }; 42010037SARM gem5 Developers}}; 42110037SARM gem5 Developers 4227646Sgene.wu@arm.comdef template MicroIntRegConstructor {{ 4237646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 4247646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 4257646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 4267646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4277646Sgene.wu@arm.com _ura, _urb, _urc, _shiftAmt, _shiftType) 4287646Sgene.wu@arm.com { 4297646Sgene.wu@arm.com %(constructor)s; 4307848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4317848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4327848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4337848SAli.Saidi@ARM.com } 4347848SAli.Saidi@ARM.com } 4357646Sgene.wu@arm.com } 4367646Sgene.wu@arm.com}}; 4377646Sgene.wu@arm.com 4386019SN/A//////////////////////////////////////////////////////////////////// 4396019SN/A// 4406019SN/A// Macro Memory-format instructions 4416019SN/A// 4426019SN/A 4437134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 4446253SN/A/** 4456253SN/A * Static instructions class for a store multiple instruction 4466253SN/A */ 4476253SN/Aclass %(class_name)s : public %(base_class)s 4486253SN/A{ 4496253SN/A public: 4506253SN/A // Constructor 4517134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4527134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 4537134Sgblack@eecs.umich.edu uint32_t reglist); 4546253SN/A}; 4556019SN/A}}; 4566019SN/A 4577134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 4587170Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4597134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 4607134Sgblack@eecs.umich.edu uint32_t reglist) 4617170Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 4627170Sgblack@eecs.umich.edu index, up, user, writeback, load, reglist) 4636253SN/A{ 4646253SN/A %(constructor)s; 4657848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4667848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4677848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4687848SAli.Saidi@ARM.com } 4697848SAli.Saidi@ARM.com } 4706253SN/A} 4716019SN/A 4726019SN/A}}; 4737176Sgblack@eecs.umich.edu 47410037SARM gem5 Developersdef template BigFpMemImmDeclare {{ 47510037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 47610037SARM gem5 Developers{ 47710037SARM gem5 Developers public: 47810037SARM gem5 Developers // Constructor 47910037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 48010037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 48110037SARM gem5 Developers}; 48210037SARM gem5 Developers}}; 48310037SARM gem5 Developers 48410037SARM gem5 Developersdef template BigFpMemImmConstructor {{ 48510037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 48610037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) 48710037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) 48810037SARM gem5 Developers{ 48910037SARM gem5 Developers %(constructor)s; 49010037SARM gem5 Developers} 49110037SARM gem5 Developers}}; 49210037SARM gem5 Developers 49310037SARM gem5 Developersdef template BigFpMemRegDeclare {{ 49410037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 49510037SARM gem5 Developers{ 49610037SARM gem5 Developers public: 49710037SARM gem5 Developers // Constructor 49810037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 49910037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 50010037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm); 50110037SARM gem5 Developers}; 50210037SARM gem5 Developers}}; 50310037SARM gem5 Developers 50410037SARM gem5 Developersdef template BigFpMemRegConstructor {{ 50510037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 50610037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 50710037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm) 50810037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, 50910037SARM gem5 Developers offset, type, imm) 51010037SARM gem5 Developers{ 51110037SARM gem5 Developers %(constructor)s; 51210037SARM gem5 Developers} 51310037SARM gem5 Developers}}; 51410037SARM gem5 Developers 51510037SARM gem5 Developersdef template BigFpMemLitDeclare {{ 51610037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 51710037SARM gem5 Developers{ 51810037SARM gem5 Developers public: 51910037SARM gem5 Developers // Constructor 52010037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 52110037SARM gem5 Developers IntRegIndex dest, int64_t imm); 52210037SARM gem5 Developers}; 52310037SARM gem5 Developers}}; 52410037SARM gem5 Developers 52510037SARM gem5 Developersdef template BigFpMemLitConstructor {{ 52610037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 52710037SARM gem5 Developers IntRegIndex dest, int64_t imm) 52810037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) 52910037SARM gem5 Developers{ 53010037SARM gem5 Developers %(constructor)s; 53110037SARM gem5 Developers} 53210037SARM gem5 Developers}}; 53310037SARM gem5 Developers 53410037SARM gem5 Developersdef template PairMemDeclare {{ 53510037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 53610037SARM gem5 Developers{ 53710037SARM gem5 Developers public: 53810037SARM gem5 Developers // Constructor 53910037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 54010037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 54110037SARM gem5 Developers bool exclusive, bool acrel, uint32_t imm, 54210037SARM gem5 Developers AddrMode mode, IntRegIndex rn, IntRegIndex rt, 54310037SARM gem5 Developers IntRegIndex rt2); 54410037SARM gem5 Developers}; 54510037SARM gem5 Developers}}; 54610037SARM gem5 Developers 54710037SARM gem5 Developersdef template PairMemConstructor {{ 54810037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 54910037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 55010037SARM gem5 Developers bool exclusive, bool acrel, uint32_t imm, AddrMode mode, 55110037SARM gem5 Developers IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) 55210037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, size, 55310037SARM gem5 Developers fp, load, noAlloc, signExt, exclusive, acrel, 55410037SARM gem5 Developers imm, mode, rn, rt, rt2) 55510037SARM gem5 Developers{ 55610037SARM gem5 Developers %(constructor)s; 55710037SARM gem5 Developers} 55810037SARM gem5 Developers}}; 55910037SARM gem5 Developers 5607639Sgblack@eecs.umich.edudef template VMemMultDeclare {{ 5617639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5627639Sgblack@eecs.umich.edu{ 5637639Sgblack@eecs.umich.edu public: 5647639Sgblack@eecs.umich.edu // Constructor 5657639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, unsigned width, 5667639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5677639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm); 5687639Sgblack@eecs.umich.edu}; 5697639Sgblack@eecs.umich.edu}}; 5707639Sgblack@eecs.umich.edu 5717639Sgblack@eecs.umich.edudef template VMemMultConstructor {{ 5727639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 5737639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5747639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm) 5757639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 5767639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm) 5777639Sgblack@eecs.umich.edu{ 5787639Sgblack@eecs.umich.edu %(constructor)s; 5797848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5807848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 5817848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 5827848SAli.Saidi@ARM.com } 5837848SAli.Saidi@ARM.com } 5847639Sgblack@eecs.umich.edu} 5857639Sgblack@eecs.umich.edu}}; 5867639Sgblack@eecs.umich.edu 5877639Sgblack@eecs.umich.edudef template VMemSingleDeclare {{ 5887639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5897639Sgblack@eecs.umich.edu{ 5907639Sgblack@eecs.umich.edu public: 5917639Sgblack@eecs.umich.edu // Constructor 5927639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 5937639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5947639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 5957639Sgblack@eecs.umich.edu}; 5967639Sgblack@eecs.umich.edu}}; 5977639Sgblack@eecs.umich.edu 5987639Sgblack@eecs.umich.edudef template VMemSingleConstructor {{ 5997639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 6007639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 6017639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 6027639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 6037639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm, lane) 6047639Sgblack@eecs.umich.edu{ 6057639Sgblack@eecs.umich.edu %(constructor)s; 6067848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 6077848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 6087848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 6097848SAli.Saidi@ARM.com } 6107848SAli.Saidi@ARM.com } 6117639Sgblack@eecs.umich.edu} 6127639Sgblack@eecs.umich.edu}}; 6137639Sgblack@eecs.umich.edu 6147176Sgblack@eecs.umich.edudef template MacroVFPMemDeclare {{ 6157176Sgblack@eecs.umich.edu/** 6167176Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 6177176Sgblack@eecs.umich.edu */ 6187176Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 6197176Sgblack@eecs.umich.edu{ 6207176Sgblack@eecs.umich.edu public: 6217176Sgblack@eecs.umich.edu // Constructor 6227176Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 6237176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, 6247176Sgblack@eecs.umich.edu bool load, uint32_t offset); 6257176Sgblack@eecs.umich.edu}; 6267176Sgblack@eecs.umich.edu}}; 6277176Sgblack@eecs.umich.edu 6287176Sgblack@eecs.umich.edudef template MacroVFPMemConstructor {{ 6297176Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 6307176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, bool load, 6317176Sgblack@eecs.umich.edu uint32_t offset) 6327176Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 6337176Sgblack@eecs.umich.edu vd, single, up, writeback, load, offset) 6347176Sgblack@eecs.umich.edu{ 6357176Sgblack@eecs.umich.edu %(constructor)s; 6367848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 6377848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 6387848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 6397848SAli.Saidi@ARM.com } 6407848SAli.Saidi@ARM.com } 6417176Sgblack@eecs.umich.edu} 6427176Sgblack@eecs.umich.edu 6437176Sgblack@eecs.umich.edu}}; 644