macromem.isa revision 12234
16019SN/A// -*- mode:c++ -*- 26019SN/A 310346Smitch.hayenga@arm.com// Copyright (c) 2010-2014 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 566309SN/A %(BasicExecDeclare)s 576309SN/A %(InitiateAccDeclare)s 586309SN/A %(CompleteAccDeclare)s 596309SN/A }; 606309SN/A}}; 616309SN/A 627134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 637170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 647170Sgblack@eecs.umich.edu RegIndex _ura, 657170Sgblack@eecs.umich.edu RegIndex _urb, 667170Sgblack@eecs.umich.edu bool _up, 677170Sgblack@eecs.umich.edu uint8_t _imm) 687134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 697134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 707134Sgblack@eecs.umich.edu { 717134Sgblack@eecs.umich.edu %(constructor)s; 727848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 737848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 747848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 757848SAli.Saidi@ARM.com } 767848SAli.Saidi@ARM.com } 777134Sgblack@eecs.umich.edu } 786309SN/A}}; 796308SN/A 8010346Smitch.hayenga@arm.com 8110346Smitch.hayenga@arm.comdef template MicroMemPairDeclare {{ 8210346Smitch.hayenga@arm.com class %(class_name)s : public %(base_class)s 8310346Smitch.hayenga@arm.com { 8410346Smitch.hayenga@arm.com public: 8510346Smitch.hayenga@arm.com %(class_name)s(ExtMachInst machInst, 8610346Smitch.hayenga@arm.com RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, 8710346Smitch.hayenga@arm.com bool _up, uint8_t _imm); 8810346Smitch.hayenga@arm.com %(BasicExecDeclare)s 8910346Smitch.hayenga@arm.com %(InitiateAccDeclare)s 9010346Smitch.hayenga@arm.com %(CompleteAccDeclare)s 9110346Smitch.hayenga@arm.com }; 9210346Smitch.hayenga@arm.com}}; 9310346Smitch.hayenga@arm.com 9410346Smitch.hayenga@arm.comdef template MicroMemPairConstructor {{ 9510346Smitch.hayenga@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9610346Smitch.hayenga@arm.com RegIndex _dreg1, 9710346Smitch.hayenga@arm.com RegIndex _dreg2, 9810346Smitch.hayenga@arm.com RegIndex _base, 9910346Smitch.hayenga@arm.com bool _up, 10010346Smitch.hayenga@arm.com uint8_t _imm) 10110346Smitch.hayenga@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10210346Smitch.hayenga@arm.com _dreg1, _dreg2, _base, _up, _imm) 10310346Smitch.hayenga@arm.com { 10410346Smitch.hayenga@arm.com %(constructor)s; 10510346Smitch.hayenga@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10610346Smitch.hayenga@arm.com for (int x = 0; x < _numDestRegs; x++) { 10710346Smitch.hayenga@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10810346Smitch.hayenga@arm.com } 10910346Smitch.hayenga@arm.com } 11010346Smitch.hayenga@arm.com } 11110346Smitch.hayenga@arm.com}}; 11210346Smitch.hayenga@arm.com 1136308SN/A//////////////////////////////////////////////////////////////////// 1146308SN/A// 1157639Sgblack@eecs.umich.edu// Neon load/store microops 1167639Sgblack@eecs.umich.edu// 1177639Sgblack@eecs.umich.edu 1187639Sgblack@eecs.umich.edudef template MicroNeonMemDeclare {{ 1197639Sgblack@eecs.umich.edu template <class Element> 1207639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1217639Sgblack@eecs.umich.edu { 1227639Sgblack@eecs.umich.edu public: 1237639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 1247639Sgblack@eecs.umich.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 1257639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, 1267639Sgblack@eecs.umich.edu %(op_class)s, _dest, _ura, _imm) 1277639Sgblack@eecs.umich.edu { 1287639Sgblack@eecs.umich.edu memAccessFlags |= extraMemFlags; 1297639Sgblack@eecs.umich.edu %(constructor)s; 1307848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1317848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1327848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1337848SAli.Saidi@ARM.com } 1347848SAli.Saidi@ARM.com } 1357639Sgblack@eecs.umich.edu } 1367639Sgblack@eecs.umich.edu 1377639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1387639Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1397639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1407639Sgblack@eecs.umich.edu }; 1417639Sgblack@eecs.umich.edu}}; 1427639Sgblack@eecs.umich.edu 1437639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1447639Sgblack@eecs.umich.edu// 1458140SMatt.Horsnell@arm.com// PC = Integer(ura) 1468140SMatt.Horsnell@arm.com// CPSR = Integer(urb) 1478140SMatt.Horsnell@arm.com// 1488140SMatt.Horsnell@arm.com 1498140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRDeclare {{ 1508140SMatt.Horsnell@arm.com class %(class_name)s : public %(base_class)s 1518140SMatt.Horsnell@arm.com { 1528140SMatt.Horsnell@arm.com public: 1538140SMatt.Horsnell@arm.com %(class_name)s(ExtMachInst machInst, 1548140SMatt.Horsnell@arm.com IntRegIndex _ura, 1558140SMatt.Horsnell@arm.com IntRegIndex _urb, 1568140SMatt.Horsnell@arm.com IntRegIndex _urc); 1578140SMatt.Horsnell@arm.com %(BasicExecDeclare)s 1588140SMatt.Horsnell@arm.com }; 1598140SMatt.Horsnell@arm.com}}; 1608140SMatt.Horsnell@arm.com 1618140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRConstructor {{ 1628140SMatt.Horsnell@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1638140SMatt.Horsnell@arm.com IntRegIndex _ura, 1648140SMatt.Horsnell@arm.com IntRegIndex _urb, 1658140SMatt.Horsnell@arm.com IntRegIndex _urc) 1668140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1678140SMatt.Horsnell@arm.com _ura, _urb, _urc) 1688140SMatt.Horsnell@arm.com { 1698140SMatt.Horsnell@arm.com %(constructor)s; 1708140SMatt.Horsnell@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1719369Snathanael.premillieu@irisa.fr flags[IsCondControl] = true; 1728140SMatt.Horsnell@arm.com for (int x = 0; x < _numDestRegs; x++) { 1738140SMatt.Horsnell@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1748140SMatt.Horsnell@arm.com } 1759369Snathanael.premillieu@irisa.fr } else { 1769369Snathanael.premillieu@irisa.fr flags[IsUncondControl] = true; 1778140SMatt.Horsnell@arm.com } 1788140SMatt.Horsnell@arm.com } 1798140SMatt.Horsnell@arm.com}}; 1808140SMatt.Horsnell@arm.com 1818140SMatt.Horsnell@arm.com//////////////////////////////////////////////////////////////////// 1828140SMatt.Horsnell@arm.com// 1837639Sgblack@eecs.umich.edu// Integer = Integer op Integer microops 1847639Sgblack@eecs.umich.edu// 1857639Sgblack@eecs.umich.edu 1867639Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1877639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1887639Sgblack@eecs.umich.edu { 1897639Sgblack@eecs.umich.edu public: 1907639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1917639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 1927639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1937639Sgblack@eecs.umich.edu }; 1947639Sgblack@eecs.umich.edu}}; 1957639Sgblack@eecs.umich.edu 1967639Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 1977639Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1987639Sgblack@eecs.umich.edu RegIndex _ura, 1997639Sgblack@eecs.umich.edu RegIndex _urb, 2007639Sgblack@eecs.umich.edu RegIndex _urc) 2017639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2027639Sgblack@eecs.umich.edu _ura, _urb, _urc) 2037639Sgblack@eecs.umich.edu { 2047639Sgblack@eecs.umich.edu %(constructor)s; 2057848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2067848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2077848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2087848SAli.Saidi@ARM.com } 2097848SAli.Saidi@ARM.com } 2107639Sgblack@eecs.umich.edu } 2117639Sgblack@eecs.umich.edu}}; 2127639Sgblack@eecs.umich.edu 2137639Sgblack@eecs.umich.edudef template MicroNeonMemExecDeclare {{ 2147639Sgblack@eecs.umich.edu template 2157639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 21612234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2177639Sgblack@eecs.umich.edu template 2187639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 21912234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2207639Sgblack@eecs.umich.edu template 2217639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 22212234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2237639Sgblack@eecs.umich.edu}}; 2247639Sgblack@eecs.umich.edu 2257639Sgblack@eecs.umich.edudef template MicroNeonExecDeclare {{ 2267639Sgblack@eecs.umich.edu template 2277639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 22812234Sgabeblack@google.com ExecContext *, Trace::InstRecord *) const; 2297639Sgblack@eecs.umich.edu}}; 2307639Sgblack@eecs.umich.edu 2317639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2327639Sgblack@eecs.umich.edu// 2337639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 2347639Sgblack@eecs.umich.edu// 2357639Sgblack@eecs.umich.edu 2367639Sgblack@eecs.umich.edudef template MicroNeonMixDeclare {{ 2377639Sgblack@eecs.umich.edu template <class Element> 2387639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2397639Sgblack@eecs.umich.edu { 2407639Sgblack@eecs.umich.edu public: 2417639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2427639Sgblack@eecs.umich.edu uint8_t _step) : 2437639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2447639Sgblack@eecs.umich.edu _dest, _op1, _step) 2457639Sgblack@eecs.umich.edu { 2467639Sgblack@eecs.umich.edu %(constructor)s; 2477848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2487848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2497848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2507848SAli.Saidi@ARM.com } 2517848SAli.Saidi@ARM.com } 2527639Sgblack@eecs.umich.edu } 2537639Sgblack@eecs.umich.edu 2547639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2557639Sgblack@eecs.umich.edu }; 2567639Sgblack@eecs.umich.edu}}; 2577639Sgblack@eecs.umich.edu 2587639Sgblack@eecs.umich.edudef template MicroNeonMixExecute {{ 2597639Sgblack@eecs.umich.edu template <class Element> 26012234Sgabeblack@google.com Fault %(class_name)s<Element>::execute(ExecContext *xc, 2617639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2627639Sgblack@eecs.umich.edu { 2637639Sgblack@eecs.umich.edu Fault fault = NoFault; 2647639Sgblack@eecs.umich.edu uint64_t resTemp = 0; 2657639Sgblack@eecs.umich.edu resTemp = resTemp; 2667639Sgblack@eecs.umich.edu %(op_decl)s; 2677639Sgblack@eecs.umich.edu %(op_rd)s; 2687639Sgblack@eecs.umich.edu 2697639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2707639Sgblack@eecs.umich.edu { 2717639Sgblack@eecs.umich.edu %(code)s; 2727639Sgblack@eecs.umich.edu if (fault == NoFault) 2737639Sgblack@eecs.umich.edu { 2747639Sgblack@eecs.umich.edu %(op_wb)s; 2757639Sgblack@eecs.umich.edu } 2768072SGiacomo.Gabrielli@arm.com } else { 2778072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2787639Sgblack@eecs.umich.edu } 2797639Sgblack@eecs.umich.edu 2807639Sgblack@eecs.umich.edu return fault; 2817639Sgblack@eecs.umich.edu } 2827639Sgblack@eecs.umich.edu}}; 2837639Sgblack@eecs.umich.edu 2847639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2857639Sgblack@eecs.umich.edu// 2867639Sgblack@eecs.umich.edu// Neon (un)packing microops using a particular lane 2877639Sgblack@eecs.umich.edu// 2887639Sgblack@eecs.umich.edu 2897639Sgblack@eecs.umich.edudef template MicroNeonMixLaneDeclare {{ 2907639Sgblack@eecs.umich.edu template <class Element> 2917639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2927639Sgblack@eecs.umich.edu { 2937639Sgblack@eecs.umich.edu public: 2947639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2957639Sgblack@eecs.umich.edu uint8_t _step, unsigned _lane) : 2967639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2977639Sgblack@eecs.umich.edu _dest, _op1, _step, _lane) 2987639Sgblack@eecs.umich.edu { 2997639Sgblack@eecs.umich.edu %(constructor)s; 3007848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3017848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3027848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3037848SAli.Saidi@ARM.com } 3047848SAli.Saidi@ARM.com } 3057639Sgblack@eecs.umich.edu } 3067639Sgblack@eecs.umich.edu 3077639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 3087639Sgblack@eecs.umich.edu }; 3097639Sgblack@eecs.umich.edu}}; 3107639Sgblack@eecs.umich.edu 3117639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 3127639Sgblack@eecs.umich.edu// 3137646Sgene.wu@arm.com// Integer = Integer 3147646Sgene.wu@arm.com// 3157646Sgene.wu@arm.com 3167646Sgene.wu@arm.comdef template MicroIntMovDeclare {{ 3177646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3187646Sgene.wu@arm.com { 3197646Sgene.wu@arm.com public: 3207646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3217646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb); 3227646Sgene.wu@arm.com %(BasicExecDeclare)s 3237646Sgene.wu@arm.com }; 3247646Sgene.wu@arm.com}}; 3257646Sgene.wu@arm.comdef template MicroIntMovConstructor {{ 3267646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 3277646Sgene.wu@arm.com RegIndex _ura, 3287646Sgene.wu@arm.com RegIndex _urb) 3297646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3307646Sgene.wu@arm.com _ura, _urb) 3317646Sgene.wu@arm.com { 3327646Sgene.wu@arm.com %(constructor)s; 3337848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3347848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3357848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3367848SAli.Saidi@ARM.com } 3377848SAli.Saidi@ARM.com } 3387646Sgene.wu@arm.com } 3397646Sgene.wu@arm.com}}; 3407646Sgene.wu@arm.com 3417646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////// 3427646Sgene.wu@arm.com// 3436308SN/A// Integer = Integer op Immediate microops 3446308SN/A// 3456308SN/A 3467639Sgblack@eecs.umich.edudef template MicroIntImmDeclare {{ 3476308SN/A class %(class_name)s : public %(base_class)s 3486308SN/A { 3496308SN/A public: 3506308SN/A %(class_name)s(ExtMachInst machInst, 3516308SN/A RegIndex _ura, RegIndex _urb, 3527646Sgene.wu@arm.com int32_t _imm); 3536308SN/A %(BasicExecDeclare)s 3546308SN/A }; 3556308SN/A}}; 3566308SN/A 3577639Sgblack@eecs.umich.edudef template MicroIntImmConstructor {{ 3587170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3597170Sgblack@eecs.umich.edu RegIndex _ura, 3607170Sgblack@eecs.umich.edu RegIndex _urb, 3617646Sgene.wu@arm.com int32_t _imm) 3627134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3637134Sgblack@eecs.umich.edu _ura, _urb, _imm) 3647134Sgblack@eecs.umich.edu { 3657134Sgblack@eecs.umich.edu %(constructor)s; 3667848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3677848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3687848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3697848SAli.Saidi@ARM.com } 3707848SAli.Saidi@ARM.com } 3717134Sgblack@eecs.umich.edu } 3726308SN/A}}; 3736019SN/A 37410037SARM gem5 Developersdef template MicroIntImmXConstructor {{ 37510037SARM gem5 Developers %(class_name)s::%(class_name)s(ExtMachInst machInst, 37610037SARM gem5 Developers RegIndex _ura, 37710037SARM gem5 Developers RegIndex _urb, 37810037SARM gem5 Developers int32_t _imm) 37910037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 38010037SARM gem5 Developers _ura, _urb, _imm) 38110037SARM gem5 Developers { 38210037SARM gem5 Developers %(constructor)s; 38310037SARM gem5 Developers } 38410037SARM gem5 Developers}}; 38510037SARM gem5 Developers 3867646Sgene.wu@arm.comdef template MicroIntRegDeclare {{ 3877646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3887646Sgene.wu@arm.com { 3897646Sgene.wu@arm.com public: 3907646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3917646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3927646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType); 3937646Sgene.wu@arm.com %(BasicExecDeclare)s 3947646Sgene.wu@arm.com }; 3957646Sgene.wu@arm.com}}; 3967646Sgene.wu@arm.com 39710037SARM gem5 Developersdef template MicroIntXERegConstructor {{ 39810037SARM gem5 Developers %(class_name)s::%(class_name)s(ExtMachInst machInst, 39910037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 40010037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt) 40110037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 40210037SARM gem5 Developers _ura, _urb, _urc, _type, _shiftAmt) 40310037SARM gem5 Developers { 40410037SARM gem5 Developers %(constructor)s; 40510037SARM gem5 Developers } 40610037SARM gem5 Developers}}; 40710037SARM gem5 Developers 40810037SARM gem5 Developersdef template MicroIntXERegDeclare {{ 40910037SARM gem5 Developers class %(class_name)s : public %(base_class)s 41010037SARM gem5 Developers { 41110037SARM gem5 Developers public: 41210037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 41310037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 41410037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt); 41510037SARM gem5 Developers %(BasicExecDeclare)s 41610037SARM gem5 Developers }; 41710037SARM gem5 Developers}}; 41810037SARM gem5 Developers 4197646Sgene.wu@arm.comdef template MicroIntRegConstructor {{ 4207646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 4217646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 4227646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 4237646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 4247646Sgene.wu@arm.com _ura, _urb, _urc, _shiftAmt, _shiftType) 4257646Sgene.wu@arm.com { 4267646Sgene.wu@arm.com %(constructor)s; 4277848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4287848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4297848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4307848SAli.Saidi@ARM.com } 4317848SAli.Saidi@ARM.com } 4327646Sgene.wu@arm.com } 4337646Sgene.wu@arm.com}}; 4347646Sgene.wu@arm.com 4356019SN/A//////////////////////////////////////////////////////////////////// 4366019SN/A// 4376019SN/A// Macro Memory-format instructions 4386019SN/A// 4396019SN/A 4407134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 4416253SN/A/** 4426253SN/A * Static instructions class for a store multiple instruction 4436253SN/A */ 4446253SN/Aclass %(class_name)s : public %(base_class)s 4456253SN/A{ 4466253SN/A public: 4476253SN/A // Constructor 4487134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4497134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 4507134Sgblack@eecs.umich.edu uint32_t reglist); 4517169Sgblack@eecs.umich.edu %(BasicExecPanic)s 4526253SN/A}; 4536019SN/A}}; 4546019SN/A 4557134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 4567170Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4577134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 4587134Sgblack@eecs.umich.edu uint32_t reglist) 4597170Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 4607170Sgblack@eecs.umich.edu index, up, user, writeback, load, reglist) 4616253SN/A{ 4626253SN/A %(constructor)s; 4637848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4647848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4657848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4667848SAli.Saidi@ARM.com } 4677848SAli.Saidi@ARM.com } 4686253SN/A} 4696019SN/A 4706019SN/A}}; 4717176Sgblack@eecs.umich.edu 47210037SARM gem5 Developersdef template BigFpMemImmDeclare {{ 47310037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 47410037SARM gem5 Developers{ 47510037SARM gem5 Developers public: 47610037SARM gem5 Developers // Constructor 47710037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 47810037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 47910037SARM gem5 Developers %(BasicExecPanic)s 48010037SARM gem5 Developers}; 48110037SARM gem5 Developers}}; 48210037SARM gem5 Developers 48310037SARM gem5 Developersdef template BigFpMemImmConstructor {{ 48410037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 48510037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) 48610037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) 48710037SARM gem5 Developers{ 48810037SARM gem5 Developers %(constructor)s; 48910037SARM gem5 Developers} 49010037SARM gem5 Developers}}; 49110037SARM gem5 Developers 49210037SARM gem5 Developersdef template BigFpMemRegDeclare {{ 49310037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 49410037SARM gem5 Developers{ 49510037SARM gem5 Developers public: 49610037SARM gem5 Developers // Constructor 49710037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 49810037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 49910037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm); 50010037SARM gem5 Developers %(BasicExecPanic)s 50110037SARM gem5 Developers}; 50210037SARM gem5 Developers}}; 50310037SARM gem5 Developers 50410037SARM gem5 Developersdef template BigFpMemRegConstructor {{ 50510037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 50610037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 50710037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm) 50810037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, 50910037SARM gem5 Developers offset, type, imm) 51010037SARM gem5 Developers{ 51110037SARM gem5 Developers %(constructor)s; 51210037SARM gem5 Developers} 51310037SARM gem5 Developers}}; 51410037SARM gem5 Developers 51510037SARM gem5 Developersdef template BigFpMemLitDeclare {{ 51610037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 51710037SARM gem5 Developers{ 51810037SARM gem5 Developers public: 51910037SARM gem5 Developers // Constructor 52010037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 52110037SARM gem5 Developers IntRegIndex dest, int64_t imm); 52210037SARM gem5 Developers %(BasicExecPanic)s 52310037SARM gem5 Developers}; 52410037SARM gem5 Developers}}; 52510037SARM gem5 Developers 52610037SARM gem5 Developersdef template BigFpMemLitConstructor {{ 52710037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 52810037SARM gem5 Developers IntRegIndex dest, int64_t imm) 52910037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) 53010037SARM gem5 Developers{ 53110037SARM gem5 Developers %(constructor)s; 53210037SARM gem5 Developers} 53310037SARM gem5 Developers}}; 53410037SARM gem5 Developers 53510037SARM gem5 Developersdef template PairMemDeclare {{ 53610037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 53710037SARM gem5 Developers{ 53810037SARM gem5 Developers public: 53910037SARM gem5 Developers // Constructor 54010037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 54110037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 54210037SARM gem5 Developers bool exclusive, bool acrel, uint32_t imm, 54310037SARM gem5 Developers AddrMode mode, IntRegIndex rn, IntRegIndex rt, 54410037SARM gem5 Developers IntRegIndex rt2); 54510037SARM gem5 Developers %(BasicExecPanic)s 54610037SARM gem5 Developers}; 54710037SARM gem5 Developers}}; 54810037SARM gem5 Developers 54910037SARM gem5 Developersdef template PairMemConstructor {{ 55010037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 55110037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 55210037SARM gem5 Developers bool exclusive, bool acrel, uint32_t imm, AddrMode mode, 55310037SARM gem5 Developers IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) 55410037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, size, 55510037SARM gem5 Developers fp, load, noAlloc, signExt, exclusive, acrel, 55610037SARM gem5 Developers imm, mode, rn, rt, rt2) 55710037SARM gem5 Developers{ 55810037SARM gem5 Developers %(constructor)s; 55910037SARM gem5 Developers} 56010037SARM gem5 Developers}}; 56110037SARM gem5 Developers 5627639Sgblack@eecs.umich.edudef template VMemMultDeclare {{ 5637639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5647639Sgblack@eecs.umich.edu{ 5657639Sgblack@eecs.umich.edu public: 5667639Sgblack@eecs.umich.edu // Constructor 5677639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, unsigned width, 5687639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5697639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm); 5707639Sgblack@eecs.umich.edu %(BasicExecPanic)s 5717639Sgblack@eecs.umich.edu}; 5727639Sgblack@eecs.umich.edu}}; 5737639Sgblack@eecs.umich.edu 5747639Sgblack@eecs.umich.edudef template VMemMultConstructor {{ 5757639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 5767639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5777639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm) 5787639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 5797639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm) 5807639Sgblack@eecs.umich.edu{ 5817639Sgblack@eecs.umich.edu %(constructor)s; 5827848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5837848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 5847848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 5857848SAli.Saidi@ARM.com } 5867848SAli.Saidi@ARM.com } 5877639Sgblack@eecs.umich.edu} 5887639Sgblack@eecs.umich.edu}}; 5897639Sgblack@eecs.umich.edu 5907639Sgblack@eecs.umich.edudef template VMemSingleDeclare {{ 5917639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5927639Sgblack@eecs.umich.edu{ 5937639Sgblack@eecs.umich.edu public: 5947639Sgblack@eecs.umich.edu // Constructor 5957639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 5967639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5977639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 5987639Sgblack@eecs.umich.edu %(BasicExecPanic)s 5997639Sgblack@eecs.umich.edu}; 6007639Sgblack@eecs.umich.edu}}; 6017639Sgblack@eecs.umich.edu 6027639Sgblack@eecs.umich.edudef template VMemSingleConstructor {{ 6037639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 6047639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 6057639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 6067639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 6077639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm, lane) 6087639Sgblack@eecs.umich.edu{ 6097639Sgblack@eecs.umich.edu %(constructor)s; 6107848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 6117848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 6127848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 6137848SAli.Saidi@ARM.com } 6147848SAli.Saidi@ARM.com } 6157639Sgblack@eecs.umich.edu} 6167639Sgblack@eecs.umich.edu}}; 6177639Sgblack@eecs.umich.edu 6187176Sgblack@eecs.umich.edudef template MacroVFPMemDeclare {{ 6197176Sgblack@eecs.umich.edu/** 6207176Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 6217176Sgblack@eecs.umich.edu */ 6227176Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 6237176Sgblack@eecs.umich.edu{ 6247176Sgblack@eecs.umich.edu public: 6257176Sgblack@eecs.umich.edu // Constructor 6267176Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 6277176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, 6287176Sgblack@eecs.umich.edu bool load, uint32_t offset); 6297176Sgblack@eecs.umich.edu %(BasicExecPanic)s 6307176Sgblack@eecs.umich.edu}; 6317176Sgblack@eecs.umich.edu}}; 6327176Sgblack@eecs.umich.edu 6337176Sgblack@eecs.umich.edudef template MacroVFPMemConstructor {{ 6347176Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 6357176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, bool load, 6367176Sgblack@eecs.umich.edu uint32_t offset) 6377176Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 6387176Sgblack@eecs.umich.edu vd, single, up, writeback, load, offset) 6397176Sgblack@eecs.umich.edu{ 6407176Sgblack@eecs.umich.edu %(constructor)s; 6417848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 6427848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 6437848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 6447848SAli.Saidi@ARM.com } 6457848SAli.Saidi@ARM.com } 6467176Sgblack@eecs.umich.edu} 6477176Sgblack@eecs.umich.edu 6487176Sgblack@eecs.umich.edu}}; 649