macromem.isa revision 10196
16019SN/A// -*- mode:c++ -*- 26019SN/A 310037SARM gem5 Developers// Copyright (c) 2010-2013 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 566309SN/A %(BasicExecDeclare)s 576309SN/A %(InitiateAccDeclare)s 586309SN/A %(CompleteAccDeclare)s 596309SN/A }; 606309SN/A}}; 616309SN/A 627134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 637170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 647170Sgblack@eecs.umich.edu RegIndex _ura, 657170Sgblack@eecs.umich.edu RegIndex _urb, 667170Sgblack@eecs.umich.edu bool _up, 677170Sgblack@eecs.umich.edu uint8_t _imm) 687134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 697134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 707134Sgblack@eecs.umich.edu { 717134Sgblack@eecs.umich.edu %(constructor)s; 727848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 737848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 747848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 757848SAli.Saidi@ARM.com } 767848SAli.Saidi@ARM.com } 777134Sgblack@eecs.umich.edu } 786309SN/A}}; 796308SN/A 806308SN/A//////////////////////////////////////////////////////////////////// 816308SN/A// 827639Sgblack@eecs.umich.edu// Neon load/store microops 837639Sgblack@eecs.umich.edu// 847639Sgblack@eecs.umich.edu 857639Sgblack@eecs.umich.edudef template MicroNeonMemDeclare {{ 867639Sgblack@eecs.umich.edu template <class Element> 877639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 887639Sgblack@eecs.umich.edu { 897639Sgblack@eecs.umich.edu public: 907639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 917639Sgblack@eecs.umich.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 927639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, 937639Sgblack@eecs.umich.edu %(op_class)s, _dest, _ura, _imm) 947639Sgblack@eecs.umich.edu { 957639Sgblack@eecs.umich.edu memAccessFlags |= extraMemFlags; 967639Sgblack@eecs.umich.edu %(constructor)s; 977848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 987848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 997848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1007848SAli.Saidi@ARM.com } 1017848SAli.Saidi@ARM.com } 1027639Sgblack@eecs.umich.edu } 1037639Sgblack@eecs.umich.edu 1047639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1057639Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1067639Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1077639Sgblack@eecs.umich.edu }; 1087639Sgblack@eecs.umich.edu}}; 1097639Sgblack@eecs.umich.edu 1107639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1117639Sgblack@eecs.umich.edu// 1128140SMatt.Horsnell@arm.com// PC = Integer(ura) 1138140SMatt.Horsnell@arm.com// CPSR = Integer(urb) 1148140SMatt.Horsnell@arm.com// 1158140SMatt.Horsnell@arm.com 1168140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRDeclare {{ 1178140SMatt.Horsnell@arm.com class %(class_name)s : public %(base_class)s 1188140SMatt.Horsnell@arm.com { 1198140SMatt.Horsnell@arm.com public: 1208140SMatt.Horsnell@arm.com %(class_name)s(ExtMachInst machInst, 1218140SMatt.Horsnell@arm.com IntRegIndex _ura, 1228140SMatt.Horsnell@arm.com IntRegIndex _urb, 1238140SMatt.Horsnell@arm.com IntRegIndex _urc); 1248140SMatt.Horsnell@arm.com %(BasicExecDeclare)s 1258140SMatt.Horsnell@arm.com }; 1268140SMatt.Horsnell@arm.com}}; 1278140SMatt.Horsnell@arm.com 1288140SMatt.Horsnell@arm.comdef template MicroSetPCCPSRConstructor {{ 1298140SMatt.Horsnell@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1308140SMatt.Horsnell@arm.com IntRegIndex _ura, 1318140SMatt.Horsnell@arm.com IntRegIndex _urb, 1328140SMatt.Horsnell@arm.com IntRegIndex _urc) 1338140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1348140SMatt.Horsnell@arm.com _ura, _urb, _urc) 1358140SMatt.Horsnell@arm.com { 1368140SMatt.Horsnell@arm.com %(constructor)s; 1378140SMatt.Horsnell@arm.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1389369Snathanael.premillieu@irisa.fr flags[IsCondControl] = true; 1398140SMatt.Horsnell@arm.com for (int x = 0; x < _numDestRegs; x++) { 1408140SMatt.Horsnell@arm.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1418140SMatt.Horsnell@arm.com } 1429369Snathanael.premillieu@irisa.fr } else { 1439369Snathanael.premillieu@irisa.fr flags[IsUncondControl] = true; 1448140SMatt.Horsnell@arm.com } 1458140SMatt.Horsnell@arm.com } 1468140SMatt.Horsnell@arm.com}}; 1478140SMatt.Horsnell@arm.com 1488140SMatt.Horsnell@arm.com//////////////////////////////////////////////////////////////////// 1498140SMatt.Horsnell@arm.com// 1507639Sgblack@eecs.umich.edu// Integer = Integer op Integer microops 1517639Sgblack@eecs.umich.edu// 1527639Sgblack@eecs.umich.edu 1537639Sgblack@eecs.umich.edudef template MicroIntDeclare {{ 1547639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1557639Sgblack@eecs.umich.edu { 1567639Sgblack@eecs.umich.edu public: 1577639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1587639Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 1597639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1607639Sgblack@eecs.umich.edu }; 1617639Sgblack@eecs.umich.edu}}; 1627639Sgblack@eecs.umich.edu 1637639Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 1647639Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1657639Sgblack@eecs.umich.edu RegIndex _ura, 1667639Sgblack@eecs.umich.edu RegIndex _urb, 1677639Sgblack@eecs.umich.edu RegIndex _urc) 1687639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1697639Sgblack@eecs.umich.edu _ura, _urb, _urc) 1707639Sgblack@eecs.umich.edu { 1717639Sgblack@eecs.umich.edu %(constructor)s; 1727848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1737848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1747848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1757848SAli.Saidi@ARM.com } 1767848SAli.Saidi@ARM.com } 1777639Sgblack@eecs.umich.edu } 1787639Sgblack@eecs.umich.edu}}; 1797639Sgblack@eecs.umich.edu 1807639Sgblack@eecs.umich.edudef template MicroNeonMemExecDeclare {{ 1817639Sgblack@eecs.umich.edu template 1827639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 18310196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 1847639Sgblack@eecs.umich.edu template 1857639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 18610196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 1877639Sgblack@eecs.umich.edu template 1887639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 18910196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 1907639Sgblack@eecs.umich.edu}}; 1917639Sgblack@eecs.umich.edu 1927639Sgblack@eecs.umich.edudef template MicroNeonExecDeclare {{ 1937639Sgblack@eecs.umich.edu template 1947639Sgblack@eecs.umich.edu Fault %(class_name)s<%(targs)s>::execute( 19510196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 1967639Sgblack@eecs.umich.edu}}; 1977639Sgblack@eecs.umich.edu 1987639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 1997639Sgblack@eecs.umich.edu// 2007639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 2017639Sgblack@eecs.umich.edu// 2027639Sgblack@eecs.umich.edu 2037639Sgblack@eecs.umich.edudef template MicroNeonMixDeclare {{ 2047639Sgblack@eecs.umich.edu template <class Element> 2057639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2067639Sgblack@eecs.umich.edu { 2077639Sgblack@eecs.umich.edu public: 2087639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2097639Sgblack@eecs.umich.edu uint8_t _step) : 2107639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2117639Sgblack@eecs.umich.edu _dest, _op1, _step) 2127639Sgblack@eecs.umich.edu { 2137639Sgblack@eecs.umich.edu %(constructor)s; 2147848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2157848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2167848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2177848SAli.Saidi@ARM.com } 2187848SAli.Saidi@ARM.com } 2197639Sgblack@eecs.umich.edu } 2207639Sgblack@eecs.umich.edu 2217639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2227639Sgblack@eecs.umich.edu }; 2237639Sgblack@eecs.umich.edu}}; 2247639Sgblack@eecs.umich.edu 2257639Sgblack@eecs.umich.edudef template MicroNeonMixExecute {{ 2267639Sgblack@eecs.umich.edu template <class Element> 22710196SCurtis.Dunham@arm.com Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, 2287639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2297639Sgblack@eecs.umich.edu { 2307639Sgblack@eecs.umich.edu Fault fault = NoFault; 2317639Sgblack@eecs.umich.edu uint64_t resTemp = 0; 2327639Sgblack@eecs.umich.edu resTemp = resTemp; 2337639Sgblack@eecs.umich.edu %(op_decl)s; 2347639Sgblack@eecs.umich.edu %(op_rd)s; 2357639Sgblack@eecs.umich.edu 2367639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2377639Sgblack@eecs.umich.edu { 2387639Sgblack@eecs.umich.edu %(code)s; 2397639Sgblack@eecs.umich.edu if (fault == NoFault) 2407639Sgblack@eecs.umich.edu { 2417639Sgblack@eecs.umich.edu %(op_wb)s; 2427639Sgblack@eecs.umich.edu } 2438072SGiacomo.Gabrielli@arm.com } else { 2448072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2457639Sgblack@eecs.umich.edu } 2467639Sgblack@eecs.umich.edu 2477639Sgblack@eecs.umich.edu return fault; 2487639Sgblack@eecs.umich.edu } 2497639Sgblack@eecs.umich.edu}}; 2507639Sgblack@eecs.umich.edu 2517639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2527639Sgblack@eecs.umich.edu// 2537639Sgblack@eecs.umich.edu// Neon (un)packing microops using a particular lane 2547639Sgblack@eecs.umich.edu// 2557639Sgblack@eecs.umich.edu 2567639Sgblack@eecs.umich.edudef template MicroNeonMixLaneDeclare {{ 2577639Sgblack@eecs.umich.edu template <class Element> 2587639Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2597639Sgblack@eecs.umich.edu { 2607639Sgblack@eecs.umich.edu public: 2617639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 2627639Sgblack@eecs.umich.edu uint8_t _step, unsigned _lane) : 2637639Sgblack@eecs.umich.edu %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2647639Sgblack@eecs.umich.edu _dest, _op1, _step, _lane) 2657639Sgblack@eecs.umich.edu { 2667639Sgblack@eecs.umich.edu %(constructor)s; 2677848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2687848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2697848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2707848SAli.Saidi@ARM.com } 2717848SAli.Saidi@ARM.com } 2727639Sgblack@eecs.umich.edu } 2737639Sgblack@eecs.umich.edu 2747639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2757639Sgblack@eecs.umich.edu }; 2767639Sgblack@eecs.umich.edu}}; 2777639Sgblack@eecs.umich.edu 2787639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2797639Sgblack@eecs.umich.edu// 2807646Sgene.wu@arm.com// Integer = Integer 2817646Sgene.wu@arm.com// 2827646Sgene.wu@arm.com 2837646Sgene.wu@arm.comdef template MicroIntMovDeclare {{ 2847646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 2857646Sgene.wu@arm.com { 2867646Sgene.wu@arm.com public: 2877646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 2887646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb); 2897646Sgene.wu@arm.com %(BasicExecDeclare)s 2907646Sgene.wu@arm.com }; 2917646Sgene.wu@arm.com}}; 2927646Sgene.wu@arm.comdef template MicroIntMovConstructor {{ 2937646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 2947646Sgene.wu@arm.com RegIndex _ura, 2957646Sgene.wu@arm.com RegIndex _urb) 2967646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 2977646Sgene.wu@arm.com _ura, _urb) 2987646Sgene.wu@arm.com { 2997646Sgene.wu@arm.com %(constructor)s; 3007848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3017848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3027848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3037848SAli.Saidi@ARM.com } 3047848SAli.Saidi@ARM.com } 3057646Sgene.wu@arm.com } 3067646Sgene.wu@arm.com}}; 3077646Sgene.wu@arm.com 3087646Sgene.wu@arm.com//////////////////////////////////////////////////////////////////// 3097646Sgene.wu@arm.com// 3106308SN/A// Integer = Integer op Immediate microops 3116308SN/A// 3126308SN/A 3137639Sgblack@eecs.umich.edudef template MicroIntImmDeclare {{ 3146308SN/A class %(class_name)s : public %(base_class)s 3156308SN/A { 3166308SN/A public: 3176308SN/A %(class_name)s(ExtMachInst machInst, 3186308SN/A RegIndex _ura, RegIndex _urb, 3197646Sgene.wu@arm.com int32_t _imm); 3206308SN/A %(BasicExecDeclare)s 3216308SN/A }; 3226308SN/A}}; 3236308SN/A 3247639Sgblack@eecs.umich.edudef template MicroIntImmConstructor {{ 3257170Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 3267170Sgblack@eecs.umich.edu RegIndex _ura, 3277170Sgblack@eecs.umich.edu RegIndex _urb, 3287646Sgene.wu@arm.com int32_t _imm) 3297134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3307134Sgblack@eecs.umich.edu _ura, _urb, _imm) 3317134Sgblack@eecs.umich.edu { 3327134Sgblack@eecs.umich.edu %(constructor)s; 3337848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3347848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3357848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3367848SAli.Saidi@ARM.com } 3377848SAli.Saidi@ARM.com } 3387134Sgblack@eecs.umich.edu } 3396308SN/A}}; 3406019SN/A 34110037SARM gem5 Developersdef template MicroIntImmXConstructor {{ 34210037SARM gem5 Developers %(class_name)s::%(class_name)s(ExtMachInst machInst, 34310037SARM gem5 Developers RegIndex _ura, 34410037SARM gem5 Developers RegIndex _urb, 34510037SARM gem5 Developers int32_t _imm) 34610037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 34710037SARM gem5 Developers _ura, _urb, _imm) 34810037SARM gem5 Developers { 34910037SARM gem5 Developers %(constructor)s; 35010037SARM gem5 Developers } 35110037SARM gem5 Developers}}; 35210037SARM gem5 Developers 3537646Sgene.wu@arm.comdef template MicroIntRegDeclare {{ 3547646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 3557646Sgene.wu@arm.com { 3567646Sgene.wu@arm.com public: 3577646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 3587646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3597646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType); 3607646Sgene.wu@arm.com %(BasicExecDeclare)s 3617646Sgene.wu@arm.com }; 3627646Sgene.wu@arm.com}}; 3637646Sgene.wu@arm.com 36410037SARM gem5 Developersdef template MicroIntXERegConstructor {{ 36510037SARM gem5 Developers %(class_name)s::%(class_name)s(ExtMachInst machInst, 36610037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 36710037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt) 36810037SARM gem5 Developers : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 36910037SARM gem5 Developers _ura, _urb, _urc, _type, _shiftAmt) 37010037SARM gem5 Developers { 37110037SARM gem5 Developers %(constructor)s; 37210037SARM gem5 Developers } 37310037SARM gem5 Developers}}; 37410037SARM gem5 Developers 37510037SARM gem5 Developersdef template MicroIntXERegDeclare {{ 37610037SARM gem5 Developers class %(class_name)s : public %(base_class)s 37710037SARM gem5 Developers { 37810037SARM gem5 Developers public: 37910037SARM gem5 Developers %(class_name)s(ExtMachInst machInst, 38010037SARM gem5 Developers RegIndex _ura, RegIndex _urb, RegIndex _urc, 38110037SARM gem5 Developers ArmExtendType _type, uint32_t _shiftAmt); 38210037SARM gem5 Developers %(BasicExecDeclare)s 38310037SARM gem5 Developers }; 38410037SARM gem5 Developers}}; 38510037SARM gem5 Developers 3867646Sgene.wu@arm.comdef template MicroIntRegConstructor {{ 3877646Sgene.wu@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 3887646Sgene.wu@arm.com RegIndex _ura, RegIndex _urb, RegIndex _urc, 3897646Sgene.wu@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) 3907646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 3917646Sgene.wu@arm.com _ura, _urb, _urc, _shiftAmt, _shiftType) 3927646Sgene.wu@arm.com { 3937646Sgene.wu@arm.com %(constructor)s; 3947848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 3957848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 3967848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 3977848SAli.Saidi@ARM.com } 3987848SAli.Saidi@ARM.com } 3997646Sgene.wu@arm.com } 4007646Sgene.wu@arm.com}}; 4017646Sgene.wu@arm.com 4026019SN/A//////////////////////////////////////////////////////////////////// 4036019SN/A// 4046019SN/A// Macro Memory-format instructions 4056019SN/A// 4066019SN/A 4077134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 4086253SN/A/** 4096253SN/A * Static instructions class for a store multiple instruction 4106253SN/A */ 4116253SN/Aclass %(class_name)s : public %(base_class)s 4126253SN/A{ 4136253SN/A public: 4146253SN/A // Constructor 4157134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4167134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 4177134Sgblack@eecs.umich.edu uint32_t reglist); 4187169Sgblack@eecs.umich.edu %(BasicExecPanic)s 4196253SN/A}; 4206019SN/A}}; 4216019SN/A 4227134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 4237170Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 4247134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 4257134Sgblack@eecs.umich.edu uint32_t reglist) 4267170Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 4277170Sgblack@eecs.umich.edu index, up, user, writeback, load, reglist) 4286253SN/A{ 4296253SN/A %(constructor)s; 4307848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 4317848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 4327848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 4337848SAli.Saidi@ARM.com } 4347848SAli.Saidi@ARM.com } 4356253SN/A} 4366019SN/A 4376019SN/A}}; 4387176Sgblack@eecs.umich.edu 43910037SARM gem5 Developersdef template BigFpMemImmDeclare {{ 44010037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 44110037SARM gem5 Developers{ 44210037SARM gem5 Developers public: 44310037SARM gem5 Developers // Constructor 44410037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 44510037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 44610037SARM gem5 Developers %(BasicExecPanic)s 44710037SARM gem5 Developers}; 44810037SARM gem5 Developers}}; 44910037SARM gem5 Developers 45010037SARM gem5 Developersdef template BigFpMemImmConstructor {{ 45110037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 45210037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) 45310037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) 45410037SARM gem5 Developers{ 45510037SARM gem5 Developers %(constructor)s; 45610037SARM gem5 Developers} 45710037SARM gem5 Developers}}; 45810037SARM gem5 Developers 45910037SARM gem5 Developersdef template BigFpMemRegDeclare {{ 46010037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 46110037SARM gem5 Developers{ 46210037SARM gem5 Developers public: 46310037SARM gem5 Developers // Constructor 46410037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 46510037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 46610037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm); 46710037SARM gem5 Developers %(BasicExecPanic)s 46810037SARM gem5 Developers}; 46910037SARM gem5 Developers}}; 47010037SARM gem5 Developers 47110037SARM gem5 Developersdef template BigFpMemRegConstructor {{ 47210037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 47310037SARM gem5 Developers bool load, IntRegIndex dest, IntRegIndex base, 47410037SARM gem5 Developers IntRegIndex offset, ArmExtendType type, int64_t imm) 47510037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, 47610037SARM gem5 Developers offset, type, imm) 47710037SARM gem5 Developers{ 47810037SARM gem5 Developers %(constructor)s; 47910037SARM gem5 Developers} 48010037SARM gem5 Developers}}; 48110037SARM gem5 Developers 48210037SARM gem5 Developersdef template BigFpMemLitDeclare {{ 48310037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 48410037SARM gem5 Developers{ 48510037SARM gem5 Developers public: 48610037SARM gem5 Developers // Constructor 48710037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 48810037SARM gem5 Developers IntRegIndex dest, int64_t imm); 48910037SARM gem5 Developers %(BasicExecPanic)s 49010037SARM gem5 Developers}; 49110037SARM gem5 Developers}}; 49210037SARM gem5 Developers 49310037SARM gem5 Developersdef template BigFpMemLitConstructor {{ 49410037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 49510037SARM gem5 Developers IntRegIndex dest, int64_t imm) 49610037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) 49710037SARM gem5 Developers{ 49810037SARM gem5 Developers %(constructor)s; 49910037SARM gem5 Developers} 50010037SARM gem5 Developers}}; 50110037SARM gem5 Developers 50210037SARM gem5 Developersdef template PairMemDeclare {{ 50310037SARM gem5 Developersclass %(class_name)s : public %(base_class)s 50410037SARM gem5 Developers{ 50510037SARM gem5 Developers public: 50610037SARM gem5 Developers // Constructor 50710037SARM gem5 Developers %(class_name)s(const char *mnemonic, ExtMachInst machInst, 50810037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 50910037SARM gem5 Developers bool exclusive, bool acrel, uint32_t imm, 51010037SARM gem5 Developers AddrMode mode, IntRegIndex rn, IntRegIndex rt, 51110037SARM gem5 Developers IntRegIndex rt2); 51210037SARM gem5 Developers %(BasicExecPanic)s 51310037SARM gem5 Developers}; 51410037SARM gem5 Developers}}; 51510037SARM gem5 Developers 51610037SARM gem5 Developersdef template PairMemConstructor {{ 51710037SARM gem5 Developers%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 51810037SARM gem5 Developers uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 51910037SARM gem5 Developers bool exclusive, bool acrel, uint32_t imm, AddrMode mode, 52010037SARM gem5 Developers IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) 52110037SARM gem5 Developers : %(base_class)s(mnemonic, machInst, %(op_class)s, size, 52210037SARM gem5 Developers fp, load, noAlloc, signExt, exclusive, acrel, 52310037SARM gem5 Developers imm, mode, rn, rt, rt2) 52410037SARM gem5 Developers{ 52510037SARM gem5 Developers %(constructor)s; 52610037SARM gem5 Developers} 52710037SARM gem5 Developers}}; 52810037SARM gem5 Developers 5297639Sgblack@eecs.umich.edudef template VMemMultDeclare {{ 5307639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5317639Sgblack@eecs.umich.edu{ 5327639Sgblack@eecs.umich.edu public: 5337639Sgblack@eecs.umich.edu // Constructor 5347639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, unsigned width, 5357639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5367639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm); 5377639Sgblack@eecs.umich.edu %(BasicExecPanic)s 5387639Sgblack@eecs.umich.edu}; 5397639Sgblack@eecs.umich.edu}}; 5407639Sgblack@eecs.umich.edu 5417639Sgblack@eecs.umich.edudef template VMemMultConstructor {{ 5427639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 5437639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5447639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm) 5457639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 5467639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm) 5477639Sgblack@eecs.umich.edu{ 5487639Sgblack@eecs.umich.edu %(constructor)s; 5497848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5507848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 5517848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 5527848SAli.Saidi@ARM.com } 5537848SAli.Saidi@ARM.com } 5547639Sgblack@eecs.umich.edu} 5557639Sgblack@eecs.umich.edu}}; 5567639Sgblack@eecs.umich.edu 5577639Sgblack@eecs.umich.edudef template VMemSingleDeclare {{ 5587639Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5597639Sgblack@eecs.umich.edu{ 5607639Sgblack@eecs.umich.edu public: 5617639Sgblack@eecs.umich.edu // Constructor 5627639Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 5637639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5647639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 5657639Sgblack@eecs.umich.edu %(BasicExecPanic)s 5667639Sgblack@eecs.umich.edu}; 5677639Sgblack@eecs.umich.edu}}; 5687639Sgblack@eecs.umich.edu 5697639Sgblack@eecs.umich.edudef template VMemSingleConstructor {{ 5707639Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 5717639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 5727639Sgblack@eecs.umich.edu uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 5737639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 5747639Sgblack@eecs.umich.edu rn, vd, regs, inc, size, align, rm, lane) 5757639Sgblack@eecs.umich.edu{ 5767639Sgblack@eecs.umich.edu %(constructor)s; 5777848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5787848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 5797848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 5807848SAli.Saidi@ARM.com } 5817848SAli.Saidi@ARM.com } 5827639Sgblack@eecs.umich.edu} 5837639Sgblack@eecs.umich.edu}}; 5847639Sgblack@eecs.umich.edu 5857176Sgblack@eecs.umich.edudef template MacroVFPMemDeclare {{ 5867176Sgblack@eecs.umich.edu/** 5877176Sgblack@eecs.umich.edu * Static instructions class for a store multiple instruction 5887176Sgblack@eecs.umich.edu */ 5897176Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 5907176Sgblack@eecs.umich.edu{ 5917176Sgblack@eecs.umich.edu public: 5927176Sgblack@eecs.umich.edu // Constructor 5937176Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 5947176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, 5957176Sgblack@eecs.umich.edu bool load, uint32_t offset); 5967176Sgblack@eecs.umich.edu %(BasicExecPanic)s 5977176Sgblack@eecs.umich.edu}; 5987176Sgblack@eecs.umich.edu}}; 5997176Sgblack@eecs.umich.edu 6007176Sgblack@eecs.umich.edudef template MacroVFPMemConstructor {{ 6017176Sgblack@eecs.umich.edu%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 6027176Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, bool writeback, bool load, 6037176Sgblack@eecs.umich.edu uint32_t offset) 6047176Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 6057176Sgblack@eecs.umich.edu vd, single, up, writeback, load, offset) 6067176Sgblack@eecs.umich.edu{ 6077176Sgblack@eecs.umich.edu %(constructor)s; 6087848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 6097848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 6107848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 6117848SAli.Saidi@ARM.com } 6127848SAli.Saidi@ARM.com } 6137176Sgblack@eecs.umich.edu} 6147176Sgblack@eecs.umich.edu 6157176Sgblack@eecs.umich.edu}}; 616