113168Smatt.horsnell@arm.com// -*- mode:c++ -*-
213168Smatt.horsnell@arm.com
313168Smatt.horsnell@arm.com// Copyright (c) 2018 ARM Limited
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3713168Smatt.horsnell@arm.com//
3813168Smatt.horsnell@arm.com// Authors: Matt Horsnell
3913168Smatt.horsnell@arm.com
4013168Smatt.horsnell@arm.com// These currently all work on quad words, so some element/register
4113168Smatt.horsnell@arm.com// storage/extraction here is fixed as constants.
4213168Smatt.horsnell@arm.comdef template CryptoPredOpExecute {{
4313168Smatt.horsnell@arm.com    Fault %(class_name)s::execute(ExecContext *xc,
4413168Smatt.horsnell@arm.com                                  Trace::InstRecord *traceData) const
4513168Smatt.horsnell@arm.com    {
4613168Smatt.horsnell@arm.com        Fault fault = NoFault;
4713168Smatt.horsnell@arm.com        %(op_decl)s;
4813168Smatt.horsnell@arm.com        %(op_rd)s;
4913168Smatt.horsnell@arm.com
5013168Smatt.horsnell@arm.com        const unsigned rCount = %(r_count)d;
5113168Smatt.horsnell@arm.com
5213168Smatt.horsnell@arm.com        union RegVect {
5313544Sgabeblack@google.com            uint32_t regs[rCount];
5413168Smatt.horsnell@arm.com        };
5513168Smatt.horsnell@arm.com
5613168Smatt.horsnell@arm.com        if (%(predicate_test)s)
5713168Smatt.horsnell@arm.com        {
5813168Smatt.horsnell@arm.com            %(code)s;
5913168Smatt.horsnell@arm.com            if (fault == NoFault)
6013168Smatt.horsnell@arm.com            {
6113168Smatt.horsnell@arm.com                %(op_wb)s;
6213168Smatt.horsnell@arm.com            }
6313168Smatt.horsnell@arm.com        } else {
6413168Smatt.horsnell@arm.com            xc->setPredicate(false);
6513168Smatt.horsnell@arm.com        }
6613168Smatt.horsnell@arm.com
6713168Smatt.horsnell@arm.com        return fault;
6813168Smatt.horsnell@arm.com    }
6913168Smatt.horsnell@arm.com}};
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