branch.isa revision 8203:78b9f056d58a
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def template BranchImmDeclare {{ 41class %(class_name)s : public %(base_class)s 42{ 43 public: 44 // Constructor 45 %(class_name)s(ExtMachInst machInst, int32_t _imm); 46 %(BasicExecDeclare)s 47}; 48}}; 49 50def template BranchImmConstructor {{ 51 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 52 int32_t _imm) 53 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 54 { 55 %(constructor)s; 56 if (!(condCode == COND_AL || condCode == COND_UC)) { 57 for (int x = 0; x < _numDestRegs; x++) { 58 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 59 } 60 flags[IsCondControl] = true; 61 } else { 62 flags[IsUncondControl] = true; 63 } 64 65 } 66}}; 67 68def template BranchImmCondDeclare {{ 69class %(class_name)s : public %(base_class)s 70{ 71 public: 72 // Constructor 73 %(class_name)s(ExtMachInst machInst, int32_t _imm, 74 ConditionCode _condCode); 75 %(BasicExecDeclare)s 76 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 77}; 78}}; 79 80def template BranchImmCondConstructor {{ 81 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 82 int32_t _imm, 83 ConditionCode _condCode) 84 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 85 _imm, _condCode) 86 { 87 %(constructor)s; 88 if (!(condCode == COND_AL || condCode == COND_UC)) { 89 for (int x = 0; x < _numDestRegs; x++) { 90 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 91 } 92 flags[IsCondControl] = true; 93 } else { 94 flags[IsUncondControl] = true; 95 } 96 } 97}}; 98 99def template BranchRegDeclare {{ 100class %(class_name)s : public %(base_class)s 101{ 102 public: 103 // Constructor 104 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 105 %(BasicExecDeclare)s 106}; 107}}; 108 109def template BranchRegConstructor {{ 110 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 111 IntRegIndex _op1) 112 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 113 { 114 %(constructor)s; 115 if (!(condCode == COND_AL || condCode == COND_UC)) { 116 for (int x = 0; x < _numDestRegs; x++) { 117 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 118 } 119 flags[IsCondControl] = true; 120 } else { 121 flags[IsUncondControl] = true; 122 } 123 if (%(is_ras_pop)s) 124 flags[IsReturn] = true; 125 } 126}}; 127 128def template BranchRegCondDeclare {{ 129class %(class_name)s : public %(base_class)s 130{ 131 public: 132 // Constructor 133 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 134 ConditionCode _condCode); 135 %(BasicExecDeclare)s 136}; 137}}; 138 139def template BranchRegCondConstructor {{ 140 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 141 IntRegIndex _op1, 142 ConditionCode _condCode) 143 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 144 _op1, _condCode) 145 { 146 %(constructor)s; 147 if (!(condCode == COND_AL || condCode == COND_UC)) { 148 for (int x = 0; x < _numDestRegs; x++) { 149 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 150 } 151 flags[IsCondControl] = true; 152 } else { 153 flags[IsUncondControl] = true; 154 } 155 if (%(is_ras_pop)s) 156 flags[IsReturn] = true; 157 } 158}}; 159 160def template BranchRegRegDeclare {{ 161class %(class_name)s : public %(base_class)s 162{ 163 public: 164 // Constructor 165 %(class_name)s(ExtMachInst machInst, 166 IntRegIndex _op1, IntRegIndex _op2); 167 %(BasicExecDeclare)s 168}; 169}}; 170 171def template BranchTableDeclare {{ 172class %(class_name)s : public %(base_class)s 173{ 174 public: 175 // Constructor 176 %(class_name)s(ExtMachInst machInst, 177 IntRegIndex _op1, IntRegIndex _op2); 178 %(BasicExecDeclare)s 179 180 %(InitiateAccDeclare)s 181 182 %(CompleteAccDeclare)s 183}; 184}}; 185 186def template BranchRegRegConstructor {{ 187 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 188 IntRegIndex _op1, 189 IntRegIndex _op2) 190 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 191 { 192 %(constructor)s; 193 if (!(condCode == COND_AL || condCode == COND_UC)) { 194 for (int x = 0; x < _numDestRegs; x++) { 195 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 196 } 197 flags[IsCondControl] = true; 198 } else { 199 flags[IsUncondControl] = true; 200 } 201 } 202}}; 203 204def template BranchImmRegDeclare {{ 205class %(class_name)s : public %(base_class)s 206{ 207 public: 208 // Constructor 209 %(class_name)s(ExtMachInst machInst, 210 int32_t imm, IntRegIndex _op1); 211 %(BasicExecDeclare)s 212}; 213}}; 214 215def template BranchImmRegConstructor {{ 216 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 217 int32_t _imm, 218 IntRegIndex _op1) 219 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 220 { 221 %(constructor)s; 222 if (!(condCode == COND_AL || condCode == COND_UC)) { 223 for (int x = 0; x < _numDestRegs; x++) { 224 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 225 } 226 flags[IsCondControl] = true; 227 } else { 228 flags[IsUncondControl] = true; 229 } 230 } 231}}; 232 233def template BranchTarget {{ 234 235 ArmISA::PCState 236 %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 237 { 238 %(op_decl)s; 239 %(op_rd)s; 240 241 ArmISA::PCState pcs = branchPC; 242 %(brTgtCode)s 243 pcs.advance(); 244 return pcs; 245 } 246}}; 247 248 249