branch.isa revision 8146:18368caa8489
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def template BranchImmDeclare {{ 41class %(class_name)s : public %(base_class)s 42{ 43 public: 44 // Constructor 45 %(class_name)s(ExtMachInst machInst, int32_t _imm); 46 %(BasicExecDeclare)s 47}; 48}}; 49 50def template BranchImmConstructor {{ 51 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 52 int32_t _imm) 53 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 54 { 55 %(constructor)s; 56 if (!(condCode == COND_AL || condCode == COND_UC)) { 57 for (int x = 0; x < _numDestRegs; x++) { 58 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 59 } 60 flags[IsCondControl] = true; 61 } else { 62 flags[IsUncondControl] = true; 63 } 64 65 } 66}}; 67 68def template BranchImmCondDeclare {{ 69class %(class_name)s : public %(base_class)s 70{ 71 public: 72 // Constructor 73 %(class_name)s(ExtMachInst machInst, int32_t _imm, 74 ConditionCode _condCode); 75 %(BasicExecDeclare)s 76 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 77}; 78}}; 79 80def template BranchImmCondConstructor {{ 81 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 82 int32_t _imm, 83 ConditionCode _condCode) 84 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 85 _imm, _condCode) 86 { 87 %(constructor)s; 88 if (!(condCode == COND_AL || condCode == COND_UC)) { 89 for (int x = 0; x < _numDestRegs; x++) { 90 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 91 } 92 flags[IsCondControl] = true; 93 } else { 94 flags[IsUncondControl] = true; 95 } 96 } 97}}; 98 99def template BranchRegDeclare {{ 100class %(class_name)s : public %(base_class)s 101{ 102 public: 103 // Constructor 104 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 105 %(BasicExecDeclare)s 106}; 107}}; 108 109def template BranchRegConstructor {{ 110 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 111 IntRegIndex _op1) 112 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 113 { 114 %(constructor)s; 115 if (!(condCode == COND_AL || condCode == COND_UC)) { 116 for (int x = 0; x < _numDestRegs; x++) { 117 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 118 } 119 flags[IsCondControl] = true; 120 } else { 121 flags[IsUncondControl] = true; 122 } 123 } 124}}; 125 126def template BranchRegCondDeclare {{ 127class %(class_name)s : public %(base_class)s 128{ 129 public: 130 // Constructor 131 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 132 ConditionCode _condCode); 133 %(BasicExecDeclare)s 134}; 135}}; 136 137def template BranchRegCondConstructor {{ 138 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 139 IntRegIndex _op1, 140 ConditionCode _condCode) 141 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 142 _op1, _condCode) 143 { 144 %(constructor)s; 145 if (!(condCode == COND_AL || condCode == COND_UC)) { 146 for (int x = 0; x < _numDestRegs; x++) { 147 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 148 } 149 flags[IsCondControl] = true; 150 } else { 151 flags[IsUncondControl] = true; 152 } 153 } 154}}; 155 156def template BranchRegRegDeclare {{ 157class %(class_name)s : public %(base_class)s 158{ 159 public: 160 // Constructor 161 %(class_name)s(ExtMachInst machInst, 162 IntRegIndex _op1, IntRegIndex _op2); 163 %(BasicExecDeclare)s 164}; 165}}; 166 167def template BranchTableDeclare {{ 168class %(class_name)s : public %(base_class)s 169{ 170 public: 171 // Constructor 172 %(class_name)s(ExtMachInst machInst, 173 IntRegIndex _op1, IntRegIndex _op2); 174 %(BasicExecDeclare)s 175 176 %(InitiateAccDeclare)s 177 178 %(CompleteAccDeclare)s 179}; 180}}; 181 182def template BranchRegRegConstructor {{ 183 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 184 IntRegIndex _op1, 185 IntRegIndex _op2) 186 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 187 { 188 %(constructor)s; 189 if (!(condCode == COND_AL || condCode == COND_UC)) { 190 for (int x = 0; x < _numDestRegs; x++) { 191 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 192 } 193 flags[IsCondControl] = true; 194 } else { 195 flags[IsUncondControl] = true; 196 } 197 } 198}}; 199 200def template BranchImmRegDeclare {{ 201class %(class_name)s : public %(base_class)s 202{ 203 public: 204 // Constructor 205 %(class_name)s(ExtMachInst machInst, 206 int32_t imm, IntRegIndex _op1); 207 %(BasicExecDeclare)s 208}; 209}}; 210 211def template BranchImmRegConstructor {{ 212 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 213 int32_t _imm, 214 IntRegIndex _op1) 215 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 216 { 217 %(constructor)s; 218 if (!(condCode == COND_AL || condCode == COND_UC)) { 219 for (int x = 0; x < _numDestRegs; x++) { 220 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 221 } 222 flags[IsCondControl] = true; 223 } else { 224 flags[IsUncondControl] = true; 225 } 226 } 227}}; 228 229def template BranchTarget {{ 230 231 ArmISA::PCState 232 %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 233 { 234 %(op_decl)s; 235 %(op_rd)s; 236 237 ArmISA::PCState pcs = branchPC; 238 %(brTgtCode)s 239 pcs.advance(); 240 return pcs; 241 } 242}}; 243 244 245