branch.isa revision 7150 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template BranchImmDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43    public:
44        // Constructor
45        %(class_name)s(ExtMachInst machInst, int32_t _imm);
46        %(BasicExecDeclare)s
47};
48}};
49
50def template BranchImmConstructor {{
51    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
52                                          int32_t _imm)
53        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
54    {
55        %(constructor)s;
56    }
57}};
58
59def template BranchImmCondDeclare {{
60class %(class_name)s : public %(base_class)s
61{
62    public:
63        // Constructor
64        %(class_name)s(ExtMachInst machInst, int32_t _imm,
65                       ConditionCode _condCode);
66        %(BasicExecDeclare)s
67};
68}};
69
70def template BranchImmCondConstructor {{
71    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
72                                          int32_t _imm,
73                                          ConditionCode _condCode)
74        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
75                         _imm, _condCode)
76    {
77        %(constructor)s;
78    }
79}};
80
81def template BranchRegDeclare {{
82class %(class_name)s : public %(base_class)s
83{
84    public:
85        // Constructor
86        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
87        %(BasicExecDeclare)s
88};
89}};
90
91def template BranchRegConstructor {{
92    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
93                                          IntRegIndex _op1)
94        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
95    {
96        %(constructor)s;
97    }
98}};
99
100def template BranchRegCondDeclare {{
101class %(class_name)s : public %(base_class)s
102{
103    public:
104        // Constructor
105        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
106                       ConditionCode _condCode);
107        %(BasicExecDeclare)s
108};
109}};
110
111def template BranchRegCondConstructor {{
112    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
113                                          IntRegIndex _op1,
114                                          ConditionCode _condCode)
115        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
116                         _op1, _condCode)
117    {
118        %(constructor)s;
119    }
120}};
121
122def template BranchRegRegDeclare {{
123class %(class_name)s : public %(base_class)s
124{
125    public:
126        // Constructor
127        %(class_name)s(ExtMachInst machInst,
128                       IntRegIndex _op1, IntRegIndex _op2);
129        %(BasicExecDeclare)s
130};
131}};
132
133def template BranchTableDeclare {{
134class %(class_name)s : public %(base_class)s
135{
136    public:
137        // Constructor
138        %(class_name)s(ExtMachInst machInst,
139                       IntRegIndex _op1, IntRegIndex _op2);
140        %(BasicExecDeclare)s
141
142        %(InitiateAccDeclare)s
143
144        %(CompleteAccDeclare)s
145};
146}};
147
148def template BranchRegRegConstructor {{
149    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
150                                          IntRegIndex _op1,
151                                          IntRegIndex _op2)
152        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
153    {
154        %(constructor)s;
155    }
156}};
157
158def template BranchImmRegDeclare {{
159class %(class_name)s : public %(base_class)s
160{
161    public:
162        // Constructor
163        %(class_name)s(ExtMachInst machInst,
164                       int32_t imm, IntRegIndex _op1);
165        %(BasicExecDeclare)s
166};
167}};
168
169def template BranchImmRegConstructor {{
170    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
171                                          int32_t _imm,
172                                          IntRegIndex _op1)
173        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
174    {
175        %(constructor)s;
176    }
177}};
178