xref: /gem5/src/arch/arm/isa/templates/branch.isa

// -*- mode:c++ -*-

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// Authors: Gabe Black

def template BranchImmDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, int32_t _imm);
        %(BasicExecDeclare)s
};
}};

def template BranchImmConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          int32_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
            flags[IsCondControl] = true;
        } else {
            flags[IsUncondControl] = true;
        }

    }
}};

def template BranchImmCondDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, int32_t _imm,
                       ConditionCode _condCode);
        %(BasicExecDeclare)s
        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;
};
}};

def template BranchImmCondConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          int32_t _imm,
                                          ConditionCode _condCode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _imm, _condCode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
            flags[IsCondControl] = true;
        } else {
            flags[IsUncondControl] = true;
        }
    }
}};

def template BranchRegDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
        %(BasicExecDeclare)s
};
}};

def template BranchRegConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _op1)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
            flags[IsCondControl] = true;
        } else {
            flags[IsUncondControl] = true;
        }
        if (%(is_ras_pop)s)
            flags[IsReturn] = true;
    }
}};

def template BranchRegCondDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                       ConditionCode _condCode);
        %(BasicExecDeclare)s
};
}};

def template BranchRegCondConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _op1,
                                          ConditionCode _condCode)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _op1, _condCode)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
            flags[IsCondControl] = true;
        } else {
            flags[IsUncondControl] = true;
        }
        if (%(is_ras_pop)s)
            flags[IsReturn] = true;
    }
}};

def template BranchRegRegDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _op1, IntRegIndex _op2);
        %(BasicExecDeclare)s
};
}};

def template BranchTableDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _op1, IntRegIndex _op2);
        %(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s
};
}};

def template BranchRegRegConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
    {
        %(constructor)s;
        if (!(condCode == COND_AL || condCode == COND_UC)) {
            for (int x = 0; x < _numDestRegs; x++) {
                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
            }
            flags[IsCondControl] = true;
        } else {
            flags[IsUncondControl] = true;
        }
    }
}};

def template BranchImmRegDeclare {{
class %(class_name)s : public %(base_class)s
{
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       int32_t imm, IntRegIndex _op1);
        %(BasicExecDeclare)s
        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;
};
}};

// Only used by CBNZ, CBZ which is conditional based on
// a register value even though the instruction is always unconditional.
def template BranchImmRegConstructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          int32_t _imm,
                                          IntRegIndex _op1)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
    {
        %(constructor)s;
        flags[IsCondControl] = true;
    }
}};

def template BranchTarget {{

    ArmISA::PCState
    %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
    {
        %(op_decl)s;
        %(op_rd)s;

        ArmISA::PCState pcs = branchPC;
        %(brTgtCode)s
        pcs.advance();
        return pcs;
    }
}};