branch.isa revision 8203
17150Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27150Sgblack@eecs.umich.edu 37150Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47150Sgblack@eecs.umich.edu// All rights reserved 57150Sgblack@eecs.umich.edu// 67150Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77150Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87150Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97150Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107150Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117150Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127150Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137150Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147150Sgblack@eecs.umich.edu// 157150Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167150Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177150Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187150Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197150Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207150Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217150Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227150Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237150Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247150Sgblack@eecs.umich.edu// this software without specific prior written permission. 257150Sgblack@eecs.umich.edu// 267150Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277150Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287150Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297150Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307150Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317150Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327150Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337150Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347150Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357150Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367150Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377150Sgblack@eecs.umich.edu// 387150Sgblack@eecs.umich.edu// Authors: Gabe Black 397150Sgblack@eecs.umich.edu 407150Sgblack@eecs.umich.edudef template BranchImmDeclare {{ 417150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 427150Sgblack@eecs.umich.edu{ 437150Sgblack@eecs.umich.edu public: 447150Sgblack@eecs.umich.edu // Constructor 457150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, int32_t _imm); 467150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 477150Sgblack@eecs.umich.edu}; 487150Sgblack@eecs.umich.edu}}; 497150Sgblack@eecs.umich.edu 507150Sgblack@eecs.umich.edudef template BranchImmConstructor {{ 517150Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 527150Sgblack@eecs.umich.edu int32_t _imm) 537150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 547150Sgblack@eecs.umich.edu { 557150Sgblack@eecs.umich.edu %(constructor)s; 567848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 577848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 587848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 597848SAli.Saidi@ARM.com } 608146SAli.Saidi@ARM.com flags[IsCondControl] = true; 618146SAli.Saidi@ARM.com } else { 628146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 637848SAli.Saidi@ARM.com } 648146SAli.Saidi@ARM.com 657150Sgblack@eecs.umich.edu } 667150Sgblack@eecs.umich.edu}}; 677150Sgblack@eecs.umich.edu 687150Sgblack@eecs.umich.edudef template BranchImmCondDeclare {{ 697150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 707150Sgblack@eecs.umich.edu{ 717150Sgblack@eecs.umich.edu public: 727150Sgblack@eecs.umich.edu // Constructor 737150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, int32_t _imm, 747150Sgblack@eecs.umich.edu ConditionCode _condCode); 757150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 768146SAli.Saidi@ARM.com ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 777150Sgblack@eecs.umich.edu}; 787150Sgblack@eecs.umich.edu}}; 797150Sgblack@eecs.umich.edu 807150Sgblack@eecs.umich.edudef template BranchImmCondConstructor {{ 817150Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 827150Sgblack@eecs.umich.edu int32_t _imm, 837150Sgblack@eecs.umich.edu ConditionCode _condCode) 847150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 857150Sgblack@eecs.umich.edu _imm, _condCode) 867150Sgblack@eecs.umich.edu { 877150Sgblack@eecs.umich.edu %(constructor)s; 887848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 897848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 907848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 917848SAli.Saidi@ARM.com } 928146SAli.Saidi@ARM.com flags[IsCondControl] = true; 938146SAli.Saidi@ARM.com } else { 948146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 957848SAli.Saidi@ARM.com } 967150Sgblack@eecs.umich.edu } 977150Sgblack@eecs.umich.edu}}; 987150Sgblack@eecs.umich.edu 997150Sgblack@eecs.umich.edudef template BranchRegDeclare {{ 1007150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1017150Sgblack@eecs.umich.edu{ 1027150Sgblack@eecs.umich.edu public: 1037150Sgblack@eecs.umich.edu // Constructor 1047150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 1057150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1067150Sgblack@eecs.umich.edu}; 1077150Sgblack@eecs.umich.edu}}; 1087150Sgblack@eecs.umich.edu 1097150Sgblack@eecs.umich.edudef template BranchRegConstructor {{ 1107150Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1117150Sgblack@eecs.umich.edu IntRegIndex _op1) 1127150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 1137150Sgblack@eecs.umich.edu { 1147150Sgblack@eecs.umich.edu %(constructor)s; 1157848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1167848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1177848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1187848SAli.Saidi@ARM.com } 1198146SAli.Saidi@ARM.com flags[IsCondControl] = true; 1208146SAli.Saidi@ARM.com } else { 1218146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 1227848SAli.Saidi@ARM.com } 1238203SAli.Saidi@ARM.com if (%(is_ras_pop)s) 1248203SAli.Saidi@ARM.com flags[IsReturn] = true; 1257150Sgblack@eecs.umich.edu } 1267150Sgblack@eecs.umich.edu}}; 1277150Sgblack@eecs.umich.edu 1287150Sgblack@eecs.umich.edudef template BranchRegCondDeclare {{ 1297150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1307150Sgblack@eecs.umich.edu{ 1317150Sgblack@eecs.umich.edu public: 1327150Sgblack@eecs.umich.edu // Constructor 1337150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 1347150Sgblack@eecs.umich.edu ConditionCode _condCode); 1357150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1367150Sgblack@eecs.umich.edu}; 1377150Sgblack@eecs.umich.edu}}; 1387150Sgblack@eecs.umich.edu 1397150Sgblack@eecs.umich.edudef template BranchRegCondConstructor {{ 1407150Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1417150Sgblack@eecs.umich.edu IntRegIndex _op1, 1427150Sgblack@eecs.umich.edu ConditionCode _condCode) 1437150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1447150Sgblack@eecs.umich.edu _op1, _condCode) 1457150Sgblack@eecs.umich.edu { 1467150Sgblack@eecs.umich.edu %(constructor)s; 1477848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1487848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1497848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1507848SAli.Saidi@ARM.com } 1518146SAli.Saidi@ARM.com flags[IsCondControl] = true; 1528146SAli.Saidi@ARM.com } else { 1538146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 1547848SAli.Saidi@ARM.com } 1558203SAli.Saidi@ARM.com if (%(is_ras_pop)s) 1568203SAli.Saidi@ARM.com flags[IsReturn] = true; 1577150Sgblack@eecs.umich.edu } 1587150Sgblack@eecs.umich.edu}}; 1597150Sgblack@eecs.umich.edu 1607150Sgblack@eecs.umich.edudef template BranchRegRegDeclare {{ 1617150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1627150Sgblack@eecs.umich.edu{ 1637150Sgblack@eecs.umich.edu public: 1647150Sgblack@eecs.umich.edu // Constructor 1657150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1667150Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2); 1677150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1687150Sgblack@eecs.umich.edu}; 1697150Sgblack@eecs.umich.edu}}; 1707150Sgblack@eecs.umich.edu 1717150Sgblack@eecs.umich.edudef template BranchTableDeclare {{ 1727150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1737150Sgblack@eecs.umich.edu{ 1747150Sgblack@eecs.umich.edu public: 1757150Sgblack@eecs.umich.edu // Constructor 1767150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1777150Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2); 1787150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1797150Sgblack@eecs.umich.edu 1807150Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1817150Sgblack@eecs.umich.edu 1827150Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1837150Sgblack@eecs.umich.edu}; 1847150Sgblack@eecs.umich.edu}}; 1857150Sgblack@eecs.umich.edu 1867150Sgblack@eecs.umich.edudef template BranchRegRegConstructor {{ 1877150Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1887150Sgblack@eecs.umich.edu IntRegIndex _op1, 1897150Sgblack@eecs.umich.edu IntRegIndex _op2) 1907150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 1917150Sgblack@eecs.umich.edu { 1927150Sgblack@eecs.umich.edu %(constructor)s; 1937848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1947848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1957848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1967848SAli.Saidi@ARM.com } 1978146SAli.Saidi@ARM.com flags[IsCondControl] = true; 1988146SAli.Saidi@ARM.com } else { 1998146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 2007848SAli.Saidi@ARM.com } 2017150Sgblack@eecs.umich.edu } 2027150Sgblack@eecs.umich.edu}}; 2037150Sgblack@eecs.umich.edu 2047150Sgblack@eecs.umich.edudef template BranchImmRegDeclare {{ 2057150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 2067150Sgblack@eecs.umich.edu{ 2077150Sgblack@eecs.umich.edu public: 2087150Sgblack@eecs.umich.edu // Constructor 2097150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 2107150Sgblack@eecs.umich.edu int32_t imm, IntRegIndex _op1); 2117150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2127150Sgblack@eecs.umich.edu}; 2137150Sgblack@eecs.umich.edu}}; 2147150Sgblack@eecs.umich.edu 2157150Sgblack@eecs.umich.edudef template BranchImmRegConstructor {{ 2167150Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 2177150Sgblack@eecs.umich.edu int32_t _imm, 2187150Sgblack@eecs.umich.edu IntRegIndex _op1) 2197150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 2207150Sgblack@eecs.umich.edu { 2217150Sgblack@eecs.umich.edu %(constructor)s; 2227848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2237848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 2247848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2257848SAli.Saidi@ARM.com } 2268146SAli.Saidi@ARM.com flags[IsCondControl] = true; 2278146SAli.Saidi@ARM.com } else { 2288146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 2297848SAli.Saidi@ARM.com } 2307150Sgblack@eecs.umich.edu } 2317150Sgblack@eecs.umich.edu}}; 2328146SAli.Saidi@ARM.com 2338146SAli.Saidi@ARM.comdef template BranchTarget {{ 2348146SAli.Saidi@ARM.com 2358146SAli.Saidi@ARM.com ArmISA::PCState 2368146SAli.Saidi@ARM.com %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 2378146SAli.Saidi@ARM.com { 2388146SAli.Saidi@ARM.com %(op_decl)s; 2398146SAli.Saidi@ARM.com %(op_rd)s; 2408146SAli.Saidi@ARM.com 2418146SAli.Saidi@ARM.com ArmISA::PCState pcs = branchPC; 2428146SAli.Saidi@ARM.com %(brTgtCode)s 2438146SAli.Saidi@ARM.com pcs.advance(); 2448146SAli.Saidi@ARM.com return pcs; 2458146SAli.Saidi@ARM.com } 2468146SAli.Saidi@ARM.com}}; 2478146SAli.Saidi@ARM.com 2488146SAli.Saidi@ARM.com 249