branch.isa revision 10184
111723Sar4jc@virginia.edu// -*- mode:c++ -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu// Copyright (c) 2010 ARM Limited 411723Sar4jc@virginia.edu// All rights reserved 511723Sar4jc@virginia.edu// 611723Sar4jc@virginia.edu// The license below extends only to copyright in the software and shall 711723Sar4jc@virginia.edu// not be construed as granting a license to any other intellectual 811723Sar4jc@virginia.edu// property including but not limited to intellectual property relating 911723Sar4jc@virginia.edu// to a hardware implementation of the functionality of the software 1011723Sar4jc@virginia.edu// licensed hereunder. You may use the software subject to the license 1111723Sar4jc@virginia.edu// terms below provided that you ensure that this notice is replicated 1211723Sar4jc@virginia.edu// unmodified and in its entirety in all distributions of the software, 1311723Sar4jc@virginia.edu// modified or unmodified, in source code or in binary form. 1411723Sar4jc@virginia.edu// 1511723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 1611723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 1711723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1811723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1911723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 2011723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 2111723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 2211723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 2311723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 2411723Sar4jc@virginia.edu// this software without specific prior written permission. 2511723Sar4jc@virginia.edu// 2611723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2711723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2811723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2911723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3011723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3111723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3211723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3311723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3411723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3511723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3611723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3711723Sar4jc@virginia.edu// 3811723Sar4jc@virginia.edu// Authors: Gabe Black 3911723Sar4jc@virginia.edu 4011723Sar4jc@virginia.edudef template BranchImmDeclare {{ 4111723Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 4211723Sar4jc@virginia.edu{ 4311723Sar4jc@virginia.edu public: 4411723Sar4jc@virginia.edu // Constructor 4511723Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst, int32_t _imm); 4611723Sar4jc@virginia.edu %(BasicExecDeclare)s 4711794Sbrandon.potter@amd.com}; 4811723Sar4jc@virginia.edu}}; 4911723Sar4jc@virginia.edu 5011723Sar4jc@virginia.edudef template BranchImmConstructor {{ 5111723Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 5211723Sar4jc@virginia.edu int32_t _imm) 5311723Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 5411723Sar4jc@virginia.edu { 5511723Sar4jc@virginia.edu %(constructor)s; 5611851Sbrandon.potter@amd.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5711723Sar4jc@virginia.edu for (int x = 0; x < _numDestRegs; x++) { 5811723Sar4jc@virginia.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 5911723Sar4jc@virginia.edu } 6011723Sar4jc@virginia.edu flags[IsCondControl] = true; 6111723Sar4jc@virginia.edu } else { 6211723Sar4jc@virginia.edu flags[IsUncondControl] = true; 6311723Sar4jc@virginia.edu } 6411723Sar4jc@virginia.edu 6511723Sar4jc@virginia.edu } 6611723Sar4jc@virginia.edu}}; 6711723Sar4jc@virginia.edu 6811723Sar4jc@virginia.edudef template BranchImmCondDeclare {{ 6911723Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 7011723Sar4jc@virginia.edu{ 7111723Sar4jc@virginia.edu public: 7211723Sar4jc@virginia.edu // Constructor 7312297Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst, int32_t _imm, 7412297Sar4jc@virginia.edu ConditionCode _condCode); 7512297Sar4jc@virginia.edu %(BasicExecDeclare)s 7612297Sar4jc@virginia.edu ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 7712297Sar4jc@virginia.edu 7812297Sar4jc@virginia.edu /// Explicitly import the otherwise hidden branchTarget 7912297Sar4jc@virginia.edu using StaticInst::branchTarget; 8012297Sar4jc@virginia.edu}; 8112297Sar4jc@virginia.edu}}; 8212297Sar4jc@virginia.edu 8312297Sar4jc@virginia.edudef template BranchImmCondConstructor {{ 8412297Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 8512297Sar4jc@virginia.edu int32_t _imm, 8612297Sar4jc@virginia.edu ConditionCode _condCode) 8712297Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8812297Sar4jc@virginia.edu _imm, _condCode) 8912297Sar4jc@virginia.edu { 9012297Sar4jc@virginia.edu %(constructor)s; 9112297Sar4jc@virginia.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9212297Sar4jc@virginia.edu for (int x = 0; x < _numDestRegs; x++) { 9312297Sar4jc@virginia.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9412297Sar4jc@virginia.edu } 9512297Sar4jc@virginia.edu flags[IsCondControl] = true; 9612297Sar4jc@virginia.edu } else { 9712297Sar4jc@virginia.edu flags[IsUncondControl] = true; 9812297Sar4jc@virginia.edu } 9912297Sar4jc@virginia.edu } 10012297Sar4jc@virginia.edu}}; 10112297Sar4jc@virginia.edu 10212297Sar4jc@virginia.edudef template BranchRegDeclare {{ 10312297Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 10412297Sar4jc@virginia.edu{ 10512297Sar4jc@virginia.edu public: 10612297Sar4jc@virginia.edu // Constructor 10712297Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 10812297Sar4jc@virginia.edu %(BasicExecDeclare)s 10912297Sar4jc@virginia.edu}; 11012297Sar4jc@virginia.edu}}; 11112297Sar4jc@virginia.edu 11212297Sar4jc@virginia.edudef template BranchRegConstructor {{ 11312297Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 11412297Sar4jc@virginia.edu IntRegIndex _op1) 11512297Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 11612297Sar4jc@virginia.edu { 11712297Sar4jc@virginia.edu %(constructor)s; 11812297Sar4jc@virginia.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 11912297Sar4jc@virginia.edu for (int x = 0; x < _numDestRegs; x++) { 12012297Sar4jc@virginia.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12112297Sar4jc@virginia.edu } 12212297Sar4jc@virginia.edu flags[IsCondControl] = true; 12312297Sar4jc@virginia.edu } else { 12412297Sar4jc@virginia.edu flags[IsUncondControl] = true; 12512297Sar4jc@virginia.edu } 12612297Sar4jc@virginia.edu if (%(is_ras_pop)s) 12712297Sar4jc@virginia.edu flags[IsReturn] = true; 12812297Sar4jc@virginia.edu } 12912297Sar4jc@virginia.edu}}; 13012297Sar4jc@virginia.edu 13112297Sar4jc@virginia.edudef template BranchRegCondDeclare {{ 13212297Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 13312297Sar4jc@virginia.edu{ 13412297Sar4jc@virginia.edu public: 13512297Sar4jc@virginia.edu // Constructor 13612297Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 13712297Sar4jc@virginia.edu ConditionCode _condCode); 13812297Sar4jc@virginia.edu %(BasicExecDeclare)s 13912297Sar4jc@virginia.edu}; 14012297Sar4jc@virginia.edu}}; 14112297Sar4jc@virginia.edu 14212297Sar4jc@virginia.edudef template BranchRegCondConstructor {{ 14312297Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 14412297Sar4jc@virginia.edu IntRegIndex _op1, 14512297Sar4jc@virginia.edu ConditionCode _condCode) 14612297Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 14712297Sar4jc@virginia.edu _op1, _condCode) 14812297Sar4jc@virginia.edu { 14912297Sar4jc@virginia.edu %(constructor)s; 15012297Sar4jc@virginia.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 15112297Sar4jc@virginia.edu for (int x = 0; x < _numDestRegs; x++) { 15212297Sar4jc@virginia.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 15312297Sar4jc@virginia.edu } 15412297Sar4jc@virginia.edu flags[IsCondControl] = true; 15512297Sar4jc@virginia.edu } else { 15612297Sar4jc@virginia.edu flags[IsUncondControl] = true; 15712297Sar4jc@virginia.edu } 15812297Sar4jc@virginia.edu if (%(is_ras_pop)s) 15912297Sar4jc@virginia.edu flags[IsReturn] = true; 16012297Sar4jc@virginia.edu } 16112297Sar4jc@virginia.edu}}; 16212297Sar4jc@virginia.edu 16312297Sar4jc@virginia.edudef template BranchRegRegDeclare {{ 16412297Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 16512297Sar4jc@virginia.edu{ 16612297Sar4jc@virginia.edu public: 16712297Sar4jc@virginia.edu // Constructor 16812414Sqtt2@cornell.edu %(class_name)s(ExtMachInst machInst, 16912297Sar4jc@virginia.edu IntRegIndex _op1, IntRegIndex _op2); 17012297Sar4jc@virginia.edu %(BasicExecDeclare)s 17112297Sar4jc@virginia.edu}; 17212297Sar4jc@virginia.edu}}; 17312297Sar4jc@virginia.edu 17412297Sar4jc@virginia.edudef template BranchTableDeclare {{ 17512297Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 17612297Sar4jc@virginia.edu{ 17712297Sar4jc@virginia.edu public: 17812297Sar4jc@virginia.edu // Constructor 17912297Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst, 18012297Sar4jc@virginia.edu IntRegIndex _op1, IntRegIndex _op2); 18112297Sar4jc@virginia.edu %(BasicExecDeclare)s 18212297Sar4jc@virginia.edu 18312297Sar4jc@virginia.edu %(InitiateAccDeclare)s 18412297Sar4jc@virginia.edu 18512297Sar4jc@virginia.edu %(CompleteAccDeclare)s 18612297Sar4jc@virginia.edu}; 18712297Sar4jc@virginia.edu}}; 18812297Sar4jc@virginia.edu 18912297Sar4jc@virginia.edudef template BranchRegRegConstructor {{ 19012297Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 19112297Sar4jc@virginia.edu IntRegIndex _op1, 19212297Sar4jc@virginia.edu IntRegIndex _op2) 19312297Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 19412297Sar4jc@virginia.edu { 19512297Sar4jc@virginia.edu %(constructor)s; 19612297Sar4jc@virginia.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 19712297Sar4jc@virginia.edu for (int x = 0; x < _numDestRegs; x++) { 19812297Sar4jc@virginia.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 19912297Sar4jc@virginia.edu } 20012297Sar4jc@virginia.edu flags[IsCondControl] = true; 20112297Sar4jc@virginia.edu } else { 20212297Sar4jc@virginia.edu flags[IsUncondControl] = true; 20312297Sar4jc@virginia.edu } 20412297Sar4jc@virginia.edu } 20512297Sar4jc@virginia.edu}}; 20612297Sar4jc@virginia.edu 20712297Sar4jc@virginia.edudef template BranchImmRegDeclare {{ 20812297Sar4jc@virginia.educlass %(class_name)s : public %(base_class)s 20912297Sar4jc@virginia.edu{ 21012297Sar4jc@virginia.edu public: 21112297Sar4jc@virginia.edu // Constructor 21212297Sar4jc@virginia.edu %(class_name)s(ExtMachInst machInst, 21312297Sar4jc@virginia.edu int32_t imm, IntRegIndex _op1); 21412297Sar4jc@virginia.edu %(BasicExecDeclare)s 21512297Sar4jc@virginia.edu}; 21612297Sar4jc@virginia.edu}}; 21712297Sar4jc@virginia.edu 21812297Sar4jc@virginia.edu// Only used by CBNZ, CBZ which is conditional based on 21912297Sar4jc@virginia.edu// a register value even though the instruction is always unconditional. 22012297Sar4jc@virginia.edudef template BranchImmRegConstructor {{ 22112297Sar4jc@virginia.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 22212297Sar4jc@virginia.edu int32_t _imm, 22312297Sar4jc@virginia.edu IntRegIndex _op1) 22412297Sar4jc@virginia.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 22512297Sar4jc@virginia.edu { 22612297Sar4jc@virginia.edu %(constructor)s; 22712297Sar4jc@virginia.edu flags[IsCondControl] = true; 22812297Sar4jc@virginia.edu } 22912297Sar4jc@virginia.edu}}; 23012297Sar4jc@virginia.edu 23112297Sar4jc@virginia.edudef template BranchTarget {{ 23212297Sar4jc@virginia.edu 23312297Sar4jc@virginia.edu ArmISA::PCState 23412297Sar4jc@virginia.edu %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 23512297Sar4jc@virginia.edu { 23612297Sar4jc@virginia.edu %(op_decl)s; 23712297Sar4jc@virginia.edu %(op_rd)s; 23812297Sar4jc@virginia.edu 23912297Sar4jc@virginia.edu ArmISA::PCState pcs = branchPC; 24012297Sar4jc@virginia.edu %(brTgtCode)s 24112297Sar4jc@virginia.edu pcs.advance(); 24212297Sar4jc@virginia.edu return pcs; 24312297Sar4jc@virginia.edu } 24412297Sar4jc@virginia.edu}}; 24512297Sar4jc@virginia.edu 24612297Sar4jc@virginia.edu 24712297Sar4jc@virginia.edu