operands.isa revision 8303 
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14// Copyright (c) 2007-2008 The Florida State University
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'tud' : ('twin64 int', 64),
51    'sf' : ('float', 32),
52    'df' : ('float', 64)
53}};
54
55let {{
56    maybePCRead = '''
57        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybeAlignedPCRead = '''
60        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
61         xc->%(func)s(this, %(op_idx)s))
62    '''
63    maybePCWrite = '''
64        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66    '''
67    maybeIWPCWrite = '''
68        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70    '''
71    maybeAIWPCWrite = '''
72        if (%(reg_idx)s == PCReg) {
73            bool thumb = THUMB;
74            if (thumb) {
75                setNextPC(xc, %(final_val)s);
76            } else {
77                setIWNextPC(xc, %(final_val)s);
78            }
79        } else {
80            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81        }
82    '''
83
84    #PCState operands need to have a sorting index (the number at the end)
85    #less than all the integer registers which might update the PC. That way
86    #if the flag bits of the pc state are updated and a branch happens through
87    #R15, the updates are layered properly and the R15 update isn't lost.
88    srtNormal = 5
89    srtCpsr = 4
90    srtBase = 3
91    srtPC = 2
92    srtMode = 1
93    srtEPC = 0
94
95    def floatReg(idx):
96        return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
97
98    def intReg(idx):
99        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
100                maybePCRead, maybePCWrite)
101
102    def intRegNPC(idx):
103        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
104
105    def intRegAPC(idx, id = srtNormal):
106        return ('IntReg', 'uw', idx, 'IsInteger', id,
107                maybeAlignedPCRead, maybePCWrite)
108
109    def intRegIWPC(idx):
110        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
111                maybePCRead, maybeIWPCWrite)
112
113    def intRegAIWPC(idx):
114        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
115                maybePCRead, maybeAIWPCWrite)
116
117    def intRegCC(idx):
118        return ('IntReg', 'uw', idx, None, srtNormal)
119
120    def cntrlReg(idx, id = srtNormal, type = 'uw'):
121        return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
122
123    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
124        return ('ControlReg', type, idx, None, id)
125
126    def pcStateReg(idx, id):
127        return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
128}};
129
130def operands {{
131    #Abstracted integer reg operands
132    'Dest': intReg('dest'),
133    'IWDest': intRegIWPC('dest'),
134    'AIWDest': intRegAIWPC('dest'),
135    'Dest2': intReg('dest2'),
136    'Result': intReg('result'),
137    'Base': intRegAPC('base', id = srtBase),
138    'Index': intReg('index'),
139    'Shift': intReg('shift'),
140    'Op1': intReg('op1'),
141    'Op2': intReg('op2'),
142    'Op3': intReg('op3'),
143    'Reg0': intReg('reg0'),
144    'Reg1': intReg('reg1'),
145    'Reg2': intReg('reg2'),
146    'Reg3': intReg('reg3'),
147
148    #Fixed index integer reg operands
149    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
150    'LR': intRegNPC('INTREG_LR'),
151    'R7': intRegNPC('7'),
152    # First four arguments are passed in registers
153    'R0': intRegNPC('0'),
154    'R1': intRegNPC('1'),
155    'R2': intRegNPC('2'),
156    'R3': intRegNPC('3'),
157
158    #Pseudo integer condition code registers
159    'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
160    'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
161    'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
162    'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
163    'OptCondCodesNZ': intRegCC(
164            '''(condCode == COND_AL || condCode == COND_UC ||
165                condCode == COND_CC || condCode == COND_CS ||
166                condCode == COND_VS || condCode == COND_VC) ?
167               INTREG_ZERO : INTREG_CONDCODES_NZ'''),
168    'OptCondCodesC': intRegCC(
169            '''(condCode == COND_HI || condCode == COND_LS ||
170                condCode == COND_CS || condCode == COND_CC) ?
171               INTREG_CONDCODES_C : INTREG_ZERO'''),
172    'OptCondCodesV': intRegCC(
173            '''(condCode == COND_VS || condCode == COND_VC ||
174                condCode == COND_GE || condCode == COND_LT ||
175                condCode == COND_GT || condCode == COND_LE) ?
176               INTREG_CONDCODES_V : INTREG_ZERO'''),
177    'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
178
179    #Abstracted floating point reg operands
180    'FpDest': floatReg('(dest + 0)'),
181    'FpDestP0': floatReg('(dest + 0)'),
182    'FpDestP1': floatReg('(dest + 1)'),
183    'FpDestP2': floatReg('(dest + 2)'),
184    'FpDestP3': floatReg('(dest + 3)'),
185    'FpDestP4': floatReg('(dest + 4)'),
186    'FpDestP5': floatReg('(dest + 5)'),
187    'FpDestP6': floatReg('(dest + 6)'),
188    'FpDestP7': floatReg('(dest + 7)'),
189    'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
190    'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
191    'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
192    'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
193    'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
194    'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
195    'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
196    'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
197
198    'FpDest2': floatReg('(dest2 + 0)'),
199    'FpDest2P0': floatReg('(dest2 + 0)'),
200    'FpDest2P1': floatReg('(dest2 + 1)'),
201    'FpDest2P2': floatReg('(dest2 + 2)'),
202    'FpDest2P3': floatReg('(dest2 + 3)'),
203
204    'FpOp1': floatReg('(op1 + 0)'),
205    'FpOp1P0': floatReg('(op1 + 0)'),
206    'FpOp1P1': floatReg('(op1 + 1)'),
207    'FpOp1P2': floatReg('(op1 + 2)'),
208    'FpOp1P3': floatReg('(op1 + 3)'),
209    'FpOp1P4': floatReg('(op1 + 4)'),
210    'FpOp1P5': floatReg('(op1 + 5)'),
211    'FpOp1P6': floatReg('(op1 + 6)'),
212    'FpOp1P7': floatReg('(op1 + 7)'),
213    'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
214    'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
215    'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
216    'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
217    'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
218    'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
219    'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
220    'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
221
222    'FpOp2': floatReg('(op2 + 0)'),
223    'FpOp2P0': floatReg('(op2 + 0)'),
224    'FpOp2P1': floatReg('(op2 + 1)'),
225    'FpOp2P2': floatReg('(op2 + 2)'),
226    'FpOp2P3': floatReg('(op2 + 3)'),
227
228    #Abstracted control reg operands
229    'MiscDest': cntrlReg('dest'),
230    'MiscOp1': cntrlReg('op1'),
231
232    #Fixed index control regs
233    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
234    'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
235    'Spsr': cntrlRegNC('MISCREG_SPSR'),
236    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
237    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
238    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
239    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
240    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
241    'Cpacr': cntrlReg('MISCREG_CPACR'),
242    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
243    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
244    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
245    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
246
247    #Register fields for microops
248    'URa' : intReg('ura'),
249    'IWRa' : intRegIWPC('ura'),
250    'Fa' : floatReg('ura'),
251    'URb' : intReg('urb'),
252    'URc' : intReg('urc'),
253
254    #Memory Operand
255    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
256
257    #PCState fields
258    'PC': pcStateReg('instPC', srtPC),
259    'NPC': pcStateReg('instNPC', srtPC),
260    'pNPC': pcStateReg('instNPC', srtEPC),
261    'IWNPC': pcStateReg('instIWNPC', srtPC),
262    'Thumb': pcStateReg('thumb', srtPC),
263    'NextThumb': pcStateReg('nextThumb', srtMode),
264    'NextJazelle': pcStateReg('nextJazelle', srtMode),
265    'NextItState': pcStateReg('nextItstate', srtMode),
266    'Itstate': pcStateReg('itstate', srtMode),
267
268    #Register operands depending on a field in the instruction encoding. These
269    #should be avoided since they may not be portable across different
270    #encodings of the same instruction.
271    'Rd': intReg('RD'),
272    'Rm': intReg('RM'),
273    'Rs': intReg('RS'),
274    'Rn': intReg('RN'),
275    'Rt': intReg('RT')
276}};
277