xref: /gem5/src/arch/arm/isa/operands.isa

// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines

def operand_types {{
    'sb' : ('signed int', 8),
    'ub' : ('unsigned int', 8),
    'sh' : ('signed int', 16),
    'uh' : ('unsigned int', 16),
    'sw' : ('signed int', 32),
    'uw' : ('unsigned int', 32),
    'ud' : ('unsigned int', 64),
    'tud' : ('twin64 int', 64),
    'sf' : ('float', 32),
    'df' : ('float', 64)
}};

let {{
    maybePCRead = '''
        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
    '''
    maybeAlignedPCRead = '''
        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
         xc->%(func)s(this, %(op_idx)s))
    '''
    maybePCWrite = '''
        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
    maybeIWPCWrite = '''
        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
    maybeAIWPCWrite = '''
        if (%(reg_idx)s == PCReg) {
            bool thumb = THUMB;
            if (thumb) {
                setNextPC(xc, %(final_val)s);
            } else {
                setIWNextPC(xc, %(final_val)s);
            }
        } else {
            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
        }
    '''
}};

def operands {{
    #Abstracted integer reg operands
    'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
             maybePCRead, maybePCWrite),
    'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
    'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
    'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3),
    'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3),
    'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3),
    'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3),
    'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3),
    'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3),
    'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3),
    'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3),
    'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3),
    'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3),
    'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3),
    'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3),
    'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3),
    'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3),
    'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3),
    'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3,
               maybePCRead, maybePCWrite),
    'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
    'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
    'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3),
    'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3),
    'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3),
    'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
               maybePCRead, maybeIWPCWrite),
    'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
                maybePCRead, maybeAIWPCWrite),
    'SpMode': ('IntReg', 'uw',
               'intRegInMode((OperatingMode)regMode, INTREG_SP)',
               'IsInteger', 3),
    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3),
    'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
             maybeAlignedPCRead, maybePCWrite),
    'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
    'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
    'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3),
    'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3),
    'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3),
    'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3),
    'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3),
    'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3),
    'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3),
    'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3),
    'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3),
    'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3),
    'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3),
    'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3),
    'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3),
    'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3),
    'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3),
    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3),
    'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
    'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
    'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3),
    'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3),
    'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3),
    'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3,
              maybePCRead, maybePCWrite),
    #General Purpose Integer Reg Operands
    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
    'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
    'R1': ('IntReg', 'uw', '0', 'IsInteger', 3),
    'R2': ('IntReg', 'uw', '1', 'IsInteger', 3),
    'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite),

    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),
    'OptCondCodes': ('IntReg', 'uw',
            '''(condCode == COND_AL || condCode == COND_UC) ?
               INTREG_ZERO : INTREG_CONDCODES''', None, 3),
    'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3),

    #Register fields for microops
    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3,
            maybePCRead, maybeIWPCWrite),
    'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3),
    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite),

    #General Purpose Floating Point Reg Operands
    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 3),
    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 3),
    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),

    #Memory Operand
    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3),

    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2),
    'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3),
    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3),
    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3),
    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3),
    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),
    'FpscrQc': ('ControlReg', 'uw', 'MISCREG_FPSCR_QC', None, 3),
    'FpscrExc': ('ControlReg', 'uw', 'MISCREG_FPSCR_EXC', None, 3),
    'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3),
    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3),
    'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3),
    'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3),
    #PCS needs to have a sorting index (the number at the end) less than all
    #the integer registers which might update the PC. That way if the flag
    #bits of the pc state are updated and a branch happens through R15, the
    #updates are layered properly and the R15 update isn't lost.
    'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0)
}};