operands.isa revision 7720 
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14// Copyright (c) 2007-2008 The Florida State University
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'tud' : ('twin64 int', 64),
51    'sf' : ('float', 32),
52    'df' : ('float', 64)
53}};
54
55let {{
56    maybePCRead = '''
57        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybeAlignedPCRead = '''
60        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
61         xc->%(func)s(this, %(op_idx)s))
62    '''
63    maybePCWrite = '''
64        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66    '''
67    maybeIWPCWrite = '''
68        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70    '''
71    maybeAIWPCWrite = '''
72        if (%(reg_idx)s == PCReg) {
73            bool thumb = THUMB;
74            if (thumb) {
75                setNextPC(xc, %(final_val)s);
76            } else {
77                setIWNextPC(xc, %(final_val)s);
78            }
79        } else {
80            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81        }
82    '''
83}};
84
85def operands {{
86    #Abstracted integer reg operands
87    'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
88             maybePCRead, maybePCWrite),
89    'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
90    'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
91    'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3),
92    'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3),
93    'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3),
94    'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3),
95    'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3),
96    'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3),
97    'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3),
98    'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3),
99    'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3),
100    'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3),
101    'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3),
102    'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3),
103    'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3),
104    'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3),
105    'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3),
106    'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3,
107               maybePCRead, maybePCWrite),
108    'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3,
109              maybePCRead, maybePCWrite),
110    'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
111    'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
112    'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3),
113    'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3),
114    'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3),
115    'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
116               maybePCRead, maybeIWPCWrite),
117    'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
118                maybePCRead, maybeAIWPCWrite),
119    'SpMode': ('IntReg', 'uw',
120               'intRegInMode((OperatingMode)regMode, INTREG_SP)',
121               'IsInteger', 3),
122    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3),
123    'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
124             maybeAlignedPCRead, maybePCWrite),
125    'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3,
126              maybePCRead, maybePCWrite),
127    'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
128              maybePCRead, maybePCWrite),
129    'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
130    'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
131    'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3),
132    'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3),
133    'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3),
134    'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3),
135    'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3),
136    'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3),
137    'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3),
138    'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3),
139    'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3),
140    'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3),
141    'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3),
142    'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3),
143    'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3),
144    'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3),
145    'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3),
146    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3),
147    'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3,
148              maybePCRead, maybePCWrite),
149    'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
150    'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
151    'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3),
152    'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3),
153    'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3),
154    'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3,
155              maybePCRead, maybePCWrite),
156    'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3,
157              maybePCRead, maybePCWrite),
158    'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3,
159              maybePCRead, maybePCWrite),
160    'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3,
161              maybePCRead, maybePCWrite),
162    'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3,
163              maybePCRead, maybePCWrite),
164    'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3,
165              maybePCRead, maybePCWrite),
166    #General Purpose Integer Reg Operands
167    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite),
168    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite),
169    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
170    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
171    'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
172    'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
173
174    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
175    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),
176    'OptCondCodes': ('IntReg', 'uw',
177            '''(condCode == COND_AL || condCode == COND_UC) ?
178               INTREG_ZERO : INTREG_CONDCODES''', None, 3),
179    'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3),
180
181    #Register fields for microops
182    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite),
183    'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3,
184            maybePCRead, maybeIWPCWrite),
185    'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3),
186    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite),
187    'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite),
188
189    #General Purpose Floating Point Reg Operands
190    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 3),
191    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 3),
192    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
193
194    #Memory Operand
195    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3),
196
197    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2),
198    'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3),
199    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3),
200    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3),
201    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3),
202    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),
203    'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3),
204    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3),
205    'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3),
206    'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3),
207    #PCS needs to have a sorting index (the number at the end) less than all
208    #the integer registers which might update the PC. That way if the flag
209    #bits of the pc state are updated and a branch happens through R15, the
210    #updates are layered properly and the R15 update isn't lost.
211    'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0)
212}};
213