operands.isa revision 7422
112953Sgabeblack@google.com// -*- mode:c++ -*-
212953Sgabeblack@google.com// Copyright (c) 2010 ARM Limited
312953Sgabeblack@google.com// All rights reserved
412953Sgabeblack@google.com//
512953Sgabeblack@google.com// The license below extends only to copyright in the software and shall
612953Sgabeblack@google.com// not be construed as granting a license to any other intellectual
712953Sgabeblack@google.com// property including but not limited to intellectual property relating
812953Sgabeblack@google.com// to a hardware implementation of the functionality of the software
912953Sgabeblack@google.com// licensed hereunder.  You may use the software subject to the license
1012953Sgabeblack@google.com// terms below provided that you ensure that this notice is replicated
1112953Sgabeblack@google.com// unmodified and in its entirety in all distributions of the software,
1212953Sgabeblack@google.com// modified or unmodified, in source code or in binary form.
1312953Sgabeblack@google.com//
1412953Sgabeblack@google.com// Copyright (c) 2007-2008 The Florida State University
1512953Sgabeblack@google.com// All rights reserved.
1612953Sgabeblack@google.com//
1712953Sgabeblack@google.com// Redistribution and use in source and binary forms, with or without
1812953Sgabeblack@google.com// modification, are permitted provided that the following conditions are
1912953Sgabeblack@google.com// met: redistributions of source code must retain the above copyright
2012953Sgabeblack@google.com// notice, this list of conditions and the following disclaimer;
2112953Sgabeblack@google.com// redistributions in binary form must reproduce the above copyright
2212953Sgabeblack@google.com// notice, this list of conditions and the following disclaimer in the
2312953Sgabeblack@google.com// documentation and/or other materials provided with the distribution;
2412953Sgabeblack@google.com// neither the name of the copyright holders nor the names of its
2512953Sgabeblack@google.com// contributors may be used to endorse or promote products derived from
2612953Sgabeblack@google.com// this software without specific prior written permission.
2712953Sgabeblack@google.com//
2812953Sgabeblack@google.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
2912953Sgabeblack@google.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3012953Sgabeblack@google.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
3112953Sgabeblack@google.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
3212953Sgabeblack@google.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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3512953Sgabeblack@google.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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3712953Sgabeblack@google.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
3812953Sgabeblack@google.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3912953Sgabeblack@google.com//
4012953Sgabeblack@google.com// Authors: Stephen Hines
4112953Sgabeblack@google.com
4212953Sgabeblack@google.comdef operand_types {{
4312953Sgabeblack@google.com    'sb' : ('signed int', 8),
4412953Sgabeblack@google.com    'ub' : ('unsigned int', 8),
4512953Sgabeblack@google.com    'sh' : ('signed int', 16),
4612953Sgabeblack@google.com    'uh' : ('unsigned int', 16),
4712953Sgabeblack@google.com    'sw' : ('signed int', 32),
4812953Sgabeblack@google.com    'uw' : ('unsigned int', 32),
4912953Sgabeblack@google.com    'ud' : ('unsigned int', 64),
5012953Sgabeblack@google.com    'sf' : ('float', 32),
5112953Sgabeblack@google.com    'df' : ('float', 64)
5212953Sgabeblack@google.com}};
5312953Sgabeblack@google.com
5412953Sgabeblack@google.comlet {{
5512953Sgabeblack@google.com    maybePCRead = '''
5612953Sgabeblack@google.com        ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
5712953Sgabeblack@google.com         xc->%(func)s(this, %(op_idx)s))
5812953Sgabeblack@google.com    '''
5912953Sgabeblack@google.com    maybeAlignedPCRead = '''
6012953Sgabeblack@google.com        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
6112953Sgabeblack@google.com         xc->%(func)s(this, %(op_idx)s))
6212953Sgabeblack@google.com    '''
6312953Sgabeblack@google.com    maybePCWrite = '''
6412953Sgabeblack@google.com        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
6512953Sgabeblack@google.com         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
6612953Sgabeblack@google.com    '''
6712953Sgabeblack@google.com    maybeIWPCWrite = '''
6812953Sgabeblack@google.com        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
6912953Sgabeblack@google.com         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
7012953Sgabeblack@google.com    '''
7112953Sgabeblack@google.com    maybeAIWPCWrite = '''
7212953Sgabeblack@google.com        if (%(reg_idx)s == PCReg) {
7312953Sgabeblack@google.com            bool thumb = THUMB;
7412953Sgabeblack@google.com            if (thumb) {
7512953Sgabeblack@google.com                setNextPC(xc, %(final_val)s);
7612953Sgabeblack@google.com            } else {
7712953Sgabeblack@google.com                setIWNextPC(xc, %(final_val)s);
7812953Sgabeblack@google.com            }
7912953Sgabeblack@google.com        } else {
8012953Sgabeblack@google.com            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
8112953Sgabeblack@google.com        }
8212953Sgabeblack@google.com    '''
8312953Sgabeblack@google.com
8412953Sgabeblack@google.com    readNPC = 'xc->readNextPC() & ~PcModeMask'
8512953Sgabeblack@google.com    writeNPC = 'setNextPC(xc, %(final_val)s)'
8612953Sgabeblack@google.com    writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
8712953Sgabeblack@google.com    forceNPC = 'xc->setNextPC(%(final_val)s)'
8812953Sgabeblack@google.com}};
8912953Sgabeblack@google.com
9012953Sgabeblack@google.comdef operands {{
9112953Sgabeblack@google.com    #Abstracted integer reg operands
9212953Sgabeblack@google.com    'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
9312953Sgabeblack@google.com             maybePCRead, maybePCWrite),
9412953Sgabeblack@google.com    'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
9512953Sgabeblack@google.com    'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
9612953Sgabeblack@google.com    'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
9712953Sgabeblack@google.com    'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
9812953Sgabeblack@google.com    'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
9912953Sgabeblack@google.com    'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
10012953Sgabeblack@google.com               maybePCRead, maybePCWrite),
10112953Sgabeblack@google.com    'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
102              maybePCRead, maybePCWrite),
103    'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
104    'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
105    'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
106    'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
107    'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
108    'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
109               maybePCRead, maybeIWPCWrite),
110    'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
111                maybePCRead, maybeAIWPCWrite),
112    'SpMode': ('IntReg', 'uw',
113               'intRegInMode((OperatingMode)regMode, INTREG_SP)',
114               'IsInteger', 2),
115    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
116    'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
117             maybeAlignedPCRead, maybePCWrite),
118    'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
119              maybePCRead, maybePCWrite),
120    'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
121              maybePCRead, maybePCWrite),
122    'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
123    'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
124    'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
125    'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
126    'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
127    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
128    'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
129              maybePCRead, maybePCWrite),
130    'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
131    'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
132    'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
133    'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
134    'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
135    'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
136              maybePCRead, maybePCWrite),
137    'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
138              maybePCRead, maybePCWrite),
139    'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
140              maybePCRead, maybePCWrite),
141    'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
142              maybePCRead, maybePCWrite),
143    'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
144              maybePCRead, maybePCWrite),
145    'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
146              maybePCRead, maybePCWrite),
147    #General Purpose Integer Reg Operands
148    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
149    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
150    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
151    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
152    'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
153    'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
154
155    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
156    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
157    'OptCondCodes': ('IntReg', 'uw',
158            '''(condCode == COND_AL || condCode == COND_UC) ?
159               INTREG_ZERO : INTREG_CONDCODES''', None, 2),
160
161    #Register fields for microops
162    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
163    'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
164            maybePCRead, maybeIWPCWrite),
165    'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
166    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
167
168    #General Purpose Floating Point Reg Operands
169    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
170    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
171    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
172
173    #Memory Operand
174    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
175
176    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
177    'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
178    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
179    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
180    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
181    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
182    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
183    'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
184    'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
185    'PC': ('PC', 'ud', None, None, 2),
186    'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
187            readNPC, writeNPC),
188    'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
189             readNPC, forceNPC),
190    'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
191              readNPC, writeIWNPC),
192}};
193