operands.isa revision 7093 
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14// Copyright (c) 2007-2008 The Florida State University
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40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'sf' : ('float', 32),
51    'df' : ('float', 64)
52}};
53
54let {{
55    maybePCRead = '''
56        ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
57         xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybePCWrite = '''
60        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62    '''
63
64    readNPC = 'xc->readNextPC() & ~PcModeMask'
65    writeNPC = 'setNextPC(xc, %(final_val)s)'
66}};
67
68def operands {{
69    #General Purpose Integer Reg Operands
70    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
71    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
72    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
73    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
74    'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
75    'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
76
77    #Destination register for load/store double instructions
78    'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
79    'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
80
81    'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
82    'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
83    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
84    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
85
86    #Register fields for microops
87    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
88    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
89
90    #General Purpose Floating Point Reg Operands
91    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
92    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
93    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
94
95    #Memory Operand
96    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
97
98    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
99    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
100    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
101    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
102    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
103    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
104    'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 50,
105            readNPC, writeNPC),
106}};
107