operands.isa revision 7091 
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14// Copyright (c) 2007-2008 The Florida State University
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40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'sf' : ('float', 32),
51    'df' : ('float', 64)
52}};
53
54let {{
55    maybePCRead = '''
56        ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
57         xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybePCWrite = '''
60        ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
61         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62    '''
63}};
64
65def operands {{
66    #General Purpose Integer Reg Operands
67    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
68    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
69    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
70    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
71    'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
72    'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
73
74    #Destination register for load/store double instructions
75    'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
76    'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
77
78    'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
79    'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
80    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
81    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
82
83    #Register fields for microops
84    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
85    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
86
87    #General Purpose Floating Point Reg Operands
88    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
89    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
90    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
91
92    #Memory Operand
93    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
94
95    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', None, 40),
96    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
97    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
98    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
99    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
100    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
101    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
102    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)
103
104}};
105