operands.isa revision 6308:46fcf4dc4c30 
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2
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29// Authors: Stephen Hines
30
31def operand_types {{
32    'sb' : ('signed int', 8),
33    'ub' : ('unsigned int', 8),
34    'sh' : ('signed int', 16),
35    'uh' : ('unsigned int', 16),
36    'sw' : ('signed int', 32),
37    'uw' : ('unsigned int', 32),
38    'ud' : ('unsigned int', 64),
39    'sf' : ('float', 32),
40    'df' : ('float', 64)
41}};
42
43def operands {{
44    #General Purpose Integer Reg Operands
45    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
46    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
47    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
48    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
49
50    #Destination register for load/store double instructions
51    'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4),
52    'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5),
53
54    'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
55    'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
56    'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
57    'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
58
59    #Register fields for microops
60    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11),
61    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12),
62
63    #General Purpose Floating Point Reg Operands
64    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
65    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
66    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
67
68    #Memory Operand
69    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
70
71    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
72    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
73    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
74    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
75
76}};
77