operands.isa revision 6247:094b7ea0b180 
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2
3// Copyright (c) 2007-2008 The Florida State University
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28//
29// Authors: Stephen Hines
30
31def operand_types {{
32    'sb' : ('signed int', 8),
33    'ub' : ('unsigned int', 8),
34    'sh' : ('signed int', 16),
35    'uh' : ('unsigned int', 16),
36    'sw' : ('signed int', 32),
37    'uw' : ('unsigned int', 32),
38    'ud' : ('unsigned int', 64),
39    'sf' : ('float', 32),
40    'df' : ('float', 64)
41}};
42
43def operands {{
44    #General Purpose Integer Reg Operands
45    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
46    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
47    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
48    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
49
50    'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
51    'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),
52    'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
53    'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
54    'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
55    'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
56    'Ignore': ('IntReg', 'uw', '16', 'IsInteger', 99),
57
58    #General Purpose Floating Point Reg Operands
59    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
60    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
61    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
62
63    #Memory Operand
64    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
65
66    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
67    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
68    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
69    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
70
71}};
72