operands.isa revision 13604:d219aedd88df 
1// -*- mode:c++ -*-
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14// Copyright (c) 2007-2008 The Florida State University
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : 'int8_t',
44    'ub' : 'uint8_t',
45    'sh' : 'int16_t',
46    'uh' : 'uint16_t',
47    'sw' : 'int32_t',
48    'uw' : 'uint32_t',
49    'ud' : 'uint64_t',
50    'tud' : 'std::array<uint64_t, 2>',
51    'sf' : 'float',
52    'df' : 'double',
53    'vc' : 'TheISA::VecRegContainer',
54    # For operations that are implemented as a template
55    'x' : 'TPElem',
56}};
57
58let {{
59    maybePCRead = '''
60        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61    '''
62    maybeAlignedPCRead = '''
63        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
64         xc->%(func)s(this, %(op_idx)s))
65    '''
66    maybePCWrite = '''
67        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
68         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
69    '''
70    maybeIWPCWrite = '''
71        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
72         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
73    '''
74    maybeAIWPCWrite = '''
75        if (%(reg_idx)s == PCReg) {
76            bool thumb = THUMB;
77            if (thumb) {
78                setNextPC(xc, %(final_val)s);
79            } else {
80                setIWNextPC(xc, %(final_val)s);
81            }
82        } else {
83            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
84        }
85    '''
86    aarch64Read = '''
87        ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
88    '''
89    aarch64Write = '''
90        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
91    '''
92    aarchX64Read = '''
93        ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
94    '''
95    aarchX64Write = '''
96        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
97    '''
98    aarchW64Read = '''
99        ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
100    '''
101    aarchW64Write = '''
102        xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
103    '''
104    cntrlNsBankedWrite = '''
105        xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
106    '''
107
108    cntrlNsBankedRead = '''
109        xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
110    '''
111
112    #PCState operands need to have a sorting index (the number at the end)
113    #less than all the integer registers which might update the PC. That way
114    #if the flag bits of the pc state are updated and a branch happens through
115    #R15, the updates are layered properly and the R15 update isn't lost.
116    srtNormal = 5
117    srtCpsr = 4
118    srtBase = 3
119    srtPC = 2
120    srtMode = 1
121    srtEPC = 0
122
123    def vectorElem(idx, elem):
124        return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
125
126    def vectorReg(idx, elems = None):
127        return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
128
129    def vectorRegElem(elem, ext = 'sf', zeroing = False):
130        return (elem, ext, zeroing)
131
132    def intReg(idx):
133        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
134                maybePCRead, maybePCWrite)
135
136    def intReg64(idx):
137        return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
138                aarch64Read, aarch64Write)
139
140    def intRegX64(idx, id = srtNormal):
141        return ('IntReg', 'ud', idx, 'IsInteger', id,
142                aarchX64Read, aarchX64Write)
143
144    def intRegW64(idx, id = srtNormal):
145        return ('IntReg', 'ud', idx, 'IsInteger', id,
146                aarchW64Read, aarchW64Write)
147
148    def intRegNPC(idx):
149        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
150
151    def intRegAPC(idx, id = srtNormal):
152        return ('IntReg', 'uw', idx, 'IsInteger', id,
153                maybeAlignedPCRead, maybePCWrite)
154
155    def intRegIWPC(idx):
156        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
157                maybePCRead, maybeIWPCWrite)
158
159    def intRegAIWPC(idx):
160        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
161                maybePCRead, maybeAIWPCWrite)
162
163    def ccReg(idx):
164        return ('CCReg', 'uw', idx, None, srtNormal)
165
166    def cntrlReg(idx, id = srtNormal, type = 'uw'):
167        return ('ControlReg', type, idx, None, id)
168
169    def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
170        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
171
172    def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
173        return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
174
175    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
176        return ('ControlReg', type, idx, None, id)
177
178    def pcStateReg(idx, id):
179        return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
180}};
181
182def operands {{
183    #Abstracted integer reg operands
184    'Dest': intReg('dest'),
185    'Dest64': intReg64('dest'),
186    'XDest': intRegX64('dest'),
187    'WDest': intRegW64('dest'),
188    'IWDest': intRegIWPC('dest'),
189    'AIWDest': intRegAIWPC('dest'),
190    'Dest2': intReg('dest2'),
191    'XDest2': intRegX64('dest2'),
192    'IWDest2': intRegIWPC('dest2'),
193    'Result': intReg('result'),
194    'XResult': intRegX64('result'),
195    'XBase': intRegX64('base', id = srtBase),
196    'Base': intRegAPC('base', id = srtBase),
197    'XOffset': intRegX64('offset'),
198    'Index': intReg('index'),
199    'Shift': intReg('shift'),
200    'Op1': intReg('op1'),
201    'Op2': intReg('op2'),
202    'Op3': intReg('op3'),
203    'Op164': intReg64('op1'),
204    'Op264': intReg64('op2'),
205    'Op364': intReg64('op3'),
206    'XOp1': intRegX64('op1'),
207    'XOp2': intRegX64('op2'),
208    'XOp3': intRegX64('op3'),
209    'WOp1': intRegW64('op1'),
210    'WOp2': intRegW64('op2'),
211    'WOp3': intRegW64('op3'),
212    'Reg0': intReg('reg0'),
213    'Reg1': intReg('reg1'),
214    'Reg2': intReg('reg2'),
215    'Reg3': intReg('reg3'),
216
217    #Fixed index integer reg operands
218    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
219    'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
220    'LR': intRegNPC('INTREG_LR'),
221    'XLR': intRegX64('INTREG_X30'),
222    'R7': intRegNPC('7'),
223    # First four arguments are passed in registers
224    'R0': intRegNPC('0'),
225    'R1': intRegNPC('1'),
226    'R2': intRegNPC('2'),
227    'R3': intRegNPC('3'),
228    'X0': intRegX64('0'),
229    'X1': intRegX64('1'),
230    'X2': intRegX64('2'),
231    'X3': intRegX64('3'),
232
233    # Condition code registers
234    'CondCodesNZ': ccReg('CCREG_NZ'),
235    'CondCodesC': ccReg('CCREG_C'),
236    'CondCodesV': ccReg('CCREG_V'),
237    'CondCodesGE': ccReg('CCREG_GE'),
238    'OptCondCodesNZ': ccReg(
239            '''((condCode == COND_AL || condCode == COND_UC ||
240                 condCode == COND_CC || condCode == COND_CS ||
241                 condCode == COND_VS || condCode == COND_VC) ?
242                CCREG_ZERO : CCREG_NZ)'''),
243    'OptCondCodesC': ccReg(
244             '''((condCode == COND_HI || condCode == COND_LS ||
245                condCode == COND_CS || condCode == COND_CC) ?
246               CCREG_C : CCREG_ZERO)'''),
247    'OptShiftRmCondCodesC': ccReg(
248            '''((condCode == COND_HI || condCode == COND_LS ||
249                 condCode == COND_CS || condCode == COND_CC ||
250                 shiftType == ROR) ?
251                CCREG_C : CCREG_ZERO)'''),
252    'OptCondCodesV': ccReg(
253            '''((condCode == COND_VS || condCode == COND_VC ||
254                 condCode == COND_GE || condCode == COND_LT ||
255                 condCode == COND_GT || condCode == COND_LE) ?
256                CCREG_V : CCREG_ZERO)'''),
257    'FpCondCodes': ccReg('CCREG_FP'),
258
259    #Abstracted floating point reg operands
260    'FpDest': vectorElem('dest / 4', 'dest % 4'),
261    'FpDestP0': vectorElem('dest / 4', '(dest % 4) + 0'),
262    'FpDestP1': vectorElem('dest / 4', '(dest % 4) + 1'),
263    'FpDestP2': vectorElem('dest / 4', '(dest % 4) + 2'),
264    'FpDestP3': vectorElem('dest / 4', '(dest % 4) + 3'),
265    'FpDestP4': vectorElem('(dest / 4) + 1', '(dest % 4) + 0'),
266    'FpDestP5': vectorElem('(dest / 4) + 1', '(dest % 4) + 1'),
267    'FpDestP6': vectorElem('(dest / 4) + 1', '(dest % 4) + 2'),
268    'FpDestP7': vectorElem('(dest / 4) + 1', '(dest % 4) + 3'),
269
270    'FpDestS0P0': vectorElem(
271        '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'),
272    'FpDestS0P1': vectorElem(
273        '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'),
274    'FpDestS1P0': vectorElem(
275        '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'),
276    'FpDestS1P1': vectorElem(
277        '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'),
278    'FpDestS2P0': vectorElem(
279        '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'),
280    'FpDestS2P1': vectorElem(
281        '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'),
282    'FpDestS3P0': vectorElem(
283        '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'),
284    'FpDestS3P1': vectorElem(
285        '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'),
286
287    'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'),
288    'FpDest2P0': vectorElem('dest2 / 4', '(dest2 % 4) + 0'),
289    'FpDest2P1': vectorElem('dest2 / 4', '(dest2 % 4) + 1'),
290    'FpDest2P2': vectorElem('dest2 / 4', '(dest2 % 4) + 2'),
291    'FpDest2P3': vectorElem('dest2 / 4', '(dest2 % 4) + 3'),
292
293    'FpOp1': vectorElem('op1 / 4', 'op1 % 4'),
294    'FpOp1P0': vectorElem('op1 / 4', '(op1 % 4) + 0'),
295    'FpOp1P1': vectorElem('op1 / 4', '(op1 % 4) + 1'),
296    'FpOp1P2': vectorElem('op1 / 4', '(op1 % 4) + 2'),
297    'FpOp1P3': vectorElem('op1 / 4', '(op1 % 4) + 3'),
298    'FpOp1P4': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 0'),
299    'FpOp1P5': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 1'),
300    'FpOp1P6': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 2'),
301    'FpOp1P7': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 3'),
302
303    'FpOp1S0P0': vectorElem(
304        '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'),
305    'FpOp1S0P1': vectorElem(
306        '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'),
307    'FpOp1S1P0': vectorElem(
308        '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'),
309    'FpOp1S1P1': vectorElem(
310        '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'),
311    'FpOp1S2P0': vectorElem(
312        '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'),
313    'FpOp1S2P1': vectorElem(
314        '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'),
315    'FpOp1S3P0': vectorElem(
316        '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'),
317    'FpOp1S3P1': vectorElem(
318        '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'),
319
320    'FpOp2': vectorElem('op2 / 4', 'op2 % 4'),
321    'FpOp2P0': vectorElem('op2 / 4', '(op2 % 4) + 0'),
322    'FpOp2P1': vectorElem('op2 / 4', '(op2 % 4) + 1'),
323    'FpOp2P2': vectorElem('op2 / 4', '(op2 % 4) + 2'),
324    'FpOp2P3': vectorElem('op2 / 4', '(op2 % 4) + 3'),
325
326    # Create AArch64 unpacked view of the FP registers
327    # Name   ::= 'AA64Vec' OpSpec [LaneSpec]
328    # OpSpec ::= IOSpec [Index] [Plus]
329    # IOSpec ::= 'S' | 'D'
330    # Index  ::= '0' | ... | '9'
331    # Plus  ::= [PlusAmount] ['l']
332    # PlusAmount ::= 'p' [PlusAmount]
333    # LaneSpec ::= 'L' Index
334    #
335    # All the constituents are hierarchically defined as part of the Vector
336    # Register they belong to
337
338    'AA64FpOp1':       vectorReg('op1',
339    {
340        'AA64FpOp1P0': vectorRegElem('0'),
341        'AA64FpOp1P1': vectorRegElem('1'),
342        'AA64FpOp1P2': vectorRegElem('2'),
343        'AA64FpOp1P3': vectorRegElem('3'),
344        'AA64FpOp1S':  vectorRegElem('0', 'sf', zeroing = True),
345        'AA64FpOp1D':  vectorRegElem('0', 'df', zeroing = True),
346        'AA64FpOp1Q':  vectorRegElem('0', 'tud', zeroing = True)
347    }),
348
349    'AA64FpOp2':       vectorReg('op2',
350    {
351        'AA64FpOp2P0': vectorRegElem('0'),
352        'AA64FpOp2P1': vectorRegElem('1'),
353        'AA64FpOp2P2': vectorRegElem('2'),
354        'AA64FpOp2P3': vectorRegElem('3'),
355        'AA64FpOp2S':  vectorRegElem('0', 'sf', zeroing = True),
356        'AA64FpOp2D':  vectorRegElem('0', 'df', zeroing = True),
357        'AA64FpOp2Q':  vectorRegElem('0', 'tud', zeroing = True)
358    }),
359
360    'AA64FpOp3':       vectorReg('op3',
361    {
362        'AA64FpOp3P0': vectorRegElem('0'),
363        'AA64FpOp3P1': vectorRegElem('1'),
364        'AA64FpOp3P2': vectorRegElem('2'),
365        'AA64FpOp3P3': vectorRegElem('3'),
366        'AA64FpOp3S':  vectorRegElem('0', 'sf', zeroing = True),
367        'AA64FpOp3D':  vectorRegElem('0', 'df', zeroing = True),
368        'AA64FpOp3Q':  vectorRegElem('0', 'tud', zeroing = True)
369    }),
370
371    'AA64FpDest':       vectorReg('dest',
372    {
373        'AA64FpDestP0': vectorRegElem('0'),
374        'AA64FpDestP1': vectorRegElem('1'),
375        'AA64FpDestP2': vectorRegElem('2'),
376        'AA64FpDestP3': vectorRegElem('3'),
377        'AA64FpDestS':  vectorRegElem('0', 'sf', zeroing = True),
378        'AA64FpDestD':  vectorRegElem('0', 'df', zeroing = True),
379        'AA64FpDestQ':  vectorRegElem('0', 'tud', zeroing = True)
380    }),
381
382    'AA64FpDest2':       vectorReg('dest2',
383    {
384        'AA64FpDest2P0': vectorRegElem('0'),
385        'AA64FpDest2P1': vectorRegElem('1'),
386        'AA64FpDest2P2': vectorRegElem('2'),
387        'AA64FpDest2P3': vectorRegElem('3'),
388        'AA64FpDest2S':  vectorRegElem('0', 'sf', zeroing = True),
389        'AA64FpDest2D':  vectorRegElem('0', 'df', zeroing = True),
390        'AA64FpDest2Q':  vectorRegElem('0', 'tud', zeroing = True)
391    }),
392
393    'AA64FpOp1V0':       vectorReg('op1',
394    {
395        'AA64FpOp1P0V0': vectorRegElem('0'),
396        'AA64FpOp1P1V0': vectorRegElem('1'),
397        'AA64FpOp1P2V0': vectorRegElem('2'),
398        'AA64FpOp1P3V0': vectorRegElem('3'),
399        'AA64FpOp1SV0':  vectorRegElem('0', 'sf', zeroing = True),
400        'AA64FpOp1DV0':  vectorRegElem('0', 'df', zeroing = True),
401        'AA64FpOp1QV0':  vectorRegElem('0', 'tud', zeroing = True)
402    }),
403
404    'AA64FpOp1V1':       vectorReg('op1+1',
405    {
406        'AA64FpOp1P0V1': vectorRegElem('0'),
407        'AA64FpOp1P1V1': vectorRegElem('1'),
408        'AA64FpOp1P2V1': vectorRegElem('2'),
409        'AA64FpOp1P3V1': vectorRegElem('3'),
410        'AA64FpOp1SV1':  vectorRegElem('0', 'sf', zeroing = True),
411        'AA64FpOp1DV1':  vectorRegElem('0', 'df', zeroing = True),
412        'AA64FpOp1QV1':  vectorRegElem('0', 'tud', zeroing = True)
413    }),
414
415    'AA64FpOp1V2':       vectorReg('op1+2',
416    {
417        'AA64FpOp1P0V2': vectorRegElem('0'),
418        'AA64FpOp1P1V2': vectorRegElem('1'),
419        'AA64FpOp1P2V2': vectorRegElem('2'),
420        'AA64FpOp1P3V2': vectorRegElem('3'),
421        'AA64FpOp1SV2':  vectorRegElem('0', 'sf', zeroing = True),
422        'AA64FpOp1DV2':  vectorRegElem('0', 'df', zeroing = True),
423        'AA64FpOp1QV2':  vectorRegElem('0', 'tud', zeroing = True)
424    }),
425
426    'AA64FpOp1V3':       vectorReg('op1+3',
427    {
428        'AA64FpOp1P0V3': vectorRegElem('0'),
429        'AA64FpOp1P1V3': vectorRegElem('1'),
430        'AA64FpOp1P2V3': vectorRegElem('2'),
431        'AA64FpOp1P3V3': vectorRegElem('3'),
432        'AA64FpOp1SV3':  vectorRegElem('0', 'sf', zeroing = True),
433        'AA64FpOp1DV3':  vectorRegElem('0', 'df', zeroing = True),
434        'AA64FpOp1QV3':  vectorRegElem('0', 'tud', zeroing = True)
435    }),
436
437    'AA64FpOp1V0S':       vectorReg('(op1+0)%32',
438    {
439        'AA64FpOp1P0V0S': vectorRegElem('0'),
440        'AA64FpOp1P1V0S': vectorRegElem('1'),
441        'AA64FpOp1P2V0S': vectorRegElem('2'),
442        'AA64FpOp1P3V0S': vectorRegElem('3'),
443        'AA64FpOp1SV0S':  vectorRegElem('0', 'sf', zeroing = True),
444        'AA64FpOp1DV0S':  vectorRegElem('0', 'df', zeroing = True),
445        'AA64FpOp1QV0S':  vectorRegElem('0', 'tud', zeroing = True)
446    }),
447
448    'AA64FpOp1V1S':       vectorReg('(op1+1)%32',
449    {
450        'AA64FpOp1P0V1S': vectorRegElem('0'),
451        'AA64FpOp1P1V1S': vectorRegElem('1'),
452        'AA64FpOp1P2V1S': vectorRegElem('2'),
453        'AA64FpOp1P3V1S': vectorRegElem('3'),
454        'AA64FpOp1SV1S':  vectorRegElem('0', 'sf', zeroing = True),
455        'AA64FpOp1DV1S':  vectorRegElem('0', 'df', zeroing = True),
456        'AA64FpOp1QV1S':  vectorRegElem('0', 'tud', zeroing = True)
457    }),
458
459    'AA64FpOp1V2S':       vectorReg('(op1+2)%32',
460    {
461        'AA64FpOp1P0V2S': vectorRegElem('0'),
462        'AA64FpOp1P1V2S': vectorRegElem('1'),
463        'AA64FpOp1P2V2S': vectorRegElem('2'),
464        'AA64FpOp1P3V2S': vectorRegElem('3'),
465        'AA64FpOp1SV2S':  vectorRegElem('0', 'sf', zeroing = True),
466        'AA64FpOp1DV2S':  vectorRegElem('0', 'df', zeroing = True),
467        'AA64FpOp1QV2S':  vectorRegElem('0', 'tud', zeroing = True)
468    }),
469
470    'AA64FpOp1V3S':       vectorReg('(op1+3)%32',
471    {
472        'AA64FpOp1P0V3S': vectorRegElem('0'),
473        'AA64FpOp1P1V3S': vectorRegElem('1'),
474        'AA64FpOp1P2V3S': vectorRegElem('2'),
475        'AA64FpOp1P3V3S': vectorRegElem('3'),
476        'AA64FpOp1SV3S':  vectorRegElem('0', 'sf', zeroing = True),
477        'AA64FpOp1DV3S':  vectorRegElem('0', 'df', zeroing = True),
478        'AA64FpOp1QV3S':  vectorRegElem('0', 'tud', zeroing = True)
479    }),
480
481    'AA64FpDestV0':       vectorReg('(dest+0)',
482    {
483        'AA64FpDestP0V0': vectorRegElem('0'),
484        'AA64FpDestP1V0': vectorRegElem('1'),
485        'AA64FpDestP2V0': vectorRegElem('2'),
486        'AA64FpDestP3V0': vectorRegElem('3'),
487        'AA64FpDestSV0':  vectorRegElem('0', 'sf', zeroing = True),
488        'AA64FpDestDV0':  vectorRegElem('0', 'df', zeroing = True),
489        'AA64FpDestQV0':  vectorRegElem('0', 'tud', zeroing = True)
490    }),
491
492    'AA64FpDestV1':       vectorReg('(dest+1)',
493    {
494        'AA64FpDestP0V1': vectorRegElem('0'),
495        'AA64FpDestP1V1': vectorRegElem('1'),
496        'AA64FpDestP2V1': vectorRegElem('2'),
497        'AA64FpDestP3V1': vectorRegElem('3'),
498        'AA64FpDestSV1':  vectorRegElem('0', 'sf', zeroing = True),
499        'AA64FpDestDV1':  vectorRegElem('0', 'df', zeroing = True),
500        'AA64FpDestQV1':  vectorRegElem('0', 'tud', zeroing = True)
501    }),
502
503    'AA64FpDestV0L':       vectorReg('(dest+0)%32',
504    {
505        'AA64FpDestP0V0L': vectorRegElem('0'),
506        'AA64FpDestP1V0L': vectorRegElem('1'),
507        'AA64FpDestP2V0L': vectorRegElem('2'),
508        'AA64FpDestP3V0L': vectorRegElem('3'),
509        'AA64FpDestSV0L':  vectorRegElem('0', 'sf', zeroing = True),
510        'AA64FpDestDV0L':  vectorRegElem('0', 'df', zeroing = True),
511        'AA64FpDestQV0L':  vectorRegElem('0', 'tud', zeroing = True)
512    }),
513
514    'AA64FpDestV1L':       vectorReg('(dest+1)%32',
515    {
516        'AA64FpDestP0V1L': vectorRegElem('0'),
517        'AA64FpDestP1V1L': vectorRegElem('1'),
518        'AA64FpDestP2V1L': vectorRegElem('2'),
519        'AA64FpDestP3V1L': vectorRegElem('3'),
520        'AA64FpDestSV1L':  vectorRegElem('0', 'sf', zeroing = True),
521        'AA64FpDestDV1L':  vectorRegElem('0', 'df', zeroing = True),
522        'AA64FpDestQV1L':  vectorRegElem('0', 'tud', zeroing = True)
523    }),
524
525    #Abstracted control reg operands
526    'MiscDest': cntrlReg('dest'),
527    'MiscOp1': cntrlReg('op1'),
528    'MiscNsBankedDest': cntrlNsBankedReg('dest'),
529    'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
530    'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
531    'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
532
533    #Fixed index control regs
534    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
535    'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
536    'Spsr': cntrlRegNC('MISCREG_SPSR'),
537    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
538    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
539    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
540    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
541    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
542    'Cpacr': cntrlReg('MISCREG_CPACR'),
543    'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
544    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
545    'Nsacr': cntrlReg('MISCREG_NSACR'),
546    'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
547    'Hcr': cntrlReg('MISCREG_HCR'),
548    'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
549    'Hdcr': cntrlReg('MISCREG_HDCR'),
550    'Hcptr': cntrlReg('MISCREG_HCPTR'),
551    'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
552    'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
553    'Hstr': cntrlReg('MISCREG_HSTR'),
554    'Scr': cntrlReg('MISCREG_SCR'),
555    'Scr64': cntrlReg('MISCREG_SCR_EL3'),
556    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
557    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
558    'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
559    'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
560
561    #Register fields for microops
562    'URa' : intReg('ura'),
563    'XURa' : intRegX64('ura'),
564    'WURa' : intRegW64('ura'),
565    'IWRa' : intRegIWPC('ura'),
566    'Fa' : vectorElem('ura / 4', 'ura % 4'),
567    'URb' : intReg('urb'),
568    'XURb' : intRegX64('urb'),
569    'URc' : intReg('urc'),
570    'XURc' : intRegX64('urc'),
571
572    #Memory Operand
573    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
574
575    #PCState fields
576    'RawPC': pcStateReg('pc', srtPC),
577    'PC': pcStateReg('instPC', srtPC),
578    'NPC': pcStateReg('instNPC', srtPC),
579    'pNPC': pcStateReg('instNPC', srtEPC),
580    'IWNPC': pcStateReg('instIWNPC', srtPC),
581    'Thumb': pcStateReg('thumb', srtPC),
582    'NextThumb': pcStateReg('nextThumb', srtMode),
583    'NextJazelle': pcStateReg('nextJazelle', srtMode),
584    'NextItState': pcStateReg('nextItstate', srtMode),
585    'Itstate': pcStateReg('itstate', srtMode),
586    'NextAArch64': pcStateReg('nextAArch64', srtMode),
587
588    #Register operands depending on a field in the instruction encoding. These
589    #should be avoided since they may not be portable across different
590    #encodings of the same instruction.
591    'Rd': intReg('RD'),
592    'Rm': intReg('RM'),
593    'Rs': intReg('RS'),
594    'Rn': intReg('RN'),
595    'Rt': intReg('RT')
596}};
597