operands.isa revision 7303
12817Sksewell@umich.edu// -*- mode:c++ -*- 22817Sksewell@umich.edu// Copyright (c) 2010 ARM Limited 32817Sksewell@umich.edu// All rights reserved 42817Sksewell@umich.edu// 52817Sksewell@umich.edu// The license below extends only to copyright in the software and shall 62817Sksewell@umich.edu// not be construed as granting a license to any other intellectual 72817Sksewell@umich.edu// property including but not limited to intellectual property relating 82817Sksewell@umich.edu// to a hardware implementation of the functionality of the software 92817Sksewell@umich.edu// licensed hereunder. You may use the software subject to the license 102817Sksewell@umich.edu// terms below provided that you ensure that this notice is replicated 112817Sksewell@umich.edu// unmodified and in its entirety in all distributions of the software, 122817Sksewell@umich.edu// modified or unmodified, in source code or in binary form. 132817Sksewell@umich.edu// 142817Sksewell@umich.edu// Copyright (c) 2007-2008 The Florida State University 152817Sksewell@umich.edu// All rights reserved. 162817Sksewell@umich.edu// 172817Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu// modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu// this software without specific prior written permission. 272817Sksewell@umich.edu// 282817Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294202Sbinkertn@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334202Sbinkertn@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355192Ssaidi@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365192Ssaidi@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375192Ssaidi@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385192Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395192Ssaidi@eecs.umich.edu// 404202Sbinkertn@umich.edu// Authors: Stephen Hines 414486Sbinkertn@umich.edu 424486Sbinkertn@umich.edudef operand_types {{ 434486Sbinkertn@umich.edu 'sb' : ('signed int', 8), 444486Sbinkertn@umich.edu 'ub' : ('unsigned int', 8), 454202Sbinkertn@umich.edu 'sh' : ('signed int', 16), 464202Sbinkertn@umich.edu 'uh' : ('unsigned int', 16), 474202Sbinkertn@umich.edu 'sw' : ('signed int', 32), 484202Sbinkertn@umich.edu 'uw' : ('unsigned int', 32), 495597Sgblack@eecs.umich.edu 'ud' : ('unsigned int', 64), 504202Sbinkertn@umich.edu 'sf' : ('float', 32), 515597Sgblack@eecs.umich.edu 'df' : ('float', 64) 524202Sbinkertn@umich.edu}}; 534202Sbinkertn@umich.edu 544202Sbinkertn@umich.edulet {{ 554202Sbinkertn@umich.edu maybePCRead = ''' 564202Sbinkertn@umich.edu ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : 574202Sbinkertn@umich.edu xc->%(func)s(this, %(op_idx)s)) 584202Sbinkertn@umich.edu ''' 594202Sbinkertn@umich.edu maybeAlignedPCRead = ''' 604202Sbinkertn@umich.edu ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) : 614202Sbinkertn@umich.edu xc->%(func)s(this, %(op_idx)s)) 624202Sbinkertn@umich.edu ''' 634202Sbinkertn@umich.edu maybePCWrite = ''' 644202Sbinkertn@umich.edu ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 655597Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 662817Sksewell@umich.edu ''' 675192Ssaidi@eecs.umich.edu maybeIWPCWrite = ''' 685192Ssaidi@eecs.umich.edu ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) : 695192Ssaidi@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 705192Ssaidi@eecs.umich.edu ''' 715192Ssaidi@eecs.umich.edu maybeAIWPCWrite = ''' 725192Ssaidi@eecs.umich.edu if (%(reg_idx)s == PCReg) { 735192Ssaidi@eecs.umich.edu bool thumb = THUMB; 745192Ssaidi@eecs.umich.edu if (thumb) { 755192Ssaidi@eecs.umich.edu setNextPC(xc, %(final_val)s); 765192Ssaidi@eecs.umich.edu } else { 775192Ssaidi@eecs.umich.edu setIWNextPC(xc, %(final_val)s); 785192Ssaidi@eecs.umich.edu } 795192Ssaidi@eecs.umich.edu } else { 805192Ssaidi@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s); 814202Sbinkertn@umich.edu } 824497Sbinkertn@umich.edu ''' 834202Sbinkertn@umich.edu 84 readNPC = 'xc->readNextPC() & ~PcModeMask' 85 writeNPC = 'setNextPC(xc, %(final_val)s)' 86 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 87 forceNPC = 'xc->setNextPC(%(final_val)s)' 88}}; 89 90def operands {{ 91 #Abstracted integer reg operands 92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 93 maybePCRead, maybePCWrite), 94 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, 95 maybePCRead, maybePCWrite), 96 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, 97 maybePCRead, maybePCWrite), 98 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 99 maybePCRead, maybeIWPCWrite), 100 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 101 maybePCRead, maybeAIWPCWrite), 102 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2), 103 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0, 104 maybeAlignedPCRead, maybePCWrite), 105 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 106 maybePCRead, maybePCWrite), 107 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, 108 maybePCRead, maybePCWrite), 109 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 110 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, 111 maybePCRead, maybePCWrite), 112 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2, 113 maybePCRead, maybePCWrite), 114 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2, 115 maybePCRead, maybePCWrite), 116 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2, 117 maybePCRead, maybePCWrite), 118 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2, 119 maybePCRead, maybePCWrite), 120 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2, 121 maybePCRead, maybePCWrite), 122 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2, 123 maybePCRead, maybePCWrite), 124 #General Purpose Integer Reg Operands 125 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite), 126 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 127 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite), 128 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite), 129 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2), 130 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2), 131 132 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), 133 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), 134 135 #Register fields for microops 136 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), 137 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, 138 maybePCRead, maybeIWPCWrite), 139 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 140 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite), 141 142 #General Purpose Floating Point Reg Operands 143 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), 144 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), 145 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), 146 147 #Memory Operand 148 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 149 150 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), 151 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 152 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 153 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), 154 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2), 155 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 156 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 157 readNPC, writeNPC), 158 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 159 readNPC, forceNPC), 160 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 161 readNPC, writeIWNPC), 162}}; 163