operands.isa revision 7241
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 27091Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 37091Sgblack@eecs.umich.edu// All rights reserved 47091Sgblack@eecs.umich.edu// 57091Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 67091Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 77091Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 87091Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 97091Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 107091Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 117091Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 127091Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 137091Sgblack@eecs.umich.edu// 146019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu// All rights reserved. 166019Shines@cs.fsu.edu// 176019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu// this software without specific prior written permission. 276019Shines@cs.fsu.edu// 286019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu// 406019Shines@cs.fsu.edu// Authors: Stephen Hines 416019Shines@cs.fsu.edu 426019Shines@cs.fsu.edudef operand_types {{ 436019Shines@cs.fsu.edu 'sb' : ('signed int', 8), 446019Shines@cs.fsu.edu 'ub' : ('unsigned int', 8), 456019Shines@cs.fsu.edu 'sh' : ('signed int', 16), 466019Shines@cs.fsu.edu 'uh' : ('unsigned int', 16), 476019Shines@cs.fsu.edu 'sw' : ('signed int', 32), 486019Shines@cs.fsu.edu 'uw' : ('unsigned int', 32), 496019Shines@cs.fsu.edu 'ud' : ('unsigned int', 64), 506019Shines@cs.fsu.edu 'sf' : ('float', 32), 516019Shines@cs.fsu.edu 'df' : ('float', 64) 526019Shines@cs.fsu.edu}}; 536019Shines@cs.fsu.edu 546312Sgblack@eecs.umich.edulet {{ 556312Sgblack@eecs.umich.edu maybePCRead = ''' 567147Sgblack@eecs.umich.edu ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : 576312Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s)) 586312Sgblack@eecs.umich.edu ''' 597186Sgblack@eecs.umich.edu maybeAlignedPCRead = ''' 607186Sgblack@eecs.umich.edu ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) : 617186Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s)) 627186Sgblack@eecs.umich.edu ''' 636312Sgblack@eecs.umich.edu maybePCWrite = ''' 647093Sgblack@eecs.umich.edu ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 656312Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 666312Sgblack@eecs.umich.edu ''' 677148Sgblack@eecs.umich.edu maybeIWPCWrite = ''' 687148Sgblack@eecs.umich.edu ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) : 697148Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 707148Sgblack@eecs.umich.edu ''' 717184Sgblack@eecs.umich.edu maybeAIWPCWrite = ''' 727184Sgblack@eecs.umich.edu if (%(reg_idx)s == PCReg) { 737184Sgblack@eecs.umich.edu if (xc->readPC() & (ULL(1) << PcTBitShift)) { 747184Sgblack@eecs.umich.edu setIWNextPC(xc, %(final_val)s); 757184Sgblack@eecs.umich.edu } else { 767184Sgblack@eecs.umich.edu setNextPC(xc, %(final_val)s); 777184Sgblack@eecs.umich.edu } 787184Sgblack@eecs.umich.edu } else { 797184Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s); 807184Sgblack@eecs.umich.edu } 817184Sgblack@eecs.umich.edu ''' 827093Sgblack@eecs.umich.edu 837093Sgblack@eecs.umich.edu readNPC = 'xc->readNextPC() & ~PcModeMask' 847093Sgblack@eecs.umich.edu writeNPC = 'setNextPC(xc, %(final_val)s)' 857148Sgblack@eecs.umich.edu writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 867151Sgblack@eecs.umich.edu forceNPC = 'xc->setNextPC(%(final_val)s)' 876312Sgblack@eecs.umich.edu}}; 886312Sgblack@eecs.umich.edu 896019Shines@cs.fsu.edudef operands {{ 907119Sgblack@eecs.umich.edu #Abstracted integer reg operands 917119Sgblack@eecs.umich.edu 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 927119Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 937148Sgblack@eecs.umich.edu 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 947148Sgblack@eecs.umich.edu maybePCRead, maybeIWPCWrite), 957148Sgblack@eecs.umich.edu 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 967184Sgblack@eecs.umich.edu maybePCRead, maybeAIWPCWrite), 977119Sgblack@eecs.umich.edu 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 987186Sgblack@eecs.umich.edu maybeAlignedPCRead, maybePCWrite), 997119Sgblack@eecs.umich.edu 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 1007119Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1017137Sgblack@eecs.umich.edu 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 1027137Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1037137Sgblack@eecs.umich.edu 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 1047137Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1057241Sgblack@eecs.umich.edu 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4, 1067241Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1077137Sgblack@eecs.umich.edu 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 1087137Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1097160Sgblack@eecs.umich.edu 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, 1107160Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1117160Sgblack@eecs.umich.edu 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, 1127160Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1137160Sgblack@eecs.umich.edu 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, 1147160Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1157160Sgblack@eecs.umich.edu 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, 1167160Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 1176019Shines@cs.fsu.edu #General Purpose Integer Reg Operands 1186312Sgblack@eecs.umich.edu 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 1196312Sgblack@eecs.umich.edu 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 1206312Sgblack@eecs.umich.edu 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 1216312Sgblack@eecs.umich.edu 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 1226393Ssaidi@eecs.umich.edu 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 1236741Sgblack@eecs.umich.edu 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 1246019Shines@cs.fsu.edu 1256299Sgblack@eecs.umich.edu #Destination register for load/store double instructions 1266312Sgblack@eecs.umich.edu 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 1276312Sgblack@eecs.umich.edu 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 1286299Sgblack@eecs.umich.edu 1296721Sgblack@eecs.umich.edu 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 1307091Sgblack@eecs.umich.edu 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 1316019Shines@cs.fsu.edu 1326308Sgblack@eecs.umich.edu #Register fields for microops 1336312Sgblack@eecs.umich.edu 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 1347207Sgblack@eecs.umich.edu 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, 1357207Sgblack@eecs.umich.edu maybePCRead, maybeIWPCWrite), 1367173Sgblack@eecs.umich.edu 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 1376312Sgblack@eecs.umich.edu 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 1386308Sgblack@eecs.umich.edu 1396019Shines@cs.fsu.edu #General Purpose Floating Point Reg Operands 1406299Sgblack@eecs.umich.edu 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 1416299Sgblack@eecs.umich.edu 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 1426299Sgblack@eecs.umich.edu 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 1436019Shines@cs.fsu.edu 1446019Shines@cs.fsu.edu #Memory Operand 1456299Sgblack@eecs.umich.edu 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 1466019Shines@cs.fsu.edu 1477093Sgblack@eecs.umich.edu 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 1487091Sgblack@eecs.umich.edu 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 1497091Sgblack@eecs.umich.edu 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 1507091Sgblack@eecs.umich.edu 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 1517091Sgblack@eecs.umich.edu 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 1527091Sgblack@eecs.umich.edu 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 1537114Sgblack@eecs.umich.edu 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1547093Sgblack@eecs.umich.edu readNPC, writeNPC), 1557151Sgblack@eecs.umich.edu 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1567151Sgblack@eecs.umich.edu readNPC, forceNPC), 1577148Sgblack@eecs.umich.edu 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1587148Sgblack@eecs.umich.edu readNPC, writeIWNPC), 1596019Shines@cs.fsu.edu}}; 160