operands.isa revision 7137
16019Shines@cs.fsu.edu// -*- mode:c++ -*- 27091Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 37091Sgblack@eecs.umich.edu// All rights reserved 47091Sgblack@eecs.umich.edu// 57091Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 67091Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 77091Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 87091Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 97091Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 107091Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 117091Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 127091Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 137091Sgblack@eecs.umich.edu// 146019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu// All rights reserved. 166019Shines@cs.fsu.edu// 176019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu// this software without specific prior written permission. 276019Shines@cs.fsu.edu// 286019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu// 406019Shines@cs.fsu.edu// Authors: Stephen Hines 416019Shines@cs.fsu.edu 426019Shines@cs.fsu.edudef operand_types {{ 436019Shines@cs.fsu.edu 'sb' : ('signed int', 8), 446019Shines@cs.fsu.edu 'ub' : ('unsigned int', 8), 456019Shines@cs.fsu.edu 'sh' : ('signed int', 16), 466019Shines@cs.fsu.edu 'uh' : ('unsigned int', 16), 476019Shines@cs.fsu.edu 'sw' : ('signed int', 32), 486019Shines@cs.fsu.edu 'uw' : ('unsigned int', 32), 496019Shines@cs.fsu.edu 'ud' : ('unsigned int', 64), 506019Shines@cs.fsu.edu 'sf' : ('float', 32), 516019Shines@cs.fsu.edu 'df' : ('float', 64) 526019Shines@cs.fsu.edu}}; 536019Shines@cs.fsu.edu 546312Sgblack@eecs.umich.edulet {{ 556312Sgblack@eecs.umich.edu maybePCRead = ''' 567093Sgblack@eecs.umich.edu ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) : 576312Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s)) 586312Sgblack@eecs.umich.edu ''' 596312Sgblack@eecs.umich.edu maybePCWrite = ''' 607093Sgblack@eecs.umich.edu ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 616312Sgblack@eecs.umich.edu xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 626312Sgblack@eecs.umich.edu ''' 637093Sgblack@eecs.umich.edu 647114Sgblack@eecs.umich.edu readPC = 'xc->readPC() & ~PcModeMask' 657114Sgblack@eecs.umich.edu writePC = 'setPC(xc, %(final_val)s)' 667114Sgblack@eecs.umich.edu 677093Sgblack@eecs.umich.edu readNPC = 'xc->readNextPC() & ~PcModeMask' 687093Sgblack@eecs.umich.edu writeNPC = 'setNextPC(xc, %(final_val)s)' 696312Sgblack@eecs.umich.edu}}; 706312Sgblack@eecs.umich.edu 716019Shines@cs.fsu.edudef operands {{ 727119Sgblack@eecs.umich.edu #Abstracted integer reg operands 737119Sgblack@eecs.umich.edu 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 747119Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 757119Sgblack@eecs.umich.edu 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 767119Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 777119Sgblack@eecs.umich.edu 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 787119Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 797137Sgblack@eecs.umich.edu 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 807137Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 817137Sgblack@eecs.umich.edu 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 827137Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 837137Sgblack@eecs.umich.edu 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 847137Sgblack@eecs.umich.edu maybePCRead, maybePCWrite), 856019Shines@cs.fsu.edu #General Purpose Integer Reg Operands 866312Sgblack@eecs.umich.edu 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 876312Sgblack@eecs.umich.edu 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 886312Sgblack@eecs.umich.edu 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 896312Sgblack@eecs.umich.edu 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 906393Ssaidi@eecs.umich.edu 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 916741Sgblack@eecs.umich.edu 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 926019Shines@cs.fsu.edu 936299Sgblack@eecs.umich.edu #Destination register for load/store double instructions 946312Sgblack@eecs.umich.edu 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 956312Sgblack@eecs.umich.edu 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 966299Sgblack@eecs.umich.edu 976721Sgblack@eecs.umich.edu 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), 986721Sgblack@eecs.umich.edu 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), 996721Sgblack@eecs.umich.edu 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 1007091Sgblack@eecs.umich.edu 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 1016019Shines@cs.fsu.edu 1026308Sgblack@eecs.umich.edu #Register fields for microops 1036312Sgblack@eecs.umich.edu 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 1046312Sgblack@eecs.umich.edu 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 1056308Sgblack@eecs.umich.edu 1066019Shines@cs.fsu.edu #General Purpose Floating Point Reg Operands 1076299Sgblack@eecs.umich.edu 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 1086299Sgblack@eecs.umich.edu 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 1096299Sgblack@eecs.umich.edu 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 1106019Shines@cs.fsu.edu 1116019Shines@cs.fsu.edu #Memory Operand 1126299Sgblack@eecs.umich.edu 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 1136019Shines@cs.fsu.edu 1147093Sgblack@eecs.umich.edu 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 1157091Sgblack@eecs.umich.edu 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 1167091Sgblack@eecs.umich.edu 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 1177091Sgblack@eecs.umich.edu 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 1187091Sgblack@eecs.umich.edu 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 1197091Sgblack@eecs.umich.edu 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 1207114Sgblack@eecs.umich.edu 'PC': ('PC', 'ud', None, (None, None, 'IsControl'), 50, 1217114Sgblack@eecs.umich.edu readPC, writePC), 1227114Sgblack@eecs.umich.edu 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 1237093Sgblack@eecs.umich.edu readNPC, writeNPC), 1246019Shines@cs.fsu.edu}}; 125