operands.isa revision 13603
1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// 14// Copyright (c) 2007-2008 The Florida State University 15// All rights reserved. 16// 17// Redistribution and use in source and binary forms, with or without 18// modification, are permitted provided that the following conditions are 19// met: redistributions of source code must retain the above copyright 20// notice, this list of conditions and the following disclaimer; 21// redistributions in binary form must reproduce the above copyright 22// notice, this list of conditions and the following disclaimer in the 23// documentation and/or other materials provided with the distribution; 24// neither the name of the copyright holders nor the names of its 25// contributors may be used to endorse or promote products derived from 26// this software without specific prior written permission. 27// 28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39// 40// Authors: Stephen Hines 41 42def operand_types {{ 43 'sb' : 'int8_t', 44 'ub' : 'uint8_t', 45 'sh' : 'int16_t', 46 'uh' : 'uint16_t', 47 'sw' : 'int32_t', 48 'uw' : 'uint32_t', 49 'ud' : 'uint64_t', 50 'tud' : 'std::array<uint64_t, 2>', 51 'sf' : 'float', 52 'df' : 'double', 53 'vc' : 'TheISA::VecRegContainer', 54 # For operations that are implemented as a template 55 'x' : 'TPElem', 56}}; 57 58let {{ 59 maybePCRead = ''' 60 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s)) 61 ''' 62 maybeAlignedPCRead = ''' 63 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) : 64 xc->%(func)s(this, %(op_idx)s)) 65 ''' 66 maybePCWrite = ''' 67 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 68 xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 69 ''' 70 maybeIWPCWrite = ''' 71 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) : 72 xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 73 ''' 74 maybeAIWPCWrite = ''' 75 if (%(reg_idx)s == PCReg) { 76 bool thumb = THUMB; 77 if (thumb) { 78 setNextPC(xc, %(final_val)s); 79 } else { 80 setIWNextPC(xc, %(final_val)s); 81 } 82 } else { 83 xc->%(func)s(this, %(op_idx)s, %(final_val)s); 84 } 85 ''' 86 aarch64Read = ''' 87 ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth)) 88 ''' 89 aarch64Write = ''' 90 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth)) 91 ''' 92 aarchX64Read = ''' 93 ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32)) 94 ''' 95 aarchX64Write = ''' 96 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32)) 97 ''' 98 aarchW64Read = ''' 99 ((xc->%(func)s(this, %(op_idx)s)) & mask(32)) 100 ''' 101 aarchW64Write = ''' 102 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32)) 103 ''' 104 cntrlNsBankedWrite = ''' 105 xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s) 106 ''' 107 108 cntrlNsBankedRead = ''' 109 xc->readMiscReg(snsBankedIndex(op1, xc->tcBase())) 110 ''' 111 112 #PCState operands need to have a sorting index (the number at the end) 113 #less than all the integer registers which might update the PC. That way 114 #if the flag bits of the pc state are updated and a branch happens through 115 #R15, the updates are layered properly and the R15 update isn't lost. 116 srtNormal = 5 117 srtCpsr = 4 118 srtBase = 3 119 srtPC = 2 120 srtMode = 1 121 srtEPC = 0 122 123 def vectorElem(idx, elem): 124 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal) 125 126 def vectorReg(idx, elems = None): 127 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal) 128 129 def vectorRegElem(elem, ext = 'sf', zeroing = False): 130 return (elem, ext, zeroing) 131 132 def floatReg(idx): 133 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal) 134 135 def intReg(idx): 136 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 137 maybePCRead, maybePCWrite) 138 139 def intReg64(idx): 140 return ('IntReg', 'ud', idx, 'IsInteger', srtNormal, 141 aarch64Read, aarch64Write) 142 143 def intRegX64(idx, id = srtNormal): 144 return ('IntReg', 'ud', idx, 'IsInteger', id, 145 aarchX64Read, aarchX64Write) 146 147 def intRegW64(idx, id = srtNormal): 148 return ('IntReg', 'ud', idx, 'IsInteger', id, 149 aarchW64Read, aarchW64Write) 150 151 def intRegNPC(idx): 152 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal) 153 154 def intRegAPC(idx, id = srtNormal): 155 return ('IntReg', 'uw', idx, 'IsInteger', id, 156 maybeAlignedPCRead, maybePCWrite) 157 158 def intRegIWPC(idx): 159 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 160 maybePCRead, maybeIWPCWrite) 161 162 def intRegAIWPC(idx): 163 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 164 maybePCRead, maybeAIWPCWrite) 165 166 def ccReg(idx): 167 return ('CCReg', 'uw', idx, None, srtNormal) 168 169 def cntrlReg(idx, id = srtNormal, type = 'uw'): 170 return ('ControlReg', type, idx, None, id) 171 172 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'): 173 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite) 174 175 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'): 176 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite) 177 178 def cntrlRegNC(idx, id = srtNormal, type = 'uw'): 179 return ('ControlReg', type, idx, None, id) 180 181 def pcStateReg(idx, id): 182 return ('PCState', 'ud', idx, (None, None, 'IsControl'), id) 183}}; 184 185def operands {{ 186 #Abstracted integer reg operands 187 'Dest': intReg('dest'), 188 'Dest64': intReg64('dest'), 189 'XDest': intRegX64('dest'), 190 'WDest': intRegW64('dest'), 191 'IWDest': intRegIWPC('dest'), 192 'AIWDest': intRegAIWPC('dest'), 193 'Dest2': intReg('dest2'), 194 'XDest2': intRegX64('dest2'), 195 'IWDest2': intRegIWPC('dest2'), 196 'Result': intReg('result'), 197 'XResult': intRegX64('result'), 198 'XBase': intRegX64('base', id = srtBase), 199 'Base': intRegAPC('base', id = srtBase), 200 'XOffset': intRegX64('offset'), 201 'Index': intReg('index'), 202 'Shift': intReg('shift'), 203 'Op1': intReg('op1'), 204 'Op2': intReg('op2'), 205 'Op3': intReg('op3'), 206 'Op164': intReg64('op1'), 207 'Op264': intReg64('op2'), 208 'Op364': intReg64('op3'), 209 'XOp1': intRegX64('op1'), 210 'XOp2': intRegX64('op2'), 211 'XOp3': intRegX64('op3'), 212 'WOp1': intRegW64('op1'), 213 'WOp2': intRegW64('op2'), 214 'WOp3': intRegW64('op3'), 215 'Reg0': intReg('reg0'), 216 'Reg1': intReg('reg1'), 217 'Reg2': intReg('reg2'), 218 'Reg3': intReg('reg3'), 219 220 #Fixed index integer reg operands 221 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'), 222 'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'), 223 'LR': intRegNPC('INTREG_LR'), 224 'XLR': intRegX64('INTREG_X30'), 225 'R7': intRegNPC('7'), 226 # First four arguments are passed in registers 227 'R0': intRegNPC('0'), 228 'R1': intRegNPC('1'), 229 'R2': intRegNPC('2'), 230 'R3': intRegNPC('3'), 231 'X0': intRegX64('0'), 232 'X1': intRegX64('1'), 233 'X2': intRegX64('2'), 234 'X3': intRegX64('3'), 235 236 # Condition code registers 237 'CondCodesNZ': ccReg('CCREG_NZ'), 238 'CondCodesC': ccReg('CCREG_C'), 239 'CondCodesV': ccReg('CCREG_V'), 240 'CondCodesGE': ccReg('CCREG_GE'), 241 'OptCondCodesNZ': ccReg( 242 '''((condCode == COND_AL || condCode == COND_UC || 243 condCode == COND_CC || condCode == COND_CS || 244 condCode == COND_VS || condCode == COND_VC) ? 245 CCREG_ZERO : CCREG_NZ)'''), 246 'OptCondCodesC': ccReg( 247 '''((condCode == COND_HI || condCode == COND_LS || 248 condCode == COND_CS || condCode == COND_CC) ? 249 CCREG_C : CCREG_ZERO)'''), 250 'OptShiftRmCondCodesC': ccReg( 251 '''((condCode == COND_HI || condCode == COND_LS || 252 condCode == COND_CS || condCode == COND_CC || 253 shiftType == ROR) ? 254 CCREG_C : CCREG_ZERO)'''), 255 'OptCondCodesV': ccReg( 256 '''((condCode == COND_VS || condCode == COND_VC || 257 condCode == COND_GE || condCode == COND_LT || 258 condCode == COND_GT || condCode == COND_LE) ? 259 CCREG_V : CCREG_ZERO)'''), 260 'FpCondCodes': ccReg('CCREG_FP'), 261 262 #Abstracted floating point reg operands 263 'FpDest': vectorElem('dest / 4', 'dest % 4'), 264 'FpDestP0': vectorElem('dest / 4', '(dest % 4) + 0'), 265 'FpDestP1': vectorElem('dest / 4', '(dest % 4) + 1'), 266 'FpDestP2': vectorElem('dest / 4', '(dest % 4) + 2'), 267 'FpDestP3': vectorElem('dest / 4', '(dest % 4) + 3'), 268 'FpDestP4': vectorElem('(dest / 4) + 1', '(dest % 4) + 0'), 269 'FpDestP5': vectorElem('(dest / 4) + 1', '(dest % 4) + 1'), 270 'FpDestP6': vectorElem('(dest / 4) + 1', '(dest % 4) + 2'), 271 'FpDestP7': vectorElem('(dest / 4) + 1', '(dest % 4) + 3'), 272 273 'FpDestS0P0': vectorElem( 274 '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'), 275 'FpDestS0P1': vectorElem( 276 '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'), 277 'FpDestS1P0': vectorElem( 278 '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'), 279 'FpDestS1P1': vectorElem( 280 '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'), 281 'FpDestS2P0': vectorElem( 282 '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'), 283 'FpDestS2P1': vectorElem( 284 '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'), 285 'FpDestS3P0': vectorElem( 286 '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'), 287 'FpDestS3P1': vectorElem( 288 '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'), 289 290 'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'), 291 'FpDest2P0': vectorElem('dest2 / 4', '(dest2 % 4) + 0'), 292 'FpDest2P1': vectorElem('dest2 / 4', '(dest2 % 4) + 1'), 293 'FpDest2P2': vectorElem('dest2 / 4', '(dest2 % 4) + 2'), 294 'FpDest2P3': vectorElem('dest2 / 4', '(dest2 % 4) + 3'), 295 296 'FpOp1': vectorElem('op1 / 4', 'op1 % 4'), 297 'FpOp1P0': vectorElem('op1 / 4', '(op1 % 4) + 0'), 298 'FpOp1P1': vectorElem('op1 / 4', '(op1 % 4) + 1'), 299 'FpOp1P2': vectorElem('op1 / 4', '(op1 % 4) + 2'), 300 'FpOp1P3': vectorElem('op1 / 4', '(op1 % 4) + 3'), 301 'FpOp1P4': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 0'), 302 'FpOp1P5': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 1'), 303 'FpOp1P6': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 2'), 304 'FpOp1P7': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 3'), 305 306 'FpOp1S0P0': vectorElem( 307 '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'), 308 'FpOp1S0P1': vectorElem( 309 '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'), 310 'FpOp1S1P0': vectorElem( 311 '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'), 312 'FpOp1S1P1': vectorElem( 313 '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'), 314 'FpOp1S2P0': vectorElem( 315 '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'), 316 'FpOp1S2P1': vectorElem( 317 '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'), 318 'FpOp1S3P0': vectorElem( 319 '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'), 320 'FpOp1S3P1': vectorElem( 321 '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'), 322 323 'FpOp2': vectorElem('op2 / 4', 'op2 % 4'), 324 'FpOp2P0': vectorElem('op2 / 4', '(op2 % 4) + 0'), 325 'FpOp2P1': vectorElem('op2 / 4', '(op2 % 4) + 1'), 326 'FpOp2P2': vectorElem('op2 / 4', '(op2 % 4) + 2'), 327 'FpOp2P3': vectorElem('op2 / 4', '(op2 % 4) + 3'), 328 329 # Create AArch64 unpacked view of the FP registers 330 # Name ::= 'AA64Vec' OpSpec [LaneSpec] 331 # OpSpec ::= IOSpec [Index] [Plus] 332 # IOSpec ::= 'S' | 'D' 333 # Index ::= '0' | ... | '9' 334 # Plus ::= [PlusAmount] ['l'] 335 # PlusAmount ::= 'p' [PlusAmount] 336 # LaneSpec ::= 'L' Index 337 # 338 # All the constituents are hierarchically defined as part of the Vector 339 # Register they belong to 340 341 'AA64FpOp1': vectorReg('op1', 342 { 343 'AA64FpOp1P0': vectorRegElem('0'), 344 'AA64FpOp1P1': vectorRegElem('1'), 345 'AA64FpOp1P2': vectorRegElem('2'), 346 'AA64FpOp1P3': vectorRegElem('3'), 347 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True), 348 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True), 349 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True) 350 }), 351 352 'AA64FpOp2': vectorReg('op2', 353 { 354 'AA64FpOp2P0': vectorRegElem('0'), 355 'AA64FpOp2P1': vectorRegElem('1'), 356 'AA64FpOp2P2': vectorRegElem('2'), 357 'AA64FpOp2P3': vectorRegElem('3'), 358 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True), 359 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True), 360 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True) 361 }), 362 363 'AA64FpOp3': vectorReg('op3', 364 { 365 'AA64FpOp3P0': vectorRegElem('0'), 366 'AA64FpOp3P1': vectorRegElem('1'), 367 'AA64FpOp3P2': vectorRegElem('2'), 368 'AA64FpOp3P3': vectorRegElem('3'), 369 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True), 370 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True), 371 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True) 372 }), 373 374 'AA64FpDest': vectorReg('dest', 375 { 376 'AA64FpDestP0': vectorRegElem('0'), 377 'AA64FpDestP1': vectorRegElem('1'), 378 'AA64FpDestP2': vectorRegElem('2'), 379 'AA64FpDestP3': vectorRegElem('3'), 380 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True), 381 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True), 382 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True) 383 }), 384 385 'AA64FpDest2': vectorReg('dest2', 386 { 387 'AA64FpDest2P0': vectorRegElem('0'), 388 'AA64FpDest2P1': vectorRegElem('1'), 389 'AA64FpDest2P2': vectorRegElem('2'), 390 'AA64FpDest2P3': vectorRegElem('3'), 391 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True), 392 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True), 393 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True) 394 }), 395 396 'AA64FpOp1V0': vectorReg('op1', 397 { 398 'AA64FpOp1P0V0': vectorRegElem('0'), 399 'AA64FpOp1P1V0': vectorRegElem('1'), 400 'AA64FpOp1P2V0': vectorRegElem('2'), 401 'AA64FpOp1P3V0': vectorRegElem('3'), 402 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True), 403 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True), 404 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True) 405 }), 406 407 'AA64FpOp1V1': vectorReg('op1+1', 408 { 409 'AA64FpOp1P0V1': vectorRegElem('0'), 410 'AA64FpOp1P1V1': vectorRegElem('1'), 411 'AA64FpOp1P2V1': vectorRegElem('2'), 412 'AA64FpOp1P3V1': vectorRegElem('3'), 413 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True), 414 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True), 415 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True) 416 }), 417 418 'AA64FpOp1V2': vectorReg('op1+2', 419 { 420 'AA64FpOp1P0V2': vectorRegElem('0'), 421 'AA64FpOp1P1V2': vectorRegElem('1'), 422 'AA64FpOp1P2V2': vectorRegElem('2'), 423 'AA64FpOp1P3V2': vectorRegElem('3'), 424 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True), 425 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True), 426 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True) 427 }), 428 429 'AA64FpOp1V3': vectorReg('op1+3', 430 { 431 'AA64FpOp1P0V3': vectorRegElem('0'), 432 'AA64FpOp1P1V3': vectorRegElem('1'), 433 'AA64FpOp1P2V3': vectorRegElem('2'), 434 'AA64FpOp1P3V3': vectorRegElem('3'), 435 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True), 436 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True), 437 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True) 438 }), 439 440 'AA64FpOp1V0S': vectorReg('(op1+0)%32', 441 { 442 'AA64FpOp1P0V0S': vectorRegElem('0'), 443 'AA64FpOp1P1V0S': vectorRegElem('1'), 444 'AA64FpOp1P2V0S': vectorRegElem('2'), 445 'AA64FpOp1P3V0S': vectorRegElem('3'), 446 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True), 447 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True), 448 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True) 449 }), 450 451 'AA64FpOp1V1S': vectorReg('(op1+1)%32', 452 { 453 'AA64FpOp1P0V1S': vectorRegElem('0'), 454 'AA64FpOp1P1V1S': vectorRegElem('1'), 455 'AA64FpOp1P2V1S': vectorRegElem('2'), 456 'AA64FpOp1P3V1S': vectorRegElem('3'), 457 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True), 458 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True), 459 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True) 460 }), 461 462 'AA64FpOp1V2S': vectorReg('(op1+2)%32', 463 { 464 'AA64FpOp1P0V2S': vectorRegElem('0'), 465 'AA64FpOp1P1V2S': vectorRegElem('1'), 466 'AA64FpOp1P2V2S': vectorRegElem('2'), 467 'AA64FpOp1P3V2S': vectorRegElem('3'), 468 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True), 469 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True), 470 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True) 471 }), 472 473 'AA64FpOp1V3S': vectorReg('(op1+3)%32', 474 { 475 'AA64FpOp1P0V3S': vectorRegElem('0'), 476 'AA64FpOp1P1V3S': vectorRegElem('1'), 477 'AA64FpOp1P2V3S': vectorRegElem('2'), 478 'AA64FpOp1P3V3S': vectorRegElem('3'), 479 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True), 480 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True), 481 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True) 482 }), 483 484 'AA64FpDestV0': vectorReg('(dest+0)', 485 { 486 'AA64FpDestP0V0': vectorRegElem('0'), 487 'AA64FpDestP1V0': vectorRegElem('1'), 488 'AA64FpDestP2V0': vectorRegElem('2'), 489 'AA64FpDestP3V0': vectorRegElem('3'), 490 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True), 491 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True), 492 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True) 493 }), 494 495 'AA64FpDestV1': vectorReg('(dest+1)', 496 { 497 'AA64FpDestP0V1': vectorRegElem('0'), 498 'AA64FpDestP1V1': vectorRegElem('1'), 499 'AA64FpDestP2V1': vectorRegElem('2'), 500 'AA64FpDestP3V1': vectorRegElem('3'), 501 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True), 502 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True), 503 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True) 504 }), 505 506 'AA64FpDestV0L': vectorReg('(dest+0)%32', 507 { 508 'AA64FpDestP0V0L': vectorRegElem('0'), 509 'AA64FpDestP1V0L': vectorRegElem('1'), 510 'AA64FpDestP2V0L': vectorRegElem('2'), 511 'AA64FpDestP3V0L': vectorRegElem('3'), 512 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True), 513 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True), 514 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True) 515 }), 516 517 'AA64FpDestV1L': vectorReg('(dest+1)%32', 518 { 519 'AA64FpDestP0V1L': vectorRegElem('0'), 520 'AA64FpDestP1V1L': vectorRegElem('1'), 521 'AA64FpDestP2V1L': vectorRegElem('2'), 522 'AA64FpDestP3V1L': vectorRegElem('3'), 523 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True), 524 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True), 525 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True) 526 }), 527 528 #Abstracted control reg operands 529 'MiscDest': cntrlReg('dest'), 530 'MiscOp1': cntrlReg('op1'), 531 'MiscNsBankedDest': cntrlNsBankedReg('dest'), 532 'MiscNsBankedOp1': cntrlNsBankedReg('op1'), 533 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'), 534 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'), 535 536 #Fixed index control regs 537 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), 538 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr), 539 'Spsr': cntrlRegNC('MISCREG_SPSR'), 540 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 541 'Fpsid': cntrlRegNC('MISCREG_FPSID'), 542 'Fpscr': cntrlRegNC('MISCREG_FPSCR'), 543 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'), 544 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'), 545 'Cpacr': cntrlReg('MISCREG_CPACR'), 546 'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'), 547 'Fpexc': cntrlRegNC('MISCREG_FPEXC'), 548 'Nsacr': cntrlReg('MISCREG_NSACR'), 549 'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'), 550 'Hcr': cntrlReg('MISCREG_HCR'), 551 'Hcr64': cntrlReg('MISCREG_HCR_EL2'), 552 'Hdcr': cntrlReg('MISCREG_HDCR'), 553 'Hcptr': cntrlReg('MISCREG_HCPTR'), 554 'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'), 555 'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'), 556 'Hstr': cntrlReg('MISCREG_HSTR'), 557 'Scr': cntrlReg('MISCREG_SCR'), 558 'Scr64': cntrlReg('MISCREG_SCR_EL3'), 559 'Sctlr': cntrlRegNC('MISCREG_SCTLR'), 560 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'), 561 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'), 562 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'), 563 564 #Register fields for microops 565 'URa' : intReg('ura'), 566 'XURa' : intRegX64('ura'), 567 'WURa' : intRegW64('ura'), 568 'IWRa' : intRegIWPC('ura'), 569 'Fa' : vectorElem('ura / 4', 'ura % 4'), 570 'URb' : intReg('urb'), 571 'XURb' : intRegX64('urb'), 572 'URc' : intReg('urc'), 573 'XURc' : intRegX64('urc'), 574 575 #Memory Operand 576 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), 577 578 #PCState fields 579 'RawPC': pcStateReg('pc', srtPC), 580 'PC': pcStateReg('instPC', srtPC), 581 'NPC': pcStateReg('instNPC', srtPC), 582 'pNPC': pcStateReg('instNPC', srtEPC), 583 'IWNPC': pcStateReg('instIWNPC', srtPC), 584 'Thumb': pcStateReg('thumb', srtPC), 585 'NextThumb': pcStateReg('nextThumb', srtMode), 586 'NextJazelle': pcStateReg('nextJazelle', srtMode), 587 'NextItState': pcStateReg('nextItstate', srtMode), 588 'Itstate': pcStateReg('itstate', srtMode), 589 'NextAArch64': pcStateReg('nextAArch64', srtMode), 590 591 #Register operands depending on a field in the instruction encoding. These 592 #should be avoided since they may not be portable across different 593 #encodings of the same instruction. 594 'Rd': intReg('RD'), 595 'Rm': intReg('RM'), 596 'Rs': intReg('RS'), 597 'Rn': intReg('RN'), 598 'Rt': intReg('RT') 599}}; 600